ppu_dispctl test for valid VGA signal using DMT 640x480 @ 60

1 files changed, 35 insertions, 0 deletions

diff --git a/basys3/basys3.srcs/ppu_dispctl_demo.xdc b/basys3/basys3.srcs/ppu_dispctl_demo.xdc
new file mode 100644
index 0000000..44f2300
--- /dev/null
+++ b/basys3/basys3.srcs/ppu_dispctl_demo.xdc
@@ -0,0 +1,35 @@
+set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports CLK100]
+set_property IOSTANDARD LVCMOS33 [get_ports {G[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {G[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {G[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {G[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports HSYNC]
+set_property IOSTANDARD LVCMOS33 [get_ports {R[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {R[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {R[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {R[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports VSYNC]
+set_property PACKAGE_PIN W5 [get_ports CLK100]
+set_property PACKAGE_PIN P19 [get_ports HSYNC]
+set_property PACKAGE_PIN R19 [get_ports VSYNC]
+
+
+set_property PACKAGE_PIN J18 [get_ports {B[3]}]
+set_property PACKAGE_PIN K18 [get_ports {B[2]}]
+set_property PACKAGE_PIN L18 [get_ports {B[1]}]
+set_property PACKAGE_PIN N18 [get_ports {B[0]}]
+set_property PACKAGE_PIN D17 [get_ports {G[3]}]
+set_property PACKAGE_PIN G17 [get_ports {G[2]}]
+set_property PACKAGE_PIN H17 [get_ports {G[1]}]
+set_property PACKAGE_PIN J17 [get_ports {G[0]}]
+set_property PACKAGE_PIN N19 [get_ports {R[3]}]
+set_property PACKAGE_PIN J19 [get_ports {R[2]}]
+set_property PACKAGE_PIN H19 [get_ports {R[1]}]
+set_property PACKAGE_PIN G19 [get_ports {R[0]}]
+
+set_property PACKAGE_PIN T18 [get_ports RESET]
+set_property IOSTANDARD LVCMOS33 [get_ports RESET]