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authorlonkaars <loek@pipeframe.xyz>2023-03-08 22:31:26 +0100
committerlonkaars <loek@pipeframe.xyz>2023-03-08 22:31:26 +0100
commit2a9b5d2ee3f8661a47849d574fdda6922568300d (patch)
treebc445f220384ba3709592d477da9b8ac72c7cb11 /basys3/basys3.srcs/ppu_dispctl.vhd
parent1e6f7c387dcaf0860988344d08cc4293b7132363 (diff)
ppu_dispctl test for valid VGA signal using DMT 640x480 @ 60
Diffstat (limited to 'basys3/basys3.srcs/ppu_dispctl.vhd')
-rw-r--r--basys3/basys3.srcs/ppu_dispctl.vhd6
1 files changed, 3 insertions, 3 deletions
diff --git a/basys3/basys3.srcs/ppu_dispctl.vhd b/basys3/basys3.srcs/ppu_dispctl.vhd
index 725a6f2..a70a2e7 100644
--- a/basys3/basys3.srcs/ppu_dispctl.vhd
+++ b/basys3/basys3.srcs/ppu_dispctl.vhd
@@ -82,9 +82,9 @@ begin
U_POS_Y <= resize(N_POS_Y / 2, U_POS_Y'length);
ADDR_O <= std_logic_vector(resize(U_POS_X, ADDR_I'length)) when U_POS_Y(0) = '0' else std_logic_vector(resize(U_POS_X, ADDR_I'length) + PPU_SCREEN_WIDTH);
- RO <= DATA_O(11 downto 8);
- GO <= DATA_O(7 downto 4);
- BO <= DATA_O(3 downto 0);
+ RO <= DATA_O(11 downto 8) when NACTIVE = '1' else (others => '0');
+ GO <= DATA_O(7 downto 4) when NACTIVE = '1' else (others => '0');
+ BO <= DATA_O(3 downto 0) when NACTIVE = '1' else (others => '0');
scanline_buffer : component ppu_dispctl_slbuf port map(
clka => CLK,