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authorlonkaars <loek@pipeframe.xyz>2023-02-24 12:15:32 +0100
committerlonkaars <loek@pipeframe.xyz>2023-02-24 12:15:32 +0100
commitfd4732181317907d51be645f75d138c2176a8e3b (patch)
tree925fc3a51912d946bec843fe5342e8cac9535e6e /basys3/basys3.srcs/ppu_comp.vhd
parente7fbeb1a6071db070c4c2b21c4c5ed70d53e269b (diff)
parentb2190241fccdfbf28d6068c9f0d2179aec285528 (diff)
merge #16
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+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 23.02.2023 10:31:25
+-- Design Name:
+-- Module Name: ppu_comp - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ppu_consts.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ppu_comp is
+ Port (
+ FG_HIT: in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0);
+ BG_EN: out std_logic;
+ FG_EN: out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0));
+
+end ppu_comp;
+
+architecture Behavioral of ppu_comp is
+signal FG_HIT_Empty : std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0');
+begin
+ process (FG_HIT)
+ variable HIT : BOOLEAN := FALSE;
+ begin
+ -- check if fg_hit is not empty
+ if FG_HIT /= FG_HIT_Empty then
+ BG_EN <= '0';
+ FOR I IN 0 TO PPU_FG_SPRITE_COUNT-1 LOOP
+ -- if fg_hit is the first one then enable it
+ IF(FG_HIT(I) = '1' AND HIT = FALSE) THEN
+ FG_EN(I) <= '1';
+ HIT := TRUE;
+ ELSE
+ -- make rest low
+ FG_EN(I) <= '0';
+ END IF;
+ END LOOP;
+ HIT := FALSE;
+ else
+ BG_EN <= '1';
+ FG_EN <= (others => '0');
+ end if;
+ end process;
+end Behavioral;