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authorlonkaars <loek@pipeframe.xyz>2023-03-10 16:09:10 +0100
committerlonkaars <loek@pipeframe.xyz>2023-03-10 16:09:10 +0100
commit80e2732c8f208f3f225a2a5c0e540bc50fceab5d (patch)
treed3fdc507b7d67d265b98585518ee85743c447d74 /basys3/basys3.srcs/ppu.vhd
parent6cd57aed4fa4d8617c602a0efa4856ea58aa2e0e (diff)
top.vhdl
Diffstat (limited to 'basys3/basys3.srcs/ppu.vhd')
-rw-r--r--basys3/basys3.srcs/ppu.vhd10
1 files changed, 4 insertions, 6 deletions
diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index 9cf1bc0..d6407df 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -14,7 +14,7 @@ entity ppu is port(
DATA : in std_logic_vector(PPU_RAM_BUS_DATA_WIDTH-1 downto 0);
R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0);
NVSYNC, NHSYNC : out std_logic; -- native VGA out
- TVSYNC, TVBLANK, THSYNC, THBLANK : out std_logic); -- tiny VGA out
+ TVBLANK, THBLANK : out std_logic); -- tiny VGA out
end ppu;
architecture Behavioral of ppu is
@@ -189,7 +189,7 @@ architecture Behavioral of ppu is
signal BG_SHIFT_X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0);
signal BG_SHIFT_Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0);
signal FG_FETCH : std_logic;
- signal TINY_VBLANK, TINY_VSYNC, TINY_HBLANK, TINY_HSYNC,
+ signal TINY_VBLANK, TINY_HBLANK,
NATIVE_VSYNC, NATIVE_HSYNC : std_logic;
begin
SYSCLK <= CLK100;
@@ -205,9 +205,7 @@ begin
PAL_AI <= (others => '0');
TVBLANK <= TINY_VBLANK;
- TVSYNC <= TINY_VSYNC;
THBLANK <= TINY_HBLANK;
- THSYNC <= TINY_HSYNC;
NVSYNC <= NATIVE_VSYNC;
NHSYNC <= NATIVE_HSYNC;
@@ -334,9 +332,9 @@ begin
RESET => SYSRST,
X => X,
Y => Y,
- VSYNC => TINY_VSYNC,
+ VSYNC => open,
VBLANK => TINY_VBLANK,
- HSYNC => TINY_HSYNC,
+ HSYNC => open,
HBLANK => TINY_HBLANK);
native_vga_signal_generator : component ppu_vga_native port map( -- native vga signal generator (upscaler)