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authorlonkaars <loek@pipeframe.xyz>2023-02-20 15:31:12 +0100
committerlonkaars <loek@pipeframe.xyz>2023-02-20 15:31:12 +0100
commit29108f38c5f885412b0a75ae46b85720946cfdb5 (patch)
tree6b78d25a98898db4a92d659d84ba1840ee6de0ee /basys3/basys3.srcs/ppu.vhd
parent77870488404563df2c18e4ec4719e767fff98919 (diff)
update TMM data width + update memory map (WIP ppu_sprite_bg)
Diffstat (limited to 'basys3/basys3.srcs/ppu.vhd')
-rw-r--r--basys3/basys3.srcs/ppu.vhd4
1 files changed, 2 insertions, 2 deletions
diff --git a/basys3/basys3.srcs/ppu.vhd b/basys3/basys3.srcs/ppu.vhd
index acf546f..c798400 100644
--- a/basys3/basys3.srcs/ppu.vhd
+++ b/basys3/basys3.srcs/ppu.vhd
@@ -79,7 +79,7 @@ architecture Behavioral of ppu is
end component;
component ppu_sprite_bg port( -- background sprite
-- inputs
- CLK : in std_logic; -- system clock
+ CLK : in std_logic; -- pipeline clock
RESET : in std_logic; -- reset clock counter
OE : in std_logic; -- output enable (of CIDX)
X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
@@ -100,7 +100,7 @@ architecture Behavioral of ppu is
end component;
component ppu_sprite_fg port( -- foreground sprite
-- inputs
- CLK : in std_logic; -- system clock
+ CLK : in std_logic; -- pipeline clock
RESET : in std_logic; -- reset internal memory and clock counters
OE : in std_logic; -- output enable (of CIDX)
X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x