diff options
| author | lonkaars <loek@pipeframe.xyz> | 2023-02-21 16:40:08 +0100 |
|---|---|---|
| committer | lonkaars <loek@pipeframe.xyz> | 2023-02-21 16:40:08 +0100 |
| commit | 3bb4bbb64bfc9263520b68cac5b3c6caaa37d19d (patch) | |
| tree | 672ed4361963a8931406d54e8d8f4883fd4e890e /basys3/basys3.srcs/er_ram.vhd | |
| parent | 9ab2a3d4b4304a4f489e100a6b66d6ee414143e7 (diff) | |
WIP ppu foreground sprite component
Diffstat (limited to 'basys3/basys3.srcs/er_ram.vhd')
| -rw-r--r-- | basys3/basys3.srcs/er_ram.vhd | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/basys3/basys3.srcs/er_ram.vhd b/basys3/basys3.srcs/er_ram.vhd index f106d4e..66f905b 100644 --- a/basys3/basys3.srcs/er_ram.vhd +++ b/basys3/basys3.srcs/er_ram.vhd @@ -21,8 +21,8 @@ end er_ram; architecture Behavioral of er_ram is component er_ram_mod generic( - W : natural := 1; -- module data width - ADDR_W : natural := 1; -- address width + W : natural := DATA_W; -- module data width + ADDR_W : natural := ADDR_W; -- address width ADDR_M : std_logic_vector(ADDR_W-1 downto 0) := (others => '0')); -- address match port( CLK : in std_logic; -- clock @@ -36,12 +36,12 @@ architecture Behavioral of er_ram is begin REG <= INT_REG; - registers : for idx in ADDR_LOW to ADDR_LOW + ADDR_RANGE - 1 generate + registers : for idx in 0 to ADDR_RANGE - 1 generate reg : component er_ram_mod generic map( W => DATA_W, ADDR_W => ADDR_W, - ADDR_M => std_logic_vector(to_unsigned(idx, ADDR_W))) + ADDR_M => std_logic_vector(to_unsigned(ADDR_LOW + idx, ADDR_W))) port map( CLK => CLK, RST => RST, |