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authorUnavailableDev <69792062+UnavailableDev@users.noreply.github.com>2023-02-22 11:17:49 +0100
committerGitHub <noreply@github.com>2023-02-22 11:17:49 +0100
commit6e1cce415050ca82f8243b5ae5a8d1564f311ee8 (patch)
tree98f0192011cde1251d38be5573292b5a130e1f1a /basys3/basys3.srcs/apu_note_to_frequency.vhd
parent9b84c25a53b7269228743e398b13c19af505226b (diff)
parent936bb51ceba0427aa1a36fcd6398d56a1a99e160 (diff)
Merge pull request #15 from UnavailableDev/dev
APU LUT / Calulations
Diffstat (limited to 'basys3/basys3.srcs/apu_note_to_frequency.vhd')
-rw-r--r--basys3/basys3.srcs/apu_note_to_frequency.vhd44
1 files changed, 24 insertions, 20 deletions
diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd
index 7e02c75..8a7b3d6 100644
--- a/basys3/basys3.srcs/apu_note_to_frequency.vhd
+++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd
@@ -5,31 +5,35 @@ use ieee.numeric_std.all;
entity apu_note_to_frequency is port (
-- clk : in std_logic;
-- rst : in std_logic;
- data : in std_logic_vector(7 downto 0);
- freq : out std_logic_vector(11 downto 0)); --frequency
+ data : in std_logic_vector(6 downto 0);
+ freq : out std_logic_vector(11 downto 0)); -- frequency
end entity;
architecture Behavioral of apu_note_to_frequency is
signal buff_small: std_logic_vector(7 downto 0) := (others => '0');
- signal buff: std_logic_vector(15 downto 0) := (others => '0');
+ signal buff: std_logic_vector(11 downto 0) := (others => '0');
signal shift: integer;
begin
- shift <= to_integer(unsigned(data(2 downto 0)));
- buff_small <=
- x"f0" when data(7 downto 3) = (x"c" & '0') else -- C 496
- x"d0" when data(7 downto 3) = (x"c" & '1') else -- C# 464
- x"b0" when data(7 downto 3) = (x"d" & '0') else -- D 432
- x"a0" when data(7 downto 3) = (x"d" & '1') else -- D# 416
- x"80" when data(7 downto 3) = (x"e" & '0') else -- E 384
- x"70" when data(7 downto 3) = (x"f" & '0') else -- F 368
- x"58" when data(7 downto 3) = (x"f" & '1') else -- F# 344
- x"40" when data(7 downto 3) = (x"8" & '0') else -- G 320
- x"30" when data(7 downto 3) = (x"8" & '1') else -- G# 304
- x"20" when data(7 downto 3) = (x"a" & '0') else -- A 288
- x"10" when data(7 downto 3) = (x"a" & '1') else -- A# 272
- x"00" when data(7 downto 3) = (x"b" & '0') else -- B 256
- x"01";
- buff <= x"1" & buff_small;
- freq <= (others => '0') & buff(15 downto shift); -- bitshift values out (or div by powers of 2)
+ shift <= to_integer(unsigned( data(2 downto 0) ));
+
+ buff <=
+ x"1F0" when data(6 downto 3) = (x"1") else -- C 496
+ x"1D0" when data(6 downto 3) = (x"2") else -- C#/Db 464
+ x"1B0" when data(6 downto 3) = (x"3") else -- D 432
+ x"1A0" when data(6 downto 3) = (x"4") else -- D#/Eb 416
+ x"180" when data(6 downto 3) = (x"5") else -- E 384
+ x"170" when data(6 downto 3) = (x"6") else -- F 368
+ x"158" when data(6 downto 3) = (x"7") else -- F#/Gb 344
+ x"140" when data(6 downto 3) = (x"8") else -- G 320
+ x"130" when data(6 downto 3) = (x"9") else -- G#/Ab 304
+ x"120" when data(6 downto 3) = (x"A") else -- A 288
+ x"110" when data(6 downto 3) = (x"B") else -- A#/Bb 272
+ x"100" when data(6 downto 3) = (x"C") else -- B 256
+ x"000";
+
+ -- buff <= x"1" & buff_small;
+ freq <= std_logic_vector( shift_right(unsigned(buff), shift) );
+ -- freq <= (others => '0') & buff(11 downto shift); -- bitshift values out (or div by powers of 2) -- TODO: NO WORKY!!! (concat (others => '0');)
+
end architecture;