diff options
author | UnavailableDev <ggwildplay@gmail.com> | 2023-03-03 11:52:26 +0100 |
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committer | UnavailableDev <ggwildplay@gmail.com> | 2023-03-03 11:52:26 +0100 |
commit | 01a693ff474a20e41e697fb68cb51a44662ac737 (patch) | |
tree | 334e25d4cd766c2e81532a0a28ccaa3735f1ceac /basys3/basys3.srcs/apu_note_to_frequency.vhd | |
parent | 7c9468e7165aac2724a8bad19e950ca435f68316 (diff) |
apu constants cleanup
Diffstat (limited to 'basys3/basys3.srcs/apu_note_to_frequency.vhd')
-rw-r--r-- | basys3/basys3.srcs/apu_note_to_frequency.vhd | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd index 810cef9..48defa3 100644 --- a/basys3/basys3.srcs/apu_note_to_frequency.vhd +++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd @@ -2,6 +2,9 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +library work; +use work.apu_consts.all; + entity apu_note_to_frequency is port ( -- clk : in std_logic; -- rst : in std_logic; @@ -10,7 +13,6 @@ entity apu_note_to_frequency is port ( end entity; architecture Behavioral of apu_note_to_frequency is - signal buff_small : std_logic_vector(7 downto 0) := (others => '0'); signal buff : std_logic_vector(15 downto 0) := (others => '0'); signal shift : integer; begin @@ -18,7 +20,7 @@ begin shift <= to_integer(unsigned( data(2 downto 0) )); buff <= - x"1F0" when data(6 downto 3) = (x"1") else -- C 496 + x"1F0" when data(6 downto 3) = (x"1") else -- C 496 --values are calculated for 8kHz sample rate x"1D0" when data(6 downto 3) = (x"2") else -- C#/Db 464 x"1B0" when data(6 downto 3) = (x"3") else -- D 432 x"1A0" when data(6 downto 3) = (x"4") else -- D#/Eb 416 @@ -32,8 +34,6 @@ begin x"100" when data(6 downto 3) = (x"C") else -- B 256 x"000"; - -- buff <= x"1" & buff_small; - freq <= std_logic_vector( shift_right(unsigned(buff), shift) ); - -- freq <= (others => '0') & buff(11 downto shift); -- bitshift values out (or div by powers of 2) -- TODO: NO WORKY!!! (concat (others => '0');) + freq <= std_logic_vector( shift_right(unsigned(buff), natural(shift)) ); -- TODO: MAYBE WORKY??? end architecture; |