initial merge of #26

3 files changed, 0 insertions, 183 deletions

diff --git a/GameLogic/vhdl/cnts.xdc b/GameLogic/vhdl/cnts.xdc
deleted file mode 100644
index b8c0604..0000000
--- a/GameLogic/vhdl/cnts.xdc
+++ /dev/null
@@ -1,72 +0,0 @@
-set_property PACKAGE_PIN W5 [get_ports clk100]

-set_property PACKAGE_PIN P19 [get_ports hsync]

-set_property PACKAGE_PIN R19 [get_ports vsync]

-set_property PACKAGE_PIN N18 [get_ports {blue[3]}]

-set_property PACKAGE_PIN L18 [get_ports {blue[2]}]

-set_property PACKAGE_PIN K18 [get_ports {blue[1]}]

-set_property PACKAGE_PIN J18 [get_ports {blue[0]}]

-set_property PACKAGE_PIN J17 [get_ports {green[3]}]

-set_property PACKAGE_PIN H17 [get_ports {green[2]}]

-set_property PACKAGE_PIN G17 [get_ports {green[1]}]

-set_property PACKAGE_PIN D17 [get_ports {green[0]}]

-set_property PACKAGE_PIN G19 [get_ports {red[3]}]

-set_property PACKAGE_PIN H19 [get_ports {red[2]}]

-set_property PACKAGE_PIN J19 [get_ports {red[1]}]

-set_property PACKAGE_PIN N19 [get_ports {red[0]}]

-set_property IOSTANDARD LVCMOS33 [get_ports clk100]

-set_property IOSTANDARD LVCMOS33 [get_ports hsync]

-set_property IOSTANDARD LVCMOS33 [get_ports vsync]

-set_property IOSTANDARD LVCMOS33 [get_ports {blue[3]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {blue[2]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {blue[0]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {blue[1]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {green[3]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {green[2]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {green[1]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {red[3]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {red[2]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {red[1]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {red[0]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {green[0]}]

-

-set_property PACKAGE_PIN T18 [get_ports resetButton]

-set_property IOSTANDARD LVCMOS33 [get_ports resetButton]

-

-set_property PACKAGE_PIN A15 [get_ports clkSPI]

-set_property PACKAGE_PIN C15 [get_ports csSPI]

-set_property PACKAGE_PIN A17 [get_ports dataSPI]

-set_property IOSTANDARD LVCMOS33 [get_ports dataSPI]

-set_property IOSTANDARD LVCMOS33 [get_ports csSPI]

-set_property IOSTANDARD LVCMOS33 [get_ports clkSPI]

-set_property PACKAGE_PIN L1 [get_ports {led[15]}]

-set_property PACKAGE_PIN P1 [get_ports {led[14]}]

-set_property PACKAGE_PIN N3 [get_ports {led[13]}]

-set_property PACKAGE_PIN P3 [get_ports {led[12]}]

-set_property PACKAGE_PIN U3 [get_ports {led[11]}]

-set_property PACKAGE_PIN W3 [get_ports {led[10]}]

-set_property PACKAGE_PIN V3 [get_ports {led[9]}]

-set_property PACKAGE_PIN V13 [get_ports {led[8]}]

-set_property PACKAGE_PIN V14 [get_ports {led[7]}]

-set_property PACKAGE_PIN U14 [get_ports {led[6]}]

-set_property PACKAGE_PIN U15 [get_ports {led[5]}]

-set_property PACKAGE_PIN W18 [get_ports {led[4]}]

-set_property PACKAGE_PIN V19 [get_ports {led[3]}]

-set_property PACKAGE_PIN U19 [get_ports {led[2]}]

-set_property PACKAGE_PIN E19 [get_ports {led[1]}]

-set_property PACKAGE_PIN U16 [get_ports {led[0]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]

-set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]

diff --git a/GameLogic/vhdl/constraints.txt b/GameLogic/vhdl/constraints.txt
deleted file mode 100644
index f254cdd..0000000
--- a/GameLogic/vhdl/constraints.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-set_property PACKAGE_PIN A15 [get_ports clkSPI]

-set_property PACKAGE_PIN C15 [get_ports csSPI]

-set_property PACKAGE_PIN A17 [get_ports dataSPI]

-set_property IOSTANDARD LVCMOS33 [get_ports dataSPI]

-set_property IOSTANDARD LVCMOS33 [get_ports csSPI]

-set_property IOSTANDARD LVCMOS33 [get_ports clkSPI]
\ No newline at end of file
diff --git a/GameLogic/vhdl/spiSlave.vhd b/GameLogic/vhdl/spiSlave.vhd
deleted file mode 100644
index 7cf3e63..0000000
--- a/GameLogic/vhdl/spiSlave.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 15.02.2023 21:09:16
--- Design Name: 
--- Module Name: top - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity spiSlave is
-  Port (    clkBoard : in std_logic; -- clock basys3 100MHz
-            clkSPI : in std_logic; -- incoming clock of SPI 
-            dataSPI : in std_logic; -- incoming data of SPI
-            csSPI : in std_logic;   -- incoming select of SPI
-            dataRead : out std_logic_vector(23 downto 0) := (others => '0') --  data read
-
-  );
-end spiSlave;
-
-architecture Behavioral of spiSlave is
-    signal PulseFF0,PulseFF1,PulseFF2,PulseFF3 : std_logic := '0';     -- signal for metastability synchronizer of clk SPI
-    signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0';          -- signal for metastability synchronizer of data SPI
-    signal ssFF0,ssFF1,ssFF2,ssFF3 : std_logic := '0';                  -- signal for metastability synchronizer of slave select SPI
-    
-    signal data : std_logic_vector(23 downto 0) := (others => '0');      -- signal to store incomming data of dataSPI (2x 8bit)
-    signal counter : integer := 23;                                      --counter for data position
-    signal enable : std_logic := '0';                                   -- enable signal if slave is selected
-begin
-    
-    process (clkBoard)
-    begin
-        
-        if rising_edge(clkBoard) then       
-            -- flip flop for clk SPI to synchronise a
-            PulseFF0 <= clkSPI;
-            PulseFF1 <= PulseFF0;
-            PulseFF2 <= PulseFF1;
-            PulseFF3 <= PulseFF2;  
-            -- flip flop for data SPI to synchronise      
-            dataFF0 <= dataSPI;
-            dataFF1 <= dataFF0;
-            dataFF2 <= dataFF1;
-            dataFF3 <= dataFF2;             
-             -- flip flop for slave select SPI to synchronise                  
-            ssFF0 <= csSPI;
-            ssFF1 <= ssFF0;
-            ssFF2 <= ssFF1;
-            ssFF3 <= ssFF2; 
-            -- check if slave select signal has falling edge (slave is selected by master)    
-            if(ssFF3 = '1' and ssFF2 = '0') then
-            --reset counter if true
-                counter <= 23;
-            --disable data read if rising edge (slave is not selected)    
-            elsif (ssFF3 = '0' and ssFF2 = '1') then
-                enable <= '0';
-            end if;            
-            --check if synchronised slave select signal is falling edge or data read is enabled
-            if(ssFF3 = '1' and ssFF2 = '0') or enable = '1' then
-                enable <= '1';                                          --enable data read
-                if (PulseFF3 = '0' and PulseFF2 = '1') then             -- check for rising edge of clk SPI
-                    if counter > -1 then                                
-                        counter <= counter - 1;
-                        -- data transfer into vector  
-                        data(counter) <= dataFF3;
-                    end if;
-                end if;
-                --check if counter is done
-                if counter = -1 then
-                    counter <= 23;       --reset counter 
-                    dataRead <= data;             
-                end if;      
-            elsif (enable = '0') then
-            --dataRead <= data;
-            
-            end if;
-
-        end if;
-
-    end process;
-
-end Behavioral;