update style guide and format code

7 files changed, 346 insertions, 471 deletions

diff --git a/basys3/basys3.srcs/ppu_comp.vhd b/basys3/basys3.srcs/ppu_comp.vhd
index 1ea315e..e79738f 100644
--- a/basys3/basys3.srcs/ppu_comp.vhd
+++ b/basys3/basys3.srcs/ppu_comp.vhd
@@ -1,67 +1,36 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 23.02.2023 10:31:25
--- Design Name: 
--- Module Name: ppu_comp - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
 use work.ppu_consts.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
-entity ppu_comp is
- Port ( 
- 		FG_HIT: in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0);
-		BG_EN: out std_logic;
-		FG_EN: out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0));
-		
+entity ppu_comp is port ( 
+	FG_HIT : in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0);
+	BG_EN : out std_logic;
+	FG_EN : out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0));
 end ppu_comp;
 
 architecture Behavioral of ppu_comp is
-signal FG_HIT_Empty : std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0');
+	signal FG_HIT_EMPTY : std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0');
 begin
-    process (FG_HIT)
-    variable HIT : BOOLEAN := FALSE;
-    begin
-        -- check if fg_hit is not empty
-        if FG_HIT /= FG_HIT_Empty then
-            BG_EN <= '0';
-            FOR I IN 0 TO PPU_FG_SPRITE_COUNT-1 LOOP
-                -- if fg_hit is the first one then enable it
-                IF(FG_HIT(I) = '1' AND HIT = FALSE) THEN
-                    FG_EN(I) <= '1';
-                    HIT := TRUE;
-                ELSE
-                    -- make rest low
-                    FG_EN(I) <= '0';
-                END IF;
-            END LOOP;
-            HIT := FALSE;
-        else
-            BG_EN <= '1';
-            FG_EN <= (others => '0');
-        end if;
-    end process;
+	process (FG_HIT)
+		variable HIT : boolean := false;
+	begin
+		-- check if FG_HIT is not empty
+		if FG_HIT /= FG_HIT_EMPTY then
+			BG_EN <= '0';
+			for i in 0 to PPU_FG_SPRITE_COUNT-1 loop
+				-- if FG_HIT is the first one then enable it
+				if(FG_HIT(i) = '1' and HIT = false) then
+					FG_EN(i) <= '1';
+					HIT := true;
+				else
+					-- make rest low
+					FG_EN(i) <= '0';
+				end if;
+			end loop;
+			HIT := false;
+		else
+			BG_EN <= '1';
+			FG_EN <= (others => '0');
+		end if;
+	end process;
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_comp_tb.vhd b/basys3/basys3.srcs/ppu_comp_tb.vhd
index e8f6893..be4c2e3 100644
--- a/basys3/basys3.srcs/ppu_comp_tb.vhd
+++ b/basys3/basys3.srcs/ppu_comp_tb.vhd
@@ -8,37 +8,33 @@ entity ppu_comp_tb is
 end ppu_comp_tb;
 
 architecture behavioral of ppu_comp_tb is
-COMPONENT ppu_comp
-        port (
- 		FG_HIT: in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0);
-		BG_EN: out std_logic;
-		FG_EN: out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0));
-end component;
-
-signal  FG_HIT: std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0');
-signal	BG_EN: std_logic  := '0';
-signal	FG_EN: std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0');
+	component ppu_comp port (
+		FG_HIT : in std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0);
+		BG_EN : out std_logic;
+		FG_EN : out std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0));
+	end component;
+	signal FG_HIT : std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0');
+	signal BG_EN : std_logic := '0';
+	signal FG_EN : std_logic_vector(PPU_FG_SPRITE_COUNT-1 downto 0) := (others => '0');
 begin
-UUT : ppu_comp port map (
-FG_HIT => FG_HIT,
-BG_EN  => BG_EN,
-FG_EN  => FG_EN
-);
- TB : PROCESS
- BEGIN
-    FG_HIT <= (OTHERS => '0');
-    wait for 1 ps;
-    FG_HIT(6) <= '1';
-    FG_HIT(5) <= '1';
-    FG_HIT(100) <= '1';
-    wait for 1 ps;
-    
-    FG_HIT(0) <= '1';
-    wait for 1 ps;
-    FG_HIT <= (OTHERS => '0');
-    wait for 1 ps;
-    
-    
-    wait;
- END PROCESS;
+	uut : ppu_comp port map (
+		FG_HIT => FG_HIT,
+		BG_EN => BG_EN,
+		FG_EN => FG_EN
+	);
+	tb : process
+	begin
+		FG_HIT <= (others => '0');
+		wait for 1 ps;
+		FG_HIT(6) <= '1';
+		FG_HIT(5) <= '1';
+		FG_HIT(100) <= '1';
+		wait for 1 ps;
+
+		FG_HIT(0) <= '1';
+		wait for 1 ps;
+		FG_HIT <= (others => '0');
+		wait for 1 ps;
+		wait;
+	end process;
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_plut.vhd b/basys3/basys3.srcs/ppu_plut.vhd
index d03da1f..d2e132e 100644
--- a/basys3/basys3.srcs/ppu_plut.vhd
+++ b/basys3/basys3.srcs/ppu_plut.vhd
@@ -1,48 +1,20 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 23.02.2023 11:03:27
--- Design Name: 
--- Module Name: ppu_plut - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
 use work.ppu_consts.all;
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-use IEEE.NUMERIC_STD.ALL;
+use ieee.numeric_std.all;
 use ieee.std_logic_unsigned.all;
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
-entity ppu_plut is
-  Port ( 
-        CLK: in std_logic; -- system clock
-		CIDX: in std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- color in
-		RESET: in std_logic;
+entity ppu_plut is port ( 
+	CLK : in std_logic; -- system clock
+	CIDX : in std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0); -- color in
+	RESET : in std_logic;
+
+	-- internal memory block (AUX)
+	PAL_WEN : in std_logic; -- VRAM PAL write enable
+	PAL_ADDR : in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); -- VRAM PAL address
+	PAL_DATA : in std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0); -- VRAM PAL data
 
-		-- internal memory block (AUX)
-		PAL_WEN: in std_logic; -- VRAM PAL write enable
-		PAL_ADDR: in std_logic_vector(PPU_PAL_ADDR_WIDTH-1 downto 0); -- VRAM PAL address
-		PAL_DATA: in std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0); -- VRAM PAL data
-		
-		R,G,B: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0)); -- VGA color out
+	R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0)); -- VGA color out
 end ppu_plut;
 
 architecture Behavioral of ppu_plut is
@@ -61,8 +33,8 @@ architecture Behavioral of ppu_plut is
 			REG : out std_logic_vector((ADDR_RANGE*DATA_W)-1 downto 0)); -- exposed register output
 	end component;
 	
-	SIGNAL PLUT : std_logic_vector((64 * PPU_PAL_DATA_WIDTH)-1 downto 0) := (others => '0');
-	SIGNAL CHECK_ZERO_CIDX   :  std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0');-- color in
+	signal PLUT : std_logic_vector((64 * PPU_PAL_DATA_WIDTH)-1 downto 0) := (others => '0');
+	signal CHECK_ZERO_CIDX : std_logic_vector(PPU_PALETTE_CIDX_WIDTH-1 downto 0) := (others => '0'); -- color in
 begin
 	RAM : component er_ram port map(
 		CLK => CLK,
@@ -72,28 +44,26 @@ begin
 		DATA => PAL_DATA,
 		REG => PLUT);
 
-
-    process(CLK,RESET)
-    	VARIABLE  COLOR   :  std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0) := (others => '0');-- COLORS RGB IN
-    	VARIABLE CIDX_INT : INTEGER := 0;
-    begin
-        IF(RESET = '1') THEN
-            PLUT <= (others => '0');
-        ELSE
-            IF rising_edge (CLK) THEN
-                IF (CIDX /= CHECK_ZERO_CIDX) THEN
-                    CIDX_INT := TO_INTEGER(UNSIGNED(CIDX));
-                    COLOR := PLUT((12 * CIDX_INT) + 11 DOWNTO (12*CIDX_INT));
-                    R <= COLOR(11 DOWNTO  8);
-                    G <= COLOR(7  DOWNTO  4);
-                    B <= COLOR(3  DOWNTO  0);
-                ELSE
-                    R <= X"0";
-                    G <= X"0";
-                    B <= X"0";
-                END IF;
-            END IF;
-        END IF;
-    end process;
-
+	process(CLK, RESET)
+		variable COLOR : std_logic_vector(PPU_PAL_DATA_WIDTH-1 downto 0) := (others => '0'); -- COLORS RGB IN
+		variable CIDX_INT : integer := 0;
+	begin
+		if RESET = '1' then
+			PLUT <= (others => '0');
+		else
+			if rising_edge (CLK) then
+				if (CIDX /= CHECK_ZERO_CIDX) then
+					CIDX_INT := to_integer(unsigned(CIDX));
+					COLOR := PLUT((12 * CIDX_INT) + 11 downto (12*CIDX_INT));
+					R <= COLOR(11 downto  8);
+					G <= COLOR(7 downto 4);
+					B <= COLOR(3 downto 0);
+				else
+					R <= x"0";
+					G <= x"0";
+					B <= x"0";
+				end if;
+			end if;
+		end if;
+	end process;
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_vga_native.vhd b/basys3/basys3.srcs/ppu_vga_native.vhd
index f5d9809..47288e9 100644
--- a/basys3/basys3.srcs/ppu_vga_native.vhd
+++ b/basys3/basys3.srcs/ppu_vga_native.vhd
@@ -1,125 +1,95 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 22.02.2023 13:20:47
--- Design Name: 
--- Module Name: ppu_vga_native - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
 use work.ppu_consts.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
 
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+entity ppu_vga_native is port (
+	CLK: in std_logic; -- system clock
+	RESET: in std_logic;
 
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
+	X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+	Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
+	PREADY: in std_logic; -- current pixel ready (pixel color is stable)
+	RI,GI,BI: in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in
 
-entity ppu_vga_native is
- Port (	CLK: in std_logic; -- system clock
-		RESET: in std_logic;
-
-		X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-		Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-		PREADY: in std_logic; -- current pixel ready (pixel color is stable)
-		RI,GI,BI: in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in
-		
-		RO,GO,BO: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
-		VSYNC, HSYNC: out std_logic); -- VGA sync outputs
+	RO,GO,BO: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
+	VSYNC, HSYNC: out std_logic); -- VGA sync outputs
 end ppu_vga_native;
 
 architecture Behavioral of ppu_vga_native is
-  type line_buffer is array(319 downto 0) of std_logic_vector(11 downto 0);
-  signal ram_x0 : line_buffer; -- buffer 0
-  signal ram_x1: line_buffer; -- buffer 1
-  signal hcount: STD_LOGIC_VECTOR(9 downto 0):= (others => '0');
-  signal vcount: STD_LOGIC_VECTOR(9 downto 0):= (others => '0');
-  signal clkCounter: STD_LOGIC_VECTOR(1 downto 0):= (others => '0');
-  signal rgb_out :  STD_LOGIC_VECTOR(11 downto 0):= (others => '0'); -- output colors
-  signal px : integer; -- conversion for hcount
-  signal py :integer; -- conversion for vcount
-  signal bufferFilledOnbuffer0 : integer;
-  signal bufferFilledOnbuffer1 :integer;
+	type line_buffer is array(319 downto 0) of std_logic_vector(11 downto 0);
+	signal ram_x0 : line_buffer; -- buffer 0
+	signal ram_x1: line_buffer; -- buffer 1
+	signal hcount: std_logic_vector(9 downto 0):= (others => '0');
+	signal vcount: std_logic_vector(9 downto 0):= (others => '0');
+	signal clk_counter: std_logic_vector(1 downto 0):= (others => '0');
+	signal rgb_out : std_logic_vector(11 downto 0):= (others => '0'); -- output colors
+	signal px : integer; -- conversion for hcount
+	signal py :integer; -- conversion for vcount
+	signal buffer_filled_on_buffer0 : integer;
+	signal buffer_filled_on_buffer1 : integer;
 begin
-    process (clk, x, y)
-        variable v_x : integer ; -- integer to hold vector X
-    begin
-        if rising_edge(clk) then
-            clkCounter <= clkCounter + 1;
-            if(clkCounter = "11")then
-                  v_x := TO_INTEGER(unsigned(x) - 72);
-                  if(v_x >= 0 and v_x < 320 and PREADY = '1') then
-                     if(y(0) = '0') then
-                        ram_x0(v_x) <= RI & GI & BI;
-                        if v_x = 319 then
-                            bufferFilledOnbuffer0 <= TO_INTEGER(unsigned(y) - 14);
-                        end if;
-                    else
-                        ram_x1(v_x) <= RI & GI & BI;
-                        if v_x = 319 then
-                            bufferFilledOnbuffer1 <= TO_INTEGER(unsigned(y) - 14);
-                        end if;
-                    end if;          
-                 end if;     
-                -- T display(display data)     
-                if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then
-                    px <= TO_INTEGER(unsigned(hcount) - 144); 
-                    py <= TO_INTEGER(unsigned(vcount) - 31);   
-                    if(bufferFilledonBuffer0 = (py/2)) then
-                        rgb_out <= ram_x0(px/2);
-                    elsif(bufferFilledonbuffer1 = (py/2)) then
-                        rgb_out <= ram_x1(px/2); 
-                
-                    else
-                        rgb_out <= (others => '0');
-                
-                    end if;
-                end if;
-                -- pulse width
-                hsync <= '1';
-                if hcount < 97 then
-                    hsync <= '0';
-                end if;
-                
-                vsync <= '1';
-                if vcount < 3 then
-                    vsync <= '0';
-                end if;
-                
-                -- sync pulse time
-                hcount <= hcount + 1;
-                
-                if hcount = 800 then
-                    vcount <= vcount + 1;
-                    hcount <= (others => '0');
-                end if;
-                
-                if vcount = 521 then
-                    vcount <= (others => '0');
-                end if;
-            end if;
-            
-            -- output colors
-        RO <= rgb_out(11 downto 8);
-        GO <= rgb_out(7 downto 4);
-        BO <= rgb_out(3 downto 0);
-        end if;
-    end process;
+	process (clk, x, y)
+		variable v_x : integer; -- integer to hold vector X
+	begin
+		if rising_edge(clk) then
+			clk_counter <= clk_counter + 1;
+			if clk_counter = "11" then
+				v_x := to_integer(unsigned(x) - 72);
+				if v_x >= 0 and v_x < 320 and PREADY = '1' then
+					if y(0) = '0' then
+						ram_x0(v_x) <= RI & GI & BI;
+						if v_x = 319 then
+							buffer_filled_on_buffer0 <= to_integer(unsigned(y) - 14);
+						end if;
+					else
+						ram_x1(v_x) <= RI & GI & BI;
+						if v_x = 319 then
+							buffer_filled_on_buffer1 <= to_integer(unsigned(y) - 14);
+						end if;
+					end if;
+				end if;
+				-- T display(display data)
+				if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then
+					px <= to_integer(unsigned(hcount) - 144);
+					py <= to_integer(unsigned(vcount) - 31);
+					if buffer_filled_on_buffer0 = (py/2) then
+						rgb_out <= ram_x0(px/2);
+					elsif buffer_filled_on_buffer1 = (py/2) then
+						rgb_out <= ram_x1(px/2);
+					else
+						rgb_out <= (others => '0');
+					end if;
+				end if;
+				-- pulse width
+				hsync <= '1';
+				if hcount < 97 then
+					hsync <= '0';
+				end if;
+
+				vsync <= '1';
+				if vcount < 3 then
+					vsync <= '0';
+				end if;
+
+				-- sync pulse time
+				hcount <= hcount + 1;
+
+				if hcount = 800 then
+					vcount <= vcount + 1;
+					hcount <= (others => '0');
+				end if;
+
+				if vcount = 521 then
+					vcount <= (others => '0');
+				end if;
+			end if;
 
+			-- output colors
+		RO <= rgb_out(11 downto 8);
+		GO <= rgb_out(7 downto 4);
+		BO <= rgb_out(3 downto 0);
+		end if;
+	end process;
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_vga_native_tb.vhd b/basys3/basys3.srcs/ppu_vga_native_tb.vhd
index 3a225d8..06061a0 100644
--- a/basys3/basys3.srcs/ppu_vga_native_tb.vhd
+++ b/basys3/basys3.srcs/ppu_vga_native_tb.vhd
@@ -1,116 +1,89 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 22.02.2023 13:28:57
--- Design Name: 
--- Module Name: ppu_vga_native_tb - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+library unisim;
+use ieee.std_logic_1164.all;
 use work.ppu_consts.all;
-
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use unisim.vcomponents.all;
 
 entity ppu_vga_native_tb is
 end ppu_vga_native_tb;
 
 architecture Behavioral of ppu_vga_native_tb is
-component ppu_vga_native
- Port (	CLK: in std_logic; -- system clock
-		RESET: in std_logic;
+	component ppu_vga_native port (
+		CLK : in std_logic; -- system clock
+		RESET : in std_logic;
+
+		X : in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+		Y : in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
+		PREADY : in std_logic; -- current pixel ready (pixel color is stable)
+		RI,GI,BI : in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in
 
-		X: in std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-		Y: in std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-		PREADY: in std_logic; -- current pixel ready (pixel color is stable)
-		RI,GI,BI: in std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color in
-		
-		RO,GO,BO: out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
-		VSYNC, HSYNC: out std_logic); -- VGA sync outputs
-end component;
-signal clk : std_logic := '0';
-signal rst : std_logic := '0';
-signal Pready : std_logic := '0';
+		RO,GO,BO : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); -- VGA color out
+		VSYNC, HSYNC : out std_logic); -- VGA sync outputs
+	end component;
+	signal CLK : std_logic := '0';
+	signal RST : std_logic := '0';
+	signal PREADY : std_logic := '0';
 
-signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0');
+	signal X : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0');
+	signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0');
 
-signal Xas : integer := 72;
-signal Yas : integer := 14;
-signal counter : std_logic_vector(1 downto 0) := (others => '0');
-signal Y : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0');
-signal RI,GI,BI: std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); -- VGA color in
-signal RO,GO,BO: std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); -- VGA color out
-signal VSYNC, HSYNC:  std_logic := '0';
+	signal RI,GI,BI : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); -- VGA color in
+	signal RO,GO,BO : std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0) := (others => '0'); -- VGA color out
+	signal VSYNC, HSYNC :  std_logic := '0';
+
+	signal Xas : integer := 72;
+	signal Yas : integer := 14;
+	signal counter : std_logic_vector(1 downto 0) := (others => '0');
 begin
+	uut : ppu_vga_native port map(
+		CLK => CLK,
+		RESET => RST,
+		X => X,
+		Y => Y,
+		PREADY => PREADY,
+		RI => RI,
+		GI => GI,
+		BI => BI,
+		RO => RO,
+		GO => GO,
+		BO => BO,
+		VSYNC => VSYNC,
+		HSYNC => HSYNC
+	);
+
+	tb : process
+	begin
+		CLK <= '1';
+		wait for 1 ps;
+		CLK <= '0';
+		wait for 1 ps;
+	end process;
 
-UUT : ppu_vga_native port map(
-    clk => clk,
-    reset => rst,
-    x => x,
-    y => y,
-    pready => pready,
-    ri => ri,
-    gi => gi,
-    bi => bi,
-    ro => ro,
-    go => go,
-    bo => bo,
-    vsync => vsync,
-    hsync => hsync
-);
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			counter <= counter + 1;
+		end if;
 
-    tb : process
-    begin
-            clk <= '1';
-            wait for 1 ps;
-            clk <= '0';
-            wait for 1 ps;
-    end process;
-    
-    
-      process(clk)
-      begin
-            if rising_edge(clk) then
-                counter <= counter + 1;
-            end if;
-            
-            if(counter = "11") then 
-                pready <= '1';   
-                ri <= x"d";
-                gi <= x"a";
-                bi <= x"d";
-                x <= std_logic_vector(to_unsigned(Xas, x'length));
-                if (Xas = 391) then
-                    Xas <= 72;
-                    y <= std_logic_vector(to_unsigned(Yas, y'length));
-                    if (Yas = 255) then
-                        Yas <= 14;
-                    else
-                        Yas <= Yas + 1;
-                    end if;
-                else
-                    Xas <= Xas + 1;
-                end if;
-            end if;
-      end process;
+		if(counter = "11") then
+			pready <= '1';
+			ri <= x"d";
+			gi <= x"a";
+			bi <= x"d";
+			x <= std_logic_vector(to_unsigned(Xas, x'length));
+			if (Xas = 391) then
+				Xas <= 72;
+				y <= std_logic_vector(to_unsigned(Yas, y'length));
+				if (Yas = 255) then
+					Yas <= 14;
+				else
+					Yas <= Yas + 1;
+				end if;
+			else
+				Xas <= Xas + 1;
+			end if;
+		end if;
+	end process;
 end Behavioral;
diff --git a/basys3/basys3.srcs/ppu_vga_tiny.vhd b/basys3/basys3.srcs/ppu_vga_tiny.vhd
index f47df48..0e496f6 100644
--- a/basys3/basys3.srcs/ppu_vga_tiny.vhd
+++ b/basys3/basys3.srcs/ppu_vga_tiny.vhd
@@ -1,103 +1,73 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 22.02.2023 13:13:03
--- Design Name: 
--- Module Name: ppu_vga_tiny - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
 use work.ppu_consts.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
 
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ppu_vga_tiny is
-  Port ( 
-  		CLK: in std_logic; -- system clock
-		RESET: in std_logic;
+entity ppu_vga_tiny is port (
+	CLK : in std_logic; -- system clock
+	RESET : in std_logic;
 
-		X: out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
-		Y: out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
-		
-		VSYNC, VBLANK, 
-		HSYNC, HBLANK: out std_logic); -- VGA sync outputs 
+	X : out std_logic_vector(PPU_POS_H_WIDTH-1 downto 0); -- current screen pixel x
+	Y : out std_logic_vector(PPU_POS_V_WIDTH-1 downto 0); -- current screen pixel y
 
+	VSYNC, VBLANK,
+	HSYNC, HBLANK : out std_logic); -- VGA sync outputs
 end ppu_vga_tiny;
 
 architecture Behavioral of ppu_vga_tiny is
-  signal hcount: STD_LOGIC_VECTOR(PPU_POS_H_WIDTH-1 downto 0):= (others => '0');
-  signal vcount: STD_LOGIC_VECTOR(PPU_POS_V_WIDTH-1 downto 0):= (others => '0');
-  signal CLKcounter: STD_LOGIC_VECTOR(4 downto 0):= (others => '0');
-  
+	signal hcount : std_logic_vector(PPU_POS_H_WIDTH-1 downto 0) := (others => '0');
+	signal vcount : std_logic_vector(PPU_POS_V_WIDTH-1 downto 0) := (others => '0');
+	signal clk_counter : std_logic_vector(4 downto 0) := (others => '0');
 begin
-process (CLK) 
-begin
-    if rising_edge(CLK) then
-        CLKcounter <= CLKcounter + 1;
-        if(CLKcounter > 15) then
-            clkCounter <= (others => '0');
-            -- x,y data uit
-            X <= hcount;
-            Y <= vcount;
-             
-            --pulse width
-            if hcount < 32 or hcount >= 320-80 then
-                hsync <= '0';
-            else
-                hsync <= '1';
-            end if;
-        
-            if vcount < 8 or vcount >= 240-15 then
-                vsync <= '0';
-            else
-                vsync <= '1';
-            end if;
-             
-            -- Hblank and Vblank outputs
-            if hcount >= 320-80 then
-                hblank <= '1';
-            else
-                hblank <= '0';
-            end if;
-            
-            if vcount >= 240-15 then
-                vblank <= '1';
-            else
-                vblank <= '0';
-            end if;
-             
-            -- sync pulse time
-            hcount <= hcount + 1;
-             
-            if hcount = 400 then
-                vcount <= vcount + 1;
-                hcount <= (others => '0');
-            end if;
-            
-            if vcount = 255 then	   
-                vcount <= (others => '0');
-            end if;
-        end if;
-    end if;
-end process;
+	process (CLK)
+	begin
+		if rising_edge(CLK) then
+			clk_counter <= clk_counter + 1;
+			if(clk_counter > 15) then
+				clk_counter <= (others => '0');
+				-- x,y data out
+				X <= hcount;
+				Y <= vcount;
+
+				--pulse width
+				if hcount < 32 or hcount >= 320-80 then
+					hsync <= '0';
+				else
+					hsync <= '1';
+				end if;
+
+				if vcount < 8 or vcount >= 240-15 then
+					vsync <= '0';
+				else
+					vsync <= '1';
+				end if;
+
+				-- Hblank and Vblank outputs
+				if hcount >= 320-80 then
+					hblank <= '1';
+				else
+					hblank <= '0';
+				end if;
+
+				if vcount >= 240-15 then
+					vblank <= '1';
+				else
+					vblank <= '0';
+				end if;
+
+				-- sync pulse time
+				hcount <= hcount + 1;
+
+				if hcount = 400 then
+					vcount <= vcount + 1;
+					hcount <= (others => '0');
+				end if;
 
+				if vcount = 255 then
+					vcount <= (others => '0');
+				end if;
+			end if;
+		end if;
+	end process;
 end Behavioral;
diff --git a/style.md b/style.md
index 4a65ed3..3fe912b 100644
--- a/style.md
+++ b/style.md
@@ -30,12 +30,14 @@ before formatting as a failsafe.
 - custom typedefs are prefixed with `hh_` and suffixed with `_t` (e.g. `hh_bam_tile_t`)
 - library hooks that need specific symbol names are exempt from the naming
   conventions (e.g. `main` or `HAL_UART_MspInit`)
+- names are always in English
 
 ## others
 
 - document **how to use** code using doxygen-style comments in headers
 - document **what code is doing** using inline comments (where applicable)
 - don't write redundant comments (e.g. `int c = a + b; // add a and b`)
+- comments are always in English
 
 ### markdown
 
@@ -52,4 +54,29 @@ before formatting as a failsafe.
 - vhdl filename is the same as the component name
 - vhdl files should end in the `.vhd` file extension, not `.vhdl`
 - use spaces around the colon used for setting the type of signal definitions
-
+- do not mix uppercase and lowercase in entity/component/port/signal names
+- remove the default vivado file headers (large comment blocks with file info)
+- add a comment to the entity definition describing what the entity does
+- library import names should be lowercase
+- with the exception of off by one shifts, absolutely NO magic numbers are
+  allowed. use existing constants if possible, or create new ones in a consts
+  file instead of using magic numbers.
+- entities/components without a generic map should put the opening `port (` on
+  the same line as the `entity ... is ` line
+- entities/components with a generic map should be formatted like this:
+  ```
+  entity ... is
+    generic map(
+      NAME : type := default;
+      NAME : type := default)
+    port map(
+      NAME : in type;
+      NAME : out type);
+  end ...;
+  ```
+- port/generic maps with only one signal should be condensed into a single line
+- all library declarations should be grouped together at the top of the file
+- all `use` directives should be grouped together below the library
+  declarations
+- use a space before and after the comment syntax, e.g. `variable x : integer
+  := 0; -- comment here`