diff options
| author | lonkaars <loek@pipeframe.xyz> | 2023-03-14 21:29:30 +0100 |
|---|---|---|
| committer | lonkaars <loek@pipeframe.xyz> | 2023-03-14 21:29:30 +0100 |
| commit | fe8519597e3b6ec5050e93aa385c1092cee0117f (patch) | |
| tree | f9ef8fafde49a48eafe46241bba04209573a7745 | |
| parent | 589f6d2fdd2b01e9d88986480796530031693443 (diff) | |
WIP ppu testing
| -rw-r--r-- | basys3/basys3.srcs/io.xdc | 7 | ||||
| -rw-r--r-- | basys3/basys3.srcs/spi.vhd | 78 | ||||
| -rw-r--r-- | basys3/basys3.srcs/spi_tb.vhd | 259 | ||||
| -rw-r--r-- | basys3/basys3.srcs/top.vhd | 5 | ||||
| -rw-r--r-- | basys3/basys3.xpr | 69 | ||||
| -rw-r--r-- | docs/hardware/hardware.kicad_pcb | 453 | ||||
| -rw-r--r-- | docs/hardware/hardware.kicad_sch | 138 | ||||
| -rw-r--r-- | docs/hardware/pinout.md | 4 |
8 files changed, 646 insertions, 367 deletions
diff --git a/basys3/basys3.srcs/io.xdc b/basys3/basys3.srcs/io.xdc index a537742..e8e47d2 100644 --- a/basys3/basys3.srcs/io.xdc +++ b/basys3/basys3.srcs/io.xdc @@ -2,9 +2,9 @@ set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI] set_property IOSTANDARD LVCMOS33 [get_ports SPI_CS] set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK] -set_property PACKAGE_PIN A15 [get_ports SPI_CLK] +set_property PACKAGE_PIN J2 [get_ports SPI_CLK] set_property PACKAGE_PIN C15 [get_ports SPI_CS] -set_property PACKAGE_PIN A17 [get_ports SPI_MOSI] +set_property PACKAGE_PIN L1 [get_ports SPI_MOSI] set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK] set_property IOSTANDARD LVCMOS33 [get_ports RESET] @@ -46,5 +46,6 @@ set_property IOSTANDARD LVCMOS33 [get_ports VBLANK] set_property IOSTANDARD LVCMOS33 [get_ports WEN] set_property PACKAGE_PIN C16 [get_ports VBLANK] -set_property PACKAGE_PIN A14 [get_ports WEN] +set_property PACKAGE_PIN J1 [get_ports WEN] + diff --git a/basys3/basys3.srcs/spi.vhd b/basys3/basys3.srcs/spi.vhd index cdf7d4a..1560b54 100644 --- a/basys3/basys3.srcs/spi.vhd +++ b/basys3/basys3.srcs/spi.vhd @@ -6,65 +6,49 @@ use work.ppu_consts.all; entity spi is port ( SYSCLK : in std_logic; -- clock basys3 100MHz - SPI_CLK : in std_logic; -- incoming clock of SPI + SPI_CLK : in std_logic; -- incoming clock of SPI SPI_MOSI : in std_logic; -- incoming data of SPI - SPI_CS : in std_logic; -- incoming select of SPI - DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); -- data read + RESET : in std_logic; -- async reset + DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0')); -- data read end spi; architecture Behavioral of spi is - signal PulseFF0,PulseFF1,PulseFF2,PulseFF3 : std_logic := '0'; -- signal for metastability synchronizer of clk SPI - signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0'; -- signal for metastability synchronizer of data SPI - signal ssFF0,ssFF1,ssFF2,ssFF3 : std_logic := '0'; -- signal for metastability synchronizer of slave select SPI - - signal SPI_REG : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0'); -- signal to store incomming data of dataSPI (2x 8bit) - signal counter : integer := 23; -- counter for data position - signal enable : std_logic := '0'; -- enable signal if slave is selected + signal clkFF0,clkFF1,clkFF2,clkFF3 : std_logic := '0'; -- signal for metastability synchronizer of clk SPI + signal dataFF0,dataFF1,dataFF2,dataFF3 : std_logic := '0'; -- signal for metastability synchronizer of data SPI + + signal SPI_REG : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0'); + signal counter : integer := 31; -- counter for data position + + constant COUNTER_RESET_VALUE : integer := PPU_RAM_BUS_ADDR_WIDTH + PPU_RAM_BUS_DATA_WIDTH - 1; begin - process (SYSCLK) begin - if rising_edge(SYSCLK) then + if RESET = '1' then + counter <= COUNTER_RESET_VALUE; + DATA <= (others => '0'); + elsif rising_edge(SYSCLK) then -- flip flop for clk SPI to synchronise a - PulseFF0 <= SPI_CLK; - PulseFF1 <= PulseFF0; - PulseFF2 <= PulseFF1; - PulseFF3 <= PulseFF2; - -- flip flop for data SPI to synchronise + clkFF0 <= SPI_CLK; + clkFF1 <= clkFF0; + clkFF2 <= clkFF1; + clkFF3 <= clkFF2; + -- flip flop for data SPI to synchronise dataFF0 <= SPI_MOSI; dataFF1 <= dataFF0; dataFF2 <= dataFF1; - dataFF3 <= dataFF2; - -- flip flop for slave select SPI to synchronise - ssFF0 <= SPI_CS; - ssFF1 <= ssFF0; - ssFF2 <= ssFF1; - ssFF3 <= ssFF2; - -- check if slave select signal has falling edge (slave is selected by master) - if(ssFF3 = '1' and ssFF2 = '0') then - -- reset counter if true - counter <= 23; - -- disable data read if rising edge (slave is not selected) - elsif (ssFF3 = '0' and ssFF2 = '1') then - enable <= '0'; - end if; - -- check if synchronised slave select signal is falling edge or data read is enabled - if(ssFF3 = '1' and ssFF2 = '0') or enable = '1' then - enable <= '1'; -- enable data read - if (PulseFF3 = '0' and PulseFF2 = '1') then -- check for rising edge of clk SPI - if counter > -1 then - counter <= counter - 1; - -- data transfer into vector - SPI_REG(counter) <= dataFF3; - end if; + dataFF3 <= dataFF2; + + if (clkFF3 = '0' and clkFF2 = '1') then -- check for rising edge of clk SPI + if counter > -1 then + counter <= counter - 1; + -- data transfer into vector + SPI_REG(counter) <= dataFF3; end if; - -- check if counter is done - if counter = -1 then - counter <= 23; -- reset counter - DATA <= SPI_REG; - end if; - elsif (enable = '0') then - -- DATA <= SPI_REG; + end if; + -- check if counter is done + if counter = -1 then + counter <= COUNTER_RESET_VALUE; -- reset counter + DATA <= SPI_REG; end if; end if; end process; diff --git a/basys3/basys3.srcs/spi_tb.vhd b/basys3/basys3.srcs/spi_tb.vhd new file mode 100644 index 0000000..a8aa8c2 --- /dev/null +++ b/basys3/basys3.srcs/spi_tb.vhd @@ -0,0 +1,259 @@ +library ieee; +library unisim; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use unisim.vcomponents.all; +use work.ppu_consts.all; + +entity spi_tb is +end spi_tb; + +architecture behavioral of spi_tb is + signal SYSCLK : std_logic := '0'; + signal SPI_CLK : std_logic := '0'; + signal SPI_MOSI : std_logic := '0'; + signal RESET : std_logic := '0'; + signal DATA : std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0) := (others => '0'); +begin + uut : entity work.spi port map( + SYSCLK => SYSCLK, + RESET => RESET, + DATA => DATA, + SPI_CLK => SPI_CLK, + SPI_MOSI => SPI_MOSI); + + sysclkgen: process + begin + for i in 0 to 10000 loop + wait for 5 ns; + SYSCLK <= '1'; + wait for 5 ns; + SYSCLK <= '0'; + end loop; + wait; -- stop for simulator + end process; + + spi_data: process + begin + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + SPI_MOSI <= '1'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + wait for 50 ns; + SPI_CLK <= '1'; + wait for 50 ns; + SPI_CLK <= '0'; + wait for 50 ns; + RESET <= '1'; + wait for 50 ns; + RESET <= '0'; + + + wait; -- stop for simulator + end process; +end; diff --git a/basys3/basys3.srcs/top.vhd b/basys3/basys3.srcs/top.vhd index 0354b62..84ab7eb 100644 --- a/basys3/basys3.srcs/top.vhd +++ b/basys3/basys3.srcs/top.vhd @@ -8,7 +8,6 @@ entity top is port ( RESET : in std_logic; -- global (async) system reset SPI_CLK : in std_logic; -- incoming clock of SPI SPI_MOSI : in std_logic; -- incoming data of SPI - SPI_CS : in std_logic; -- incoming select of SPI WEN : in std_logic; -- PPU VRAM write enable R,G,B : out std_logic_vector(PPU_COLOR_OUTPUT_DEPTH-1 downto 0); VSYNC, HSYNC : out std_logic; -- VGA sync out @@ -30,7 +29,7 @@ architecture Behavioral of top is SYSCLK : in std_logic; -- clock basys3 100MHz SPI_CLK : in std_logic; -- incoming clock of SPI SPI_MOSI : in std_logic; -- incoming data of SPI - SPI_CS : in std_logic; -- incoming select of SPI + RESET : in std_logic; -- async reset DATA : out std_logic_vector(PPU_RAM_BUS_ADDR_WIDTH+PPU_RAM_BUS_DATA_WIDTH-1 downto 0)); -- data read end component; @@ -40,9 +39,9 @@ architecture Behavioral of top is begin serial_peripheral_interface: component spi port map( SYSCLK => SYSCLK, + RESET => RESET, SPI_CLK => SPI_CLK, SPI_MOSI => SPI_MOSI, - SPI_CS => '1', DATA => SPI_DATA); picture_processing_unit: component ppu port map( diff --git a/basys3/basys3.xpr b/basys3/basys3.xpr index 4e5b2dc..5b31f27 100644 --- a/basys3/basys3.xpr +++ b/basys3/basys3.xpr @@ -59,7 +59,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> - <Option Name="WTXSimLaunchSim" Val="0"/> + <Option Name="WTXSimLaunchSim" Val="5"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/> @@ -203,11 +203,16 @@ </FileSet> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> <Filter Type="Srcs"/> + <File Path="$PSRCDIR/spi_tb.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopModule" Val="top"/> + <Option Name="TopModule" Val="spi_tb"/> <Option Name="TopLib" Val="xil_defaultlib"/> - <Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/> <Option Name="SelectedSimModel" Val="rtl"/> @@ -226,7 +231,14 @@ <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="implementation"/> - <Attr Name="UsedInSteps" Val="synth_1"/> + <Attr Name="AutoDcp" Val="1"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/utils_1/imports/synth_2/top.dcp"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedInSteps" Val="synth_2"/> <Attr Name="AutoDcp" Val="1"/> </FileInfo> </File> @@ -313,19 +325,17 @@ </Simulator> </Simulators> <Runs Version="1" Minor="19"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Run Id="ppu_dispctl_pixclk_synth_1" Type="Ft3:Synth" SrcSet="ppu_dispctl_pixclk" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_pixclk" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_dispctl_pixclk_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_synth_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> - <Step Id="synth_design"> - <Option Id="FlattenHierarchy">0</Option> - </Step> + <Step Id="synth_design"/> </Strategy> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="ppu_dispctl_pixclk_synth_1" Type="Ft3:Synth" SrcSet="ppu_dispctl_pixclk" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_pixclk" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_dispctl_pixclk_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_synth_1"> + <Run Id="ppu_dispctl_slbuf_synth_1" Type="Ft3:Synth" SrcSet="ppu_dispctl_slbuf" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_slbuf" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_dispctl_slbuf_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_synth_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> @@ -335,7 +345,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="ppu_dispctl_slbuf_synth_1" Type="Ft3:Synth" SrcSet="ppu_dispctl_slbuf" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_slbuf" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_dispctl_slbuf_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_synth_1"> + <Run Id="ppu_tmm_synth_1" Type="Ft3:Synth" SrcSet="ppu_tmm" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_tmm_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> @@ -345,7 +355,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="ppu_tmm_synth_1" Type="Ft3:Synth" SrcSet="ppu_tmm" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_tmm_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_synth_1"> + <Run Id="ppu_bam_synth_1" Type="Ft3:Synth" SrcSet="ppu_bam" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_bam_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> @@ -355,7 +365,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="ppu_bam_synth_1" Type="Ft3:Synth" SrcSet="ppu_bam" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ppu_bam_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_synth_1"> + <Run Id="synth_2" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_2/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_2" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_2" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_2"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> @@ -365,7 +375,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="ppu_dispctl_pixclk_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_pixclk" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_dispctl_pixclk_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -375,15 +385,14 @@ <Step Id="post_place_power_opt_design"/> <Step Id="phys_opt_design"/> <Step Id="route_design"/> - <Step Id="post_route_phys_opt_design" EnableStepBool="1"/> + <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> - <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="ppu_dispctl_pixclk_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_pixclk" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_dispctl_pixclk_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_pixclk_impl_1"> + <Run Id="ppu_dispctl_slbuf_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_slbuf" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_dispctl_slbuf_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -400,7 +409,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="ppu_dispctl_slbuf_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_dispctl_slbuf" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_dispctl_slbuf_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_dispctl_slbuf_impl_1"> + <Run Id="ppu_tmm_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_tmm_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -417,7 +426,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="ppu_tmm_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_tmm" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_tmm_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_tmm_impl_1"> + <Run Id="ppu_bam_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_bam_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -434,7 +443,7 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="ppu_bam_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="ppu_bam" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ppu_bam_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ppu_bam_impl_1"> + <Run Id="impl_2" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_2" SynthRun="synth_2" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_2" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_2"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -447,6 +456,7 @@ <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> @@ -459,26 +469,15 @@ <Dashboards> <Dashboard Name="default_dashboard"> <Gadgets> - <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> - </Gadget> - <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> - </Gadget> - <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> - </Gadget> - <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> - </Gadget> + <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"/> + <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"/> + <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"/> + <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"/> <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> - <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> </Gadget> - <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> - <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> - </Gadget> + <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"/> </Gadgets> </Dashboard> <CurrentDashboard>default_dashboard</CurrentDashboard> diff --git a/docs/hardware/hardware.kicad_pcb b/docs/hardware/hardware.kicad_pcb index ded14d2..bf02072 100644 --- a/docs/hardware/hardware.kicad_pcb +++ b/docs/hardware/hardware.kicad_pcb @@ -118,13 +118,12 @@ (net 40 "unconnected-(J6-Pin_2-Pad2)") (net 41 "unconnected-(J6-Pin_3-Pad3)") (net 42 "unconnected-(J6-Pin_4-Pad4)") - (net 43 "unconnected-(J6-Pin_5-Pad5)") - (net 44 "unconnected-(J6-Pin_6-Pad6)") - (net 45 "Net-(J6-Pin_7)") - (net 46 "unconnected-(J6-Pin_8-Pad8)") - (net 47 "unconnected-(J6-Pin_9-Pad9)") - (net 48 "unconnected-(J6-Pin_10-Pad10)") - (net 49 "unconnected-(J6-Pin_12-Pad12)") + (net 43 "unconnected-(J6-Pin_6-Pad6)") + (net 44 "Net-(J6-Pin_7)") + (net 45 "unconnected-(J6-Pin_8-Pad8)") + (net 46 "unconnected-(J6-Pin_9-Pad9)") + (net 47 "unconnected-(J6-Pin_10-Pad10)") + (net 48 "unconnected-(J6-Pin_12-Pad12)") (footprint "Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Vertical" (layer "F.Cu") (tstamp 0dee130f-c83f-4dd5-8dbf-6cf84c47a719) @@ -180,15 +179,15 @@ (fp_line (start 3.81 13.97) (end -1.27 13.97) (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp b289e20d-8174-46f7-a359-034f5c41fe9a)) (pad "1" thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") - (net 27 "SPI_CLK") (pinfunction "Pin_1") (pintype "passive") (tstamp dc81b7c7-7358-4d2e-b645-3d258ae2a739)) + (net 22 "PPU_VRAM_WEN") (pinfunction "Pin_1") (pintype "passive") (tstamp dc81b7c7-7358-4d2e-b645-3d258ae2a739)) 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46.99)) + (wire (pts (xy 124.46 46.99) (xy 129.54 46.99)) (stroke (width 0) (type default)) (uuid b056940d-08b7-4eb9-8d4f-941533d27271) ) @@ -679,23 +686,31 @@ (stroke (width 0) (type default)) (uuid c0efcef6-b4d4-4f7d-bbfa-70da3e407b4f) ) - (wire (pts (xy 125.73 57.15) (xy 137.16 57.15)) + (wire (pts (xy 127 57.15) (xy 138.43 57.15)) (stroke (width 0) (type default)) (uuid c34692e8-e9c5-4e2b-a88a-b5369411831d) ) - (wire (pts (xy 146.05 57.15) (xy 146.05 49.53)) + (wire (pts (xy 107.95 57.15) (xy 111.76 57.15)) + (stroke (width 0) (type default)) + (uuid d064f681-efb4-4435-86f9-1f13b6b2bd3a) + ) + (wire (pts (xy 147.32 57.15) (xy 147.32 49.53)) (stroke (width 0) (type default)) (uuid d6fe7fd7-07cb-4b0e-b3fc-5762e8fbe616) ) - (wire (pts (xy 106.68 57.15) (xy 106.68 60.96)) + (wire (pts (xy 87.63 57.15) (xy 87.63 62.23)) (stroke (width 0) (type default)) (uuid e31c03ce-f409-4173-851d-158a3ce3f417) ) + (wire (pts (xy 104.14 57.15) (xy 107.95 57.15)) + (stroke (width 0) (type default)) + (uuid f8885bb5-7050-4b23-af4c-f7697c057416) + ) (wire (pts (xy 64.77 36.83) (xy 82.55 36.83)) (stroke (width 0) (type default)) (uuid f9db127e-de5f-40c0-83b0-43004a7b3d65) ) - (wire (pts (xy 123.19 57.15) (xy 125.73 57.15)) + (wire (pts (xy 124.46 57.15) (xy 127 57.15)) (stroke (width 0) (type default)) (uuid fc704422-e8f0-485b-a194-0746bf18debc) ) @@ -798,10 +813,10 @@ (effects (font (size 1.27 1.27)) (justify right) hide) ) ) - (global_label "SPI_CLK" (shape input) (at 91.44 46.99 180) (fields_autoplaced) + (global_label "SPI_CLK" (shape input) (at 91.44 52.07 180) (fields_autoplaced) (effects (font (size 1.27 1.27)) (justify right)) (uuid 8004fd75-c5f3-47c9-b252-91cf505302f3) - (property "Intersheetrefs" "${INTERSHEET_REFS}" (at 80.9142 46.99 0) + (property "Intersheetrefs" "${INTERSHEET_REFS}" (at 80.9142 52.07 0) (effects (font (size 1.27 1.27)) (justify right) hide) ) ) @@ -875,10 +890,10 @@ (effects (font (size 1.27 1.27)) (justify right) hide) ) ) - (global_label "PPU_VRAM_WEN" (shape input) (at 91.44 52.07 180) (fields_autoplaced) + (global_label "PPU_VRAM_WEN" (shape input) (at 91.44 46.99 180) (fields_autoplaced) (effects (font (size 1.27 1.27)) (justify right)) (uuid c786c23b-7648-4838-a747-4b793feda3f2) - (property "Intersheetrefs" "${INTERSHEET_REFS}" (at 73.899 52.07 0) + (property "Intersheetrefs" "${INTERSHEET_REFS}" (at 73.899 46.99 0) (effects (font (size 1.27 1.27)) (justify right) hide) ) ) @@ -911,19 +926,19 @@ ) ) - (symbol (lib_id "power:GND") (at 125.73 62.23 0) (unit 1) + (symbol (lib_id "power:GND") (at 127 62.23 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 07a3f9f8-a4fe-4dc9-b155-663dc89e5351) - (property "Reference" "#PWR06" (at 125.73 68.58 0) + (property "Reference" "#PWR06" (at 127 68.58 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Value" "GND" (at 125.73 67.31 0) + (property "Value" "GND" (at 127 67.31 0) (effects (font (size 1.27 1.27))) ) - (property "Footprint" "" (at 125.73 62.23 0) + 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(instances + (project "hardware" + (path "/9c6bd711-93fb-4327-8ec4-bcfe43c3c3c8" + (reference "#PWR07") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Device:C") (at 138.43 52.07 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 88616a98-32a9-45a4-ad80-7b1dbb105eda) - (property "Reference" "C1" (at 140.97 51.435 0) + (property "Reference" "C1" (at 142.24 51.435 0) (effects (font (size 1.27 1.27)) (justify left)) ) - (property "Value" "C" (at 140.97 53.975 0) + (property "Value" "C" (at 142.24 53.975 0) (effects (font (size 1.27 1.27)) (justify left)) ) - (property "Footprint" "Capacitor_THT:C_Disc_D6.0mm_W2.5mm_P5.00mm" (at 138.1252 55.88 0) + (property "Footprint" "Capacitor_THT:C_Disc_D6.0mm_W2.5mm_P5.00mm" (at 139.3952 55.88 0) (effects (font (size 1.27 1.27))) ) - (property "Datasheet" "~" (at 137.16 52.07 0) + (property "Datasheet" "~" (at 138.43 52.07 0) (effects (font (size 1.27 1.27)) hide) ) (pin "1" (uuid 2e4adc0b-f7e2-4883-97a8-f94df64dbd8a)) @@ -1271,19 +1311,19 @@ ) ) - (symbol (lib_id "power:GND") (at 106.68 60.96 0) (unit 1) + (symbol (lib_id "power:GND") (at 87.63 62.23 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid fc17c221-25c0-4f40-b58b-a20f0652bf18) - (property "Reference" "#PWR05" (at 106.68 67.31 0) + (property "Reference" "#PWR05" (at 87.63 68.58 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Value" "GND" (at 106.68 66.04 0) + (property "Value" "GND" (at 87.63 67.31 0) (effects (font (size 1.27 1.27))) ) - (property "Footprint" "" (at 106.68 60.96 0) + (property "Footprint" "" (at 87.63 62.23 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Datasheet" "" (at 106.68 60.96 0) + (property "Datasheet" "" (at 87.63 62.23 0) (effects (font (size 1.27 1.27)) hide) ) (pin "1" (uuid 00533e7a-0505-41b6-b5e2-f52df8bab4fb)) @@ -1296,19 +1336,19 @@ ) ) - (symbol (lib_id "Connector_Generic:Conn_02x06_Top_Bottom") (at 115.57 52.07 0) (unit 1) + (symbol (lib_id "Connector_Generic:Conn_02x06_Top_Bottom") (at 116.84 52.07 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid fe7b1f01-3f0e-49f0-9674-7a7e79bae509) - (property "Reference" "J6" (at 116.84 41.91 0) + (property "Reference" "J6" (at 118.11 41.91 0) (effects (font (size 1.27 1.27))) ) - (property "Value" "BASYS_JB" (at 116.84 44.45 0) + (property "Value" "BASYS_JB" (at 118.11 44.45 0) (effects (font (size 1.27 1.27))) ) - (property "Footprint" "Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Vertical" (at 115.57 52.07 0) + (property "Footprint" "Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Vertical" (at 116.84 52.07 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Datasheet" "~" (at 115.57 52.07 0) + (property "Datasheet" "~" (at 116.84 52.07 0) (effects (font (size 1.27 1.27)) hide) ) (pin "1" (uuid 0321aaf6-2626-45de-b511-1c2c91087b99)) diff --git a/docs/hardware/pinout.md b/docs/hardware/pinout.md index 2d5bb08..6c08201 100644 --- a/docs/hardware/pinout.md +++ b/docs/hardware/pinout.md @@ -3,9 +3,9 @@ |function|stm32 soc name|stm32 header name|fpga soc name|fpga header name| |-|-|-|-|-| |SPI MOSI|PA7|D11|L1|JA2| -|SPI CLK|PA5|D13|J1|JA1| +|SPI CLK|PA5|D13|J2|JA3| || -|PPU VRAM WEN|PA9|D8|J2|JA3| +|PPU VRAM WEN|PA9|D8|J1|JA1| || |APU PWM out|||A15|JB7| || |