aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorUnavailableDev <69792062+UnavailableDev@users.noreply.github.com>2023-03-03 11:59:55 +0100
committerGitHub <noreply@github.com>2023-03-03 11:59:55 +0100
commit9d998d2deb5fb1f90fd34ca10e4b44fc2bc8337d (patch)
tree0a987fae08d066e749fcaa34af4e5bccf2095cce
parent7c9468e7165aac2724a8bad19e950ca435f68316 (diff)
parent586aded2dddf2e6101d2709e42bceccadb50e8a1 (diff)
Merge pull request #19 from UnavailableDev/dev
apu constants cleanup
-rw-r--r--basys3/basys3.srcs/apu_consts.vhd5
-rw-r--r--basys3/basys3.srcs/apu_lut_reader.vhd16
-rw-r--r--basys3/basys3.srcs/apu_note_to_frequency.vhd10
3 files changed, 21 insertions, 10 deletions
diff --git a/basys3/basys3.srcs/apu_consts.vhd b/basys3/basys3.srcs/apu_consts.vhd
new file mode 100644
index 0000000..f0e2754
--- /dev/null
+++ b/basys3/basys3.srcs/apu_consts.vhd
@@ -0,0 +1,5 @@
+package apu_consts is
+ constant SAMPLE_SIZE_WIDTH : natural := 8; -- data width for sample size
+ constant SAMPLE_SIZE : natural := 256; -- max value in sample size
+
+end package apu_consts;
diff --git a/basys3/basys3.srcs/apu_lut_reader.vhd b/basys3/basys3.srcs/apu_lut_reader.vhd
index 2f92eca..b3b0ca4 100644
--- a/basys3/basys3.srcs/apu_lut_reader.vhd
+++ b/basys3/basys3.srcs/apu_lut_reader.vhd
@@ -2,20 +2,23 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+library work;
+use work.apu_consts.all;
+
entity apu_lut_reader is
port (
clk : in std_logic;
rst : in std_logic;
freq : in std_logic_vector(11 downto 0);
wave : in std_logic_vector(1 downto 0);
- value : out std_logic_vector(7 downto 0)
+ value : out std_logic_vector(SAMPLE_SIZE_WIDTH-1 downto 0)
);
end entity;
architecture behavioral of apu_lut_reader is
- constant AMPLITUDE : natural := 0;
- constant SAMPLE_SIZE : natural := 256;
+ -- amplitude (currently) only applies to square waves
+ constant AMPLITUDE : natural := SAMPLE_SIZE/2; -- less or equals SAMPLE_SIZE/2 (Amplitude around SAMPLE_SIZE/2)
signal idx : unsigned := (others => '0');
signal buf : unsigned := (others => '0');
@@ -23,6 +26,9 @@ architecture behavioral of apu_lut_reader is
begin
process (clk)
+ variable val_min : unsigned := to_unsigned(SAMPLE_SIZE/2 - integer(AMPLITUDE),SAMPLE_SIZE_WIDTH-1);
+ variable val_max : unsigned := to_unsigned(SAMPLE_SIZE/2 + integer(AMPLITUDE),SAMPLE_SIZE_WIDTH-1);
+
begin
if rst = '1' then
idx <= x"00";
@@ -35,9 +41,9 @@ begin
value <= std_logic_vector( idx );
elsif wave = "01" then -- Square
if idx < (SAMPLE_SIZE/2) then
- value <= x"00"; --std_logic_vector( SAMPLE_SIZE-AMPLITUDE ); -- TODO: make so that this work with a changable amplitude (for square wave)
+ value <= std_logic_vector(val_min); --std_logic_vector( SAMPLE_SIZE-AMPLITUDE ); -- TODO: make so that this work with a changable amplitude (for square wave)
else
- value <= x"FF";
+ value <= std_logic_vector(val_max);
end if;
elsif wave = "10" then -- Triangle
if idx < (SAMPLE_SIZE/2) then
diff --git a/basys3/basys3.srcs/apu_note_to_frequency.vhd b/basys3/basys3.srcs/apu_note_to_frequency.vhd
index 810cef9..48defa3 100644
--- a/basys3/basys3.srcs/apu_note_to_frequency.vhd
+++ b/basys3/basys3.srcs/apu_note_to_frequency.vhd
@@ -2,6 +2,9 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+library work;
+use work.apu_consts.all;
+
entity apu_note_to_frequency is port (
-- clk : in std_logic;
-- rst : in std_logic;
@@ -10,7 +13,6 @@ entity apu_note_to_frequency is port (
end entity;
architecture Behavioral of apu_note_to_frequency is
- signal buff_small : std_logic_vector(7 downto 0) := (others => '0');
signal buff : std_logic_vector(15 downto 0) := (others => '0');
signal shift : integer;
begin
@@ -18,7 +20,7 @@ begin
shift <= to_integer(unsigned( data(2 downto 0) ));
buff <=
- x"1F0" when data(6 downto 3) = (x"1") else -- C 496
+ x"1F0" when data(6 downto 3) = (x"1") else -- C 496 --values are calculated for 8kHz sample rate
x"1D0" when data(6 downto 3) = (x"2") else -- C#/Db 464
x"1B0" when data(6 downto 3) = (x"3") else -- D 432
x"1A0" when data(6 downto 3) = (x"4") else -- D#/Eb 416
@@ -32,8 +34,6 @@ begin
x"100" when data(6 downto 3) = (x"C") else -- B 256
x"000";
- -- buff <= x"1" & buff_small;
- freq <= std_logic_vector( shift_right(unsigned(buff), shift) );
- -- freq <= (others => '0') & buff(11 downto shift); -- bitshift values out (or div by powers of 2) -- TODO: NO WORKY!!! (concat (others => '0');)
+ freq <= std_logic_vector( shift_right(unsigned(buff), natural(shift)) ); -- TODO: MAYBE WORKY???
end architecture;