From dd98fe4239181753337a95d887db0d5c56e52b13 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Mon, 28 Nov 2022 21:28:44 +0100
Subject: clean up code and update design files

---
 src/alu.vhd      | 9 ---------
 src/main-alu.vhd | 6 +++---
 2 files changed, 3 insertions(+), 12 deletions(-)

(limited to 'src')

diff --git a/src/alu.vhd b/src/alu.vhd
index edaee52..ee9b729 100644
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -29,17 +29,8 @@ architecture Behavioral of ALU is
 	signal C_AplusB,
 	       C_AminB,
 				 C_BminA,
-				 C_Dummy,
-				 C_OnlyA,
-				 C_OnlyB,
 				 C_MinA,
 				 C_MinB,
-				 C_ShiftLeftA,
-				 C_ShiftRightA,
-				 C_RotateLeftA,
-				 C_RotateRightA,
-				 C_AllZeros,
-				 C_AllOnes,
 				 C: std_logic := '0';
 	component add8bs is
 		port (
diff --git a/src/main-alu.vhd b/src/main-alu.vhd
index ffc46f8..b7ffa05 100644
--- a/src/main-alu.vhd
+++ b/src/main-alu.vhd
@@ -9,7 +9,8 @@ entity main is
 		Op: in std_logic_vector(3 downto 0);
 		CLK: in std_logic;
 		DD: out std_logic_vector(7 downto 0);
-		DS: out std_logic_vector(3 downto 0));
+		DS: out std_logic_vector(3 downto 0);
+		EQ: out std_logic);
 end main;
 
 architecture Behavioral of main is
@@ -42,7 +43,6 @@ architecture Behavioral of main is
 	end component;
 
 	signal CALC_NUM: std_logic_vector(8 downto 0);
-	signal ALU_EQ: std_logic;
 	signal DISP_NUM: std_logic_vector(8 downto 0);
 	signal N0, N1, N2, N3: std_logic_vector(3 downto 0);
 	signal NC0, NC1: std_logic_vector(8 downto 0); -- carry from bin2bcd8
@@ -62,7 +62,7 @@ begin
 			Op => Op,
 			Res => CALC_NUM(7 downto 0),
 			Cout => CALC_NUM(8),
-			Equal => ALU_EQ);
+			Equal => EQ);
 	
 	topos: component stopp
 		port map(
-- 
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