From a3b5c4f84698182612f1ce43f09645bfc3566221 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Mon, 28 Nov 2022 10:27:50 +0100
Subject: working bin2bcd8 and design for signed to positive part

---
 src/bin2bcd8.vhd    | 17 +++++++++++++++++
 src/bin2bcd8_tb.vhd | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 src/main-alu.vhd    |  0
 3 files changed, 65 insertions(+)
 create mode 100644 src/bin2bcd8.vhd
 create mode 100644 src/bin2bcd8_tb.vhd
 create mode 100644 src/main-alu.vhd

(limited to 'src')

diff --git a/src/bin2bcd8.vhd b/src/bin2bcd8.vhd
new file mode 100644
index 0000000..eb8c71d
--- /dev/null
+++ b/src/bin2bcd8.vhd
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+-- use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity bin2bcd8 is port(
+	A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit)
+	X: out std_logic_vector(3 downto 0); -- bcd output
+	R: out std_logic_vector(7 downto 0)); -- remainder after operation
+end bin2bcd8;
+
+architecture Behavioral of bin2bcd8 is
+begin
+	X <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) mod 10, 4));
+	R <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) / 10, 8));
+end Behavioral;
diff --git a/src/bin2bcd8_tb.vhd b/src/bin2bcd8_tb.vhd
new file mode 100644
index 0000000..4e24471
--- /dev/null
+++ b/src/bin2bcd8_tb.vhd
@@ -0,0 +1,48 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity bin2bcd8_tb is 
+end bin2bcd8_tb;
+
+architecture Behavioral of bin2bcd8_tb is
+component bin2bcd8 port(
+	A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit)
+	X: out std_logic_vector(3 downto 0); -- bcd output
+	R: out std_logic_vector(7 downto 0)); -- remainder after operation
+end component;
+-- test input
+signal I: std_logic_vector(7 downto 0) := (others => '0');
+-- test output
+signal X: std_logic_vector(3 downto 0);
+signal R: std_logic_vector(7 downto 0);
+
+signal test_case: std_logic_vector(7 downto 0);
+signal OK: boolean := true;
+begin
+	test: bin2bcd8 port map(
+		A => I,
+		X => X,
+		R => R);
+
+	tb: process
+		-- expected output
+		variable X_t: integer := 0;
+		variable Y_t: integer := 0;
+	begin
+	
+	for test_i in 0 to 255 loop
+		test_case <= std_logic_vector(to_unsigned(test_i,8));
+		wait for 1 ps;
+
+		I <= test_case;
+
+		wait for 10 ns;
+	end loop;
+	wait; -- stop simulator
+	end process;
+end Behavioral;
+
diff --git a/src/main-alu.vhd b/src/main-alu.vhd
new file mode 100644
index 0000000..e69de29
-- 
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