From 586888eb79dece078253fbd3af16b8167e84d960 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Wed, 16 Nov 2022 16:48:21 +0100
Subject: implement bin2bcd

---
 .../adder-and-display.srcs/sources_1/bin2bcd.vhd   | 33 ++++++++++++++++++++++
 .../adder-and-display.srcs/sources_1/main.vhd      | 32 +++++++++------------
 adder-and-display/adder-and-display.xpr            |  6 ++++
 3 files changed, 53 insertions(+), 18 deletions(-)
 create mode 100644 adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd

(limited to 'adder-and-display')

diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
new file mode 100644
index 0000000..4bb18bb
--- /dev/null
+++ b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity bin2bcd is port(
+	I: in std_logic_vector(4 downto 0);
+	X: out std_logic_vector(3 downto 0);
+	Y: out std_logic_vector(3 downto 0));
+end bin2bcd;
+
+architecture Behavioral of bin2bcd is
+begin
+	with I select
+		X <=
+			x"0" when x"00" | x"0a" | x"14" | x"1e",
+			x"1" when x"01" | x"0b" | x"15" | x"1f",
+			x"2" when x"02" | x"0c" | x"16",
+			x"3" when x"03" | x"0d" | x"17",
+			x"4" when x"04" | x"0e" | x"18",
+			x"5" when x"05" | x"0f" | x"19",
+			x"6" when x"06" | x"10" | x"1a",
+			x"7" when x"07" | x"11" | x"1b",
+			x"8" when x"08" | x"12" | x"1c",
+			x"9" when x"09" | x"13" | x"1d",
+			(others => '0') when others;
+	with I select
+		Y <=
+			x"0" when x"00" | x"01" | x"02" | x"03" | x"04" | x"05" | x"06" | x"07" | x"08" | x"09",
+			x"1" when x"0a" | x"0b" | x"0c" | x"0d" | x"0e" | x"0f" | x"10" | x"11" | x"12" | x"13",
+			x"2" when x"14" | x"15" | x"16" | x"17" | x"18" | x"19" | x"1a" | x"1b" | x"1c" | x"1d",
+			x"3" when x"1e" | x"1f",
+			(others => '0') when others;
+end Behavioral;
+
diff --git a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd
index 907d8cc..92e306e 100644
--- a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd
+++ b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd
@@ -23,7 +23,7 @@ architecture Behavioral of main is
 	end component;
 	component bin2bcd
 		port (
-			I: in std_logic_vector(3 downto 0);
+			I: in std_logic_vector(4 downto 0);
 			X: out std_logic_vector(3 downto 0);
 			Y: out std_logic_vector(3 downto 0));
 	end component;
@@ -38,6 +38,8 @@ architecture Behavioral of main is
 			DS: out std_logic_vector(3 downto 0));
 	end component;
 	signal X: std_logic_vector(3 downto 0); -- add out
+	signal Cout: std_logic; -- carry out
+	signal AOW: std_logic_vector(4 downto 0); -- add out wide (5-bit)
 	signal BCD0: std_logic_vector(3 downto 0); -- bcd 10^0
 	signal BCD1: std_logic_vector(3 downto 0); -- bcd 10^1
 	signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock
@@ -54,26 +56,20 @@ begin
 			B => B,
 			Cin => '0',
 			X => X,
-			Cout => open);
-	-- bcd: component bin2bcd
-	-- 	port map (
-	-- 		I => X,
-	-- 		X => BCD0,
-	-- 		Y => BCD1);
-	-- disp: component bcd2disp
-	-- 	port map (
-	-- 		CLK => CLK_T(19),
-	-- 		N0 => BCD0,
-	-- 		N1 => BCD1,
-	-- 		N2 => "0000",
-	-- 		N3 => "0000");
+			Cout => Cout);
+  AOW <= Cout & X;
+	bcd: component bin2bcd
+		port map (
+			I => AOW,
+			X => BCD0,
+			Y => BCD1);
 	disp: component bcd2disp
 		port map (
 			CLK => CLK_T(18),
-			N0 => X,
-			N1 => X,
-			N2 => "0000",
-			N3 => "0000",
+			N0 => "0000",
+			N1 => "0000",
+			N2 => BCD1,
+			N3 => BCD0,
 			DD => DD,
 			DS => DS);
 end Behavioral;
diff --git a/adder-and-display/adder-and-display.xpr b/adder-and-display/adder-and-display.xpr
index 2ff8357..5dcc304 100644
--- a/adder-and-display/adder-and-display.xpr
+++ b/adder-and-display/adder-and-display.xpr
@@ -114,6 +114,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/bin2bcd.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/sources_1/dispdrv.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
-- 
cgit v1.2.3


From eb1e133237544a31db67358cb65200a0717c1ace Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Wed, 16 Nov 2022 18:40:01 +0100
Subject: fix bin2bcd implementation

---
 .../adder-and-display.srcs/sources_1/bin2bcd.vhd   | 28 ++++++++++-----------
 adder-and-display/adder-and-display.xpr            | 29 ++++++++++++++++++----
 2 files changed, 38 insertions(+), 19 deletions(-)

(limited to 'adder-and-display')

diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
index 4bb18bb..548c9e5 100644
--- a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
+++ b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd
@@ -11,23 +11,23 @@ architecture Behavioral of bin2bcd is
 begin
 	with I select
 		X <=
-			x"0" when x"00" | x"0a" | x"14" | x"1e",
-			x"1" when x"01" | x"0b" | x"15" | x"1f",
-			x"2" when x"02" | x"0c" | x"16",
-			x"3" when x"03" | x"0d" | x"17",
-			x"4" when x"04" | x"0e" | x"18",
-			x"5" when x"05" | x"0f" | x"19",
-			x"6" when x"06" | x"10" | x"1a",
-			x"7" when x"07" | x"11" | x"1b",
-			x"8" when x"08" | x"12" | x"1c",
-			x"9" when x"09" | x"13" | x"1d",
+			b"0000" when b"00000" | b"01010" | b"10100" | b"11110",
+			b"0001" when b"00001" | b"01011" | b"10101" | b"11111",
+			b"0010" when b"00010" | b"01100" | b"10110",
+			b"0011" when b"00011" | b"01101" | b"10111",
+			b"0100" when b"00100" | b"01110" | b"11000",
+			b"0101" when b"00101" | b"01111" | b"11001",
+			b"0110" when b"00110" | b"10000" | b"11010",
+			b"0111" when b"00111" | b"10001" | b"11011",
+			b"1000" when b"01000" | b"10010" | b"11100",
+			b"1001" when b"01001" | b"10011" | b"11101",
 			(others => '0') when others;
 	with I select
 		Y <=
-			x"0" when x"00" | x"01" | x"02" | x"03" | x"04" | x"05" | x"06" | x"07" | x"08" | x"09",
-			x"1" when x"0a" | x"0b" | x"0c" | x"0d" | x"0e" | x"0f" | x"10" | x"11" | x"12" | x"13",
-			x"2" when x"14" | x"15" | x"16" | x"17" | x"18" | x"19" | x"1a" | x"1b" | x"1c" | x"1d",
-			x"3" when x"1e" | x"1f",
+			b"0000" when b"00000" | b"00001" | b"00010" | b"00011" | b"00100" | b"00101" | b"00110" | b"00111" | b"01000" | b"01001",
+			b"0001" when b"01010" | b"01011" | b"01100" | b"01101" | b"01110" | b"01111" | b"10000" | b"10001" | b"10010" | b"10011",
+			b"0010" when b"10100" | b"10101" | b"10110" | b"10111" | b"11000" | b"11001" | b"11010" | b"11011" | b"11100" | b"11101",
+			b"0011" when b"11110" | b"11111",
 			(others => '0') when others;
 end Behavioral;
 
diff --git a/adder-and-display/adder-and-display.xpr b/adder-and-display/adder-and-display.xpr
index 5dcc304..0a0e2ef 100644
--- a/adder-and-display/adder-and-display.xpr
+++ b/adder-and-display/adder-and-display.xpr
@@ -59,7 +59,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTXSimLaunchSim" Val="14"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -160,11 +160,30 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sim_1/bin2bcd_tb.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/dispdrv.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/dispdrv_tb.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopModule" Val="bin2bcd_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SelectedSimModel" Val="rtl"/>
@@ -173,6 +192,7 @@
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="NLNetlistMode" Val="funcsim"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
@@ -222,7 +242,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
         <Step Id="init_design"/>
@@ -235,7 +255,6 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
-- 
cgit v1.2.3


From ecdebc2b9a2e72e907b5c9bce82ad9df4960dcf8 Mon Sep 17 00:00:00 2001
From: lonkaars <loek@pipeframe.xyz>
Date: Wed, 16 Nov 2022 18:59:28 +0100
Subject: dispdrv testbench WIP

---
 .../adder-and-display.srcs/sim_1/dispdrv_tb.vhd    | 77 ++++++++++++++++++++++
 adder-and-display/adder-and-display.xpr            | 17 +----
 2 files changed, 79 insertions(+), 15 deletions(-)
 create mode 100644 adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd

(limited to 'adder-and-display')

diff --git a/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd b/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd
new file mode 100644
index 0000000..2c8d6f5
--- /dev/null
+++ b/adder-and-display/adder-and-display.srcs/sim_1/dispdrv_tb.vhd
@@ -0,0 +1,77 @@
+library IEEE;
+library UNISIM;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity dispdrv_tb is
+end dispdrv_tb;
+
+architecture Behavioral of dispdrv_tb is
+component dispdrv port (
+	CLK: in std_logic;
+	D0: in std_logic_vector(7 downto 0);
+	D1: in std_logic_vector(7 downto 0);
+	D2: in std_logic_vector(7 downto 0);
+	D3: in std_logic_vector(7 downto 0);
+	D: out std_logic_vector(7 downto 0);
+	S: out std_logic_vector(1 downto 0));
+end component;
+signal CLK: std_logic;
+signal D0: std_logic_vector(7 downto 0);
+signal D1: std_logic_vector(7 downto 0);
+signal D2: std_logic_vector(7 downto 0);
+signal D3: std_logic_vector(7 downto 0);
+signal D: std_logic_vector(7 downto 0);
+signal S: std_logic_vector(1 downto 0);
+
+signal test_case: std_logic_vector(1 downto 0);
+signal OK: boolean := true;
+begin
+	test: dispdrv port map(
+		CLK => CLK,
+		D0 => D0,
+		D1 => D1,
+		D2 => D2,
+		D3 => D3,
+		D => D,
+		S => S);
+
+	tb: process
+		variable D0_t: std_logic_vector(7 downto 0) := b"00001111";
+		variable D1_t: std_logic_vector(7 downto 0) := b"11110000";
+		variable D2_t: std_logic_vector(7 downto 0) := b"01010101";
+		variable D3_t: std_logic_vector(7 downto 0) := b"10101010";
+	begin
+
+	D0 <= D0_t;
+	D1 <= D1_t;
+	D2 <= D2_t;
+	D3 <= D3_t;
+
+	for test_i in 0 to 3 loop
+		test_case <= std_logic_vector(to_unsigned(test_i, 2));
+		CLK <= '0';
+		wait for 5 ns;
+		CLK <= '1';
+		wait for 5 ns;
+
+		if test_case = 0 and D /= D0_t then
+			OK <= false;
+		end if;
+		if test_case = 1 and D /= D1_t then
+			OK <= false;
+		end if;
+		if test_case = 2 and D /= D2_t then
+			OK <= false;
+		end if;
+		if test_case = 3 and D /= D3_t then
+			OK <= false;
+		end if;
+	end loop;
+	wait;
+	end process;
+end Behavioral;
+
diff --git a/adder-and-display/adder-and-display.xpr b/adder-and-display/adder-and-display.xpr
index 0a0e2ef..cc9d180 100644
--- a/adder-and-display/adder-and-display.xpr
+++ b/adder-and-display/adder-and-display.xpr
@@ -44,6 +44,7 @@
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
     <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
     <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
@@ -59,7 +60,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="14"/>
+    <Option Name="WTXSimLaunchSim" Val="16"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -114,12 +115,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/bin2bcd.vhd">
-        <FileInfo>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PSRCDIR/sources_1/dispdrv.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -166,16 +161,8 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sim_1/dispdrv.vhd">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PSRCDIR/sim_1/dispdrv_tb.vhd">
         <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
-- 
cgit v1.2.3