From 7fd197c3ab26c17c12e19f76d893acb1d7ee95fd Mon Sep 17 00:00:00 2001 From: lonkaars Date: Sun, 5 Feb 2023 15:07:34 +0100 Subject: martijn's code toegevoegd voor prog2w1 sound --- sound/sound.srcs/AudioOut.vhd | 1 + sound/sound.srcs/PlayAudio.vhd | 1 + sound/sound.srcs/SampleOut.vhd | 1 + sound/sound.srcs/constrs_1/new/main.xdc | 6 + .../ip/BertErnie44Audio/BertErnie44Audio.xci | 258 ++++++++++++++++++ sound/sound.xpr | 298 +++++++++++++++++++++ src/AudioOut.vhd | 71 +++++ src/PlayAudio.vhd | 77 ++++++ src/SampleOut.vhd | 65 +++++ 9 files changed, 778 insertions(+) create mode 120000 sound/sound.srcs/AudioOut.vhd create mode 120000 sound/sound.srcs/PlayAudio.vhd create mode 120000 sound/sound.srcs/SampleOut.vhd create mode 100644 sound/sound.srcs/constrs_1/new/main.xdc create mode 100644 sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci create mode 100644 sound/sound.xpr create mode 100644 src/AudioOut.vhd create mode 100644 src/PlayAudio.vhd create mode 100644 src/SampleOut.vhd diff --git a/sound/sound.srcs/AudioOut.vhd b/sound/sound.srcs/AudioOut.vhd new file mode 120000 index 0000000..b45f809 --- /dev/null +++ b/sound/sound.srcs/AudioOut.vhd @@ -0,0 +1 @@ +../../src/AudioOut.vhd \ No newline at end of file diff --git a/sound/sound.srcs/PlayAudio.vhd b/sound/sound.srcs/PlayAudio.vhd new file mode 120000 index 0000000..a9d1583 --- /dev/null +++ b/sound/sound.srcs/PlayAudio.vhd @@ -0,0 +1 @@ +../../src/PlayAudio.vhd \ No newline at end of file diff --git a/sound/sound.srcs/SampleOut.vhd b/sound/sound.srcs/SampleOut.vhd new file mode 120000 index 0000000..4ef35b5 --- /dev/null +++ b/sound/sound.srcs/SampleOut.vhd @@ -0,0 +1 @@ +../../src/SampleOut.vhd \ No newline at end of file diff --git a/sound/sound.srcs/constrs_1/new/main.xdc b/sound/sound.srcs/constrs_1/new/main.xdc new file mode 100644 index 0000000..ec3e564 --- /dev/null +++ b/sound/sound.srcs/constrs_1/new/main.xdc @@ -0,0 +1,6 @@ +set_property IOSTANDARD LVCMOS33 [get_ports clk100] +set_property IOSTANDARD LVCMOS33 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports outMusic] +set_property PACKAGE_PIN W5 [get_ports clk100] +set_property PACKAGE_PIN A15 [get_ports outMusic] +set_property PACKAGE_PIN U18 [get_ports reset] diff --git a/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci b/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci new file mode 100644 index 0000000..1f464b9 --- /dev/null +++ b/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci @@ -0,0 +1,258 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "BertErnie44Audio", + "component_reference": "xilinx.com:ip:blk_mem_gen:8.4", + "ip_revision": "5", + "gen_directory": "../../../../sound.gen/sources_1/ip/BertErnie44Audio", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "BertErnie44Audio", "resolve_type": "user", "usage": "all" } ], + "Interface_Type": [ { "value": "Native", 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+ "mode": "slave", + "parameters": { + "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ADDR": [ { "physical_name": "addra" } ], + "CLK": [ { "physical_name": "clka" } ], + "DIN": [ { "physical_name": "dina" } ], + "DOUT": [ { "physical_name": "douta" } ], + "WE": [ { "physical_name": "wea" } ] + } + } + }, + "memory_maps": { + "S_1": { + "address_blocks": { + "Mem0": { + "base_address": "0", + "range": "4096", + "usage": "memory", + "access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ], + "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ] + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/sound/sound.xpr b/sound/sound.xpr new file mode 100644 index 0000000..f02c84f --- /dev/null +++ b/sound/sound.xpr @@ -0,0 +1,298 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/src/AudioOut.vhd b/src/AudioOut.vhd new file mode 100644 index 0000000..715bf7f --- /dev/null +++ b/src/AudioOut.vhd @@ -0,0 +1,71 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity AudioOut is + generic( + INPUT_DEPTH: integer := 256; + INPUT_SAMPLE_SIZE: integer := 36984; + INPUT_AUDIO_HZ: integer := 44100; + INPUT_CLK_HZ: integer := 100000000 + ); + Port ( reset, clk : in STD_LOGIC; + inMusicData : in STD_LOGIC_VECTOR(7 downto 0); + outMusic : out STD_LOGIC); +end AudioOut; + +architecture Behavioral of AudioOut is + signal count: integer; + --signal bStartMusic : boolean; + +begin + process (reset, clk) + variable currentThreasHold: integer; + begin + -- if reset + if (reset = '1') then + -- default values for outputs, so output state is always defined + outMusic <= '0'; + count <= 0; + currentThreasHold := 0; + -- + elsif rising_edge(clk) then + -- default values for outputs, so output state is always defined + outMusic <= '0'; + count <= 0; + currentThreasHold := 0; + + -- start code + -- calculate amount of puls to turn on PWM + -- calculate available PWM pulses: (INPUT_CLK_KHZ/INPUT_AUDIO_KHZ) + -- multiply by target audio signal level + -- devide by available audio signal depth + currentThreasHold := ((INPUT_CLK_HZ/INPUT_AUDIO_HZ) * to_integer(unsigned(inMusicData))) / (INPUT_DEPTH); + + -- check if PWM duty cicle is high enough: currentThreasHold has to be variable otherwise first check count = 1 one to late + if (count >= currentThreasHold) then + -- no pwm output + outMusic <= '0'; + else + -- keep pwm high + outMusic <= '1'; + end if; + + -- + count <= count + 1; + + -- check for max level + -- if counter is >= the max amount of pulses per audio sample + if (count >= (INPUT_CLK_HZ/INPUT_AUDIO_HZ)) then + -- Next audio sample + count <= 1; + end if; + + + + + end if; + end process; + +end Behavioral; diff --git a/src/PlayAudio.vhd b/src/PlayAudio.vhd new file mode 100644 index 0000000..a916d3e --- /dev/null +++ b/src/PlayAudio.vhd @@ -0,0 +1,77 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity PlayAudio is + generic( + CLK_KHZ: integer := 100000 + ); + Port ( reset, clk100 : in STD_LOGIC; + outMusic : out STD_LOGIC); +end PlayAudio; + +architecture Behavioral of PlayAudio is + component SampleOut is + generic( + INPUT_DEPTH: integer := 256; + INPUT_SAMPLE_SIZE: integer := 36984; + INPUT_AUDIO_KHZ: integer := 44; + INPUT_CLK_KHZ: integer := 100000 + ); + Port ( reset, clk : in STD_LOGIC; + inCOEData : in STD_LOGIC_VECTOR(7 downto 0); + outCOEData : out STD_LOGIC_VECTOR(7 downto 0); + outCOEAddress : out STD_LOGIC_VECTOR(15 downto 0) + ); + end component; + + component AudioOut is + generic( + INPUT_DEPTH: integer := 256; + INPUT_SAMPLE_SIZE: integer := 36984; + INPUT_AUDIO_KHZ: integer := 44; + INPUT_CLK_KHZ: integer := 100000 + ); + Port ( reset, clk : in STD_LOGIC; + inMusicData : in STD_LOGIC_VECTOR(7 downto 0); + outMusic : out STD_LOGIC); + end component; + + component BertErnie44Audio IS + PORT ( + clka : IN STD_LOGIC; + addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END component; + + +signal COEAddress :STD_LOGIC_VECTOR(15 DOWNTO 0); +signal COEData :STD_LOGIC_VECTOR(7 DOWNTO 0); +signal MusicLevel:STD_LOGIC_VECTOR(7 DOWNTO 0); + +begin + -- map ports + SampleOut0: SampleOut Port Map( + reset => reset, + clk => clk100, + inCOEData => COEData, + outCOEData => MusicLevel, + outCOEAddress => COEAddress + ); + + -- map ports + AudioOut0: AudioOut Port Map( + reset => reset, + clk => clk100, + inMusicData => MusicLevel, + outMusic => outMusic + ); + + -- map ports + BertErnie44Audio0: BertErnie44Audio Port Map( + clka => clk100, + addra => COEAddress, + douta => COEData + ); + +end Behavioral; diff --git a/src/SampleOut.vhd b/src/SampleOut.vhd new file mode 100644 index 0000000..bd2d2dc --- /dev/null +++ b/src/SampleOut.vhd @@ -0,0 +1,65 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity SampleOut is + generic( + INPUT_DEPTH: integer := 256; + INPUT_SAMPLE_SIZE: integer := 36984; + INPUT_AUDIO_HZ: integer := 44100; + INPUT_CLK_HZ: integer := 100000000 + ); + Port ( reset, clk : in STD_LOGIC; + inCOEData : in STD_LOGIC_VECTOR(7 downto 0); + outCOEData : out STD_LOGIC_VECTOR(7 downto 0); + outCOEAddress : out STD_LOGIC_VECTOR(15 downto 0) + ); +end SampleOut; + +architecture Behavioral of SampleOut is + signal count: integer; + signal COEAddress: integer; + +begin + outCOEData <= inCOEData; + + process (reset, clk) + --variable currentThreasHold: integer; + begin + -- if reset + if (reset = '1') then + -- default values for outputs, so output state is always defined + outCOEAddress <= (others => '0'); + count <= 0; + COEAddress <= 0; + -- + elsif rising_edge(clk) then + -- default values for outputs, so output state is always defined + outCOEAddress <= (others => '0'); + count <= 0; + COEAddress <= 0; + + -- start code + outCOEAddress <= std_logic_vector (to_unsigned(COEAddress, outCOEAddress'length)); + count <= count + 1; + COEAddress <= COEAddress; + + -- if counter is >= the max amount of pulses per audio sample + if (count >= INPUT_CLK_HZ/INPUT_AUDIO_HZ) then -- Next audio sample + count <= 0; + COEAddress <= COEAddress + 1; --todo: check timing delay + -- add + 1 becouse COEAddress is signal updated ad end of process + outCOEAddress <= std_logic_vector (to_unsigned(COEAddress + 1, outCOEAddress'length)); + + -- check for max level: add + 1 becouse COEAddress is signal updated ad end of process + if (COEAddress + 1 >= INPUT_SAMPLE_SIZE) then + -- First audio sample + outCOEAddress <= (others => '0'); + COEAddress <= 0; + end if; + end if; + end if; + end process; + +end Behavioral; -- cgit v1.2.3