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-rw-r--r--src/alu.vhd73
-rw-r--r--src/eq8b.vhd3
-rw-r--r--src/min8b.vhd30
-rw-r--r--src/min8b_tb.vhd51
-rw-r--r--src/twoc.vhd10
-rw-r--r--src/twoc_tb.vhd46
6 files changed, 173 insertions, 40 deletions
diff --git a/src/alu.vhd b/src/alu.vhd
index 0022b4e..7da5696 100644
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -25,7 +25,8 @@ architecture Behavioral of ALU is
R_RotateRightA,
R_AllZeros,
R_AllOnes,
- R: std_logic_vector(7 downto 0);
+ R: std_logic_vector(7 downto 0) := (others => '0');
+ signal C_AMinB, C_BMinA, C_MinA, C_MinB: std_logic := '0'; -- Minus carry out (test bench edge case)
component add8b is
port (
A: in std_logic_vector(7 downto 0);
@@ -45,7 +46,8 @@ architecture Behavioral of ALU is
component twoc is
port (
A: in std_logic_vector(7 downto 0);
- X: out std_logic_vector(7 downto 0));
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
end component;
component sl8b is
port (
@@ -91,65 +93,82 @@ begin
B => B,
Cin => '0',
X => R_AminB,
- Cout => open);
+ Cout => C_AMinB);
BminA: component min8b
port map(
A => B,
B => A,
Cin => '0',
X => R_BminA,
- Cout => open);
+ Cout => C_BMinA);
R_OnlyA <= A;
R_OnlyB <= B;
MinA: component twoc
- port map(A => A, X => R_MinA);
+ port map(
+ A => A,
+ X => R_MinA,
+ Cout => C_MinA);
MinB: component twoc
- port map(A => B, X => R_MinA);
+ port map(
+ A => B,
+ X => R_MinB,
+ Cout => C_MinB);
ShiftLeftA: component sl8b
port map(
A => A,
- S => B,
+ S => x"01",
X => R_ShiftLeftA);
ShiftRightA: component sr8b
port map(
A => A,
- S => B,
+ S => x"01",
X => R_ShiftRightA);
RotateLeftA: component rl8b
port map(
A => A,
- S => B,
+ S => x"01",
X => R_RotateLeftA);
RotateRightA: component rr8b
port map(
A => A,
- S => B,
+ S => x"01",
X => R_RotateRightA);
with Op select
R <=
- R_AplusB when x"0",
- R_AminB when x"1",
- R_BminA when x"2",
- R_Dummy when x"3",
- R_OnlyA when x"4",
- R_OnlyB when x"5",
- R_MinA when x"6",
- R_MinB when x"7",
- R_ShiftLeftA when x"8",
- R_ShiftRightA when x"9",
- R_RotateLeftA when x"a",
- R_RotateRightA when x"b",
- R_Dummy when x"c",
- R_Dummy when x"d",
- R_AllZeros when x"e",
- R_AllOnes when x"f",
+ R_AplusB when x"0", -- AplusB
+ R_AminB when x"1", -- AminB
+ R_BminA when x"2", -- BminA
+ R_Dummy when x"3", -- Dummy
+ R_OnlyA when x"4", -- OnlyA
+ R_OnlyB when x"5", -- OnlyB
+ R_MinA when x"6", -- MinA
+ R_MinB when x"7", -- MinB
+ R_ShiftLeftA when x"8", -- ShiftLeftA
+ R_ShiftRightA when x"9", -- ShiftRightA
+ R_RotateLeftA when x"a", -- RotateLeftA
+ R_RotateRightA when x"b", -- RotateRightA
+ R_Dummy when x"c", -- Dummy
+ R_Dummy when x"d", -- Dummy
+ R_AllZeros when x"e", -- AllZeros
+ R_AllOnes when x"f", -- AllOnes
(others => '0') when others;
+ with Op select
+ Cout <=
+ R(7) when x"0" | x"3" | x"c" | x"d", -- AplusB, MinA, MinB, Dummy
+ C_AMinB when x"1", -- AminB
+ C_BMinA when x"2", -- BminA
+ A(7) when x"4" | x"8" | x"a", -- OnlyA, ShiftLeftA, RotateLeftA
+ B(7) when x"5", -- OnlyB
+ C_MinA when x"6", -- MinA TODO FIX
+ C_MinB when x"7", -- MinB TODO FIX
+ '0' when x"9" | x"b" | x"e", -- ShiftRightA, RotateRightA, AllZeros
+ '1' when x"f", -- AllOnes
+ '0' when others;
eq: component eq8b
port map(
A => A,
B => B,
Equal => Equal);
Res <= R;
- Cout <= R(7);
end Behavioral;
diff --git a/src/eq8b.vhd b/src/eq8b.vhd
index 0c382a8..1f929e5 100644
--- a/src/eq8b.vhd
+++ b/src/eq8b.vhd
@@ -4,8 +4,7 @@ USE ieee.numeric_std.all;
entity eq8b is
port (
- A: in std_logic_vector(7 downto 0);
- B: in std_logic_vector(7 downto 0);
+ A, B: in std_logic_vector(7 downto 0);
Equal: out std_logic);
end eq8b;
diff --git a/src/min8b.vhd b/src/min8b.vhd
index f2623aa..898d3c7 100644
--- a/src/min8b.vhd
+++ b/src/min8b.vhd
@@ -4,8 +4,7 @@ USE ieee.numeric_std.all;
entity min8b is
port (
- A: in std_logic_vector(7 downto 0);
- B: in std_logic_vector(7 downto 0);
+ A, B: in std_logic_vector(7 downto 0);
Cin: in std_logic;
X: out std_logic_vector(7 downto 0);
Cout: out std_logic);
@@ -13,29 +12,44 @@ end min8b;
architecture Behavioral of min8b is
signal Bmin: std_logic_vector(7 downto 0);
+ signal Bcom: std_logic;
+ signal carry: std_logic;
component twoc
port (
A: in std_logic_vector(7 downto 0);
- X: out std_logic_vector(7 downto 0));
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
end component;
component add8b
port (
- A: in std_logic_vector(7 downto 0);
- B: in std_logic_vector(7 downto 0);
+ A, B: in std_logic_vector(7 downto 0);
Cin: in std_logic;
X: out std_logic_vector(7 downto 0);
Cout: out std_logic);
end component;
+ component add1b
+ port (
+ A, B, Cin: in std_logic;
+ X, Cout: out std_logic);
+ end component;
begin
complement: component twoc
port map (
A => B,
- X => Bmin);
- add: component add8b
+ X => Bmin,
+ Cout => Bcom);
+ add8: component add8b
port map (
A => A,
B => Bmin,
Cin => Cin,
X => X,
- Cout => Cout);
+ Cout => carry);
+ add1: component add1b
+ port map(
+ A => A(7),
+ B => Bcom,
+ Cin => carry,
+ X => Cout,
+ Cout => open);
end Behavioral;
diff --git a/src/min8b_tb.vhd b/src/min8b_tb.vhd
new file mode 100644
index 0000000..fb22cb0
--- /dev/null
+++ b/src/min8b_tb.vhd
@@ -0,0 +1,51 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity min8b_tb is
+end min8b_tb;
+
+architecture behavioral of min8b_tb is
+ component min8b
+ port (
+ A: in std_logic_vector(7 downto 0);
+ B: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
+ end component;
+ signal A: std_logic_vector(7 downto 0);
+ signal B: std_logic_vector(7 downto 0);
+ signal Cin: std_logic;
+ signal test_case: std_logic_vector(7 downto 0) := (others => '0');
+ signal Cout: std_logic;
+ signal OK: boolean := true;
+begin
+ UUT: component twoc
+ port map(
+ A => A,
+ X => X);
+
+ tb: process
+ variable temp: std_logic_vector(8 downto 0);
+ begin
+ Cin <= '0';
+ for i in 0 to 255 loop
+ test_case <= std_logic_vector(to_unsigned(i,8));
+ wait for 1 ps;
+ A <= test_case;
+
+ X_t := -i;
+
+ wait for 5 ns;
+ if to_signed(X_t, 8) /= signed(X) then
+ OK <= false;
+ end if;
+ wait for 5 ns;
+ end loop;
+ wait; -- stop for simulator
+ end process;
+end;
diff --git a/src/twoc.vhd b/src/twoc.vhd
index 5c86056..7a2c89d 100644
--- a/src/twoc.vhd
+++ b/src/twoc.vhd
@@ -5,11 +5,13 @@ USE ieee.numeric_std.all;
entity twoc is
port (
A: in std_logic_vector(7 downto 0);
- X: out std_logic_vector(7 downto 0));
+ X: out std_logic_vector(7 downto 0);
+ Cout: out std_logic);
end twoc;
architecture Behavioral of twoc is
signal NA: std_logic_vector(7 downto 0); -- not A
+ signal A0: std_logic; -- A = 0
component add8b is
port (
A: in std_logic_vector(7 downto 0);
@@ -23,7 +25,9 @@ begin
add: component add8b -- add one
port map (
A => NA,
- B => "00000001",
+ B => x"01",
Cin => '0',
- X => X);
+ X => X,
+ Cout => A0);
+ Cout <= not (A0 or A(7));
end Behavioral;
diff --git a/src/twoc_tb.vhd b/src/twoc_tb.vhd
new file mode 100644
index 0000000..fc53bea
--- /dev/null
+++ b/src/twoc_tb.vhd
@@ -0,0 +1,46 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use unisim.vcomponents.all;
+
+entity twoc_tb is
+end twoc_tb;
+
+architecture behavioral of twoc_tb is
+ component twoc
+ port (
+ A: in std_logic_vector(7 downto 0);
+ X: out std_logic_vector(7 downto 0));
+ end component;
+ signal A: std_logic_vector(7 downto 0);
+ signal X: std_logic_vector(7 downto 0);
+ signal test_case: std_logic_vector(7 downto 0) := (others => '0');
+ signal OK: boolean := true;
+begin
+ UUT: component twoc
+ port map(
+ A => A,
+ X => X);
+
+ tb: process
+ variable X_t: integer;
+
+ begin
+ for i in 0 to 255 loop
+ test_case <= std_logic_vector(to_unsigned(i,8));
+ wait for 1 ps;
+ A <= test_case;
+
+ X_t := -i;
+
+ wait for 5 ns;
+ if to_signed(X_t, 8) /= signed(X) then
+ OK <= false;
+ end if;
+ wait for 5 ns;
+ end loop;
+ wait; -- stop for simulator
+ end process;
+end;