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-rw-r--r--src/alu.vhd3
-rw-r--r--src/bcddec.vhd5
-rw-r--r--src/bin2bcd.vhd41
-rw-r--r--src/bin2bcd5.vhd33
-rw-r--r--src/bin2bcd5_tb.vhd (renamed from src/bin2bcd_tb.vhd)0
-rw-r--r--src/bin2bcd8.vhd18
-rw-r--r--src/bin2bcd8_tb.vhd48
-rw-r--r--src/main-alu.vhd39
-rw-r--r--src/min8b.vhd2
-rw-r--r--src/stopp.vhd17
-rw-r--r--src/twoc.vhd28
11 files changed, 110 insertions, 124 deletions
diff --git a/src/alu.vhd b/src/alu.vhd
index 1d3a1e8..edaee52 100644
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -60,6 +60,7 @@ architecture Behavioral of ALU is
component twoc is
port (
A: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
X: out std_logic_vector(7 downto 0);
Cout: out std_logic);
end component;
@@ -120,11 +121,13 @@ begin
MinA: component twoc
port map(
A => A,
+ Cin => A(7),
X => R_MinA,
Cout => C_MinA);
MinB: component twoc
port map(
A => B,
+ Cin => B(7),
X => R_MinB,
Cout => C_MinB);
ShiftLeftA: component sl8b
diff --git a/src/bcddec.vhd b/src/bcddec.vhd
index cee9a97..ccb251d 100644
--- a/src/bcddec.vhd
+++ b/src/bcddec.vhd
@@ -17,6 +17,9 @@ begin
"01111101" when A = "0110" else
"00100111" when A = "0111" else
"01111111" when A = "1000" else
- "01101111" when A = "1001";
+ "01101111" when A = "1001" else
+ "00000000" when A = "1010" else
+ "01000000" when A = "1011" else
+ "00000000";
end Behavioral;
diff --git a/src/bin2bcd.vhd b/src/bin2bcd.vhd
index 548c9e5..6d7ac07 100644
--- a/src/bin2bcd.vhd
+++ b/src/bin2bcd.vhd
@@ -1,33 +1,20 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+-- use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
-entity bin2bcd is port(
- I: in std_logic_vector(4 downto 0);
- X: out std_logic_vector(3 downto 0);
- Y: out std_logic_vector(3 downto 0));
+entity bin2bcd is
+ generic(
+ width: integer := 8);
+ port(
+ A: in std_logic_vector(width-1 downto 0); -- binary input (unsigned 8-bit)
+ X: out std_logic_vector(3 downto 0); -- bcd output
+ R: out std_logic_vector(width-1 downto 0)); -- remainder after operation
end bin2bcd;
architecture Behavioral of bin2bcd is
begin
- with I select
- X <=
- b"0000" when b"00000" | b"01010" | b"10100" | b"11110",
- b"0001" when b"00001" | b"01011" | b"10101" | b"11111",
- b"0010" when b"00010" | b"01100" | b"10110",
- b"0011" when b"00011" | b"01101" | b"10111",
- b"0100" when b"00100" | b"01110" | b"11000",
- b"0101" when b"00101" | b"01111" | b"11001",
- b"0110" when b"00110" | b"10000" | b"11010",
- b"0111" when b"00111" | b"10001" | b"11011",
- b"1000" when b"01000" | b"10010" | b"11100",
- b"1001" when b"01001" | b"10011" | b"11101",
- (others => '0') when others;
- with I select
- Y <=
- b"0000" when b"00000" | b"00001" | b"00010" | b"00011" | b"00100" | b"00101" | b"00110" | b"00111" | b"01000" | b"01001",
- b"0001" when b"01010" | b"01011" | b"01100" | b"01101" | b"01110" | b"01111" | b"10000" | b"10001" | b"10010" | b"10011",
- b"0010" when b"10100" | b"10101" | b"10110" | b"10111" | b"11000" | b"11001" | b"11010" | b"11011" | b"11100" | b"11101",
- b"0011" when b"11110" | b"11111",
- (others => '0') when others;
+ X <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) mod 10, 4));
+ R <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) / 10, width));
end Behavioral;
-
diff --git a/src/bin2bcd5.vhd b/src/bin2bcd5.vhd
new file mode 100644
index 0000000..548c9e5
--- /dev/null
+++ b/src/bin2bcd5.vhd
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity bin2bcd is port(
+ I: in std_logic_vector(4 downto 0);
+ X: out std_logic_vector(3 downto 0);
+ Y: out std_logic_vector(3 downto 0));
+end bin2bcd;
+
+architecture Behavioral of bin2bcd is
+begin
+ with I select
+ X <=
+ b"0000" when b"00000" | b"01010" | b"10100" | b"11110",
+ b"0001" when b"00001" | b"01011" | b"10101" | b"11111",
+ b"0010" when b"00010" | b"01100" | b"10110",
+ b"0011" when b"00011" | b"01101" | b"10111",
+ b"0100" when b"00100" | b"01110" | b"11000",
+ b"0101" when b"00101" | b"01111" | b"11001",
+ b"0110" when b"00110" | b"10000" | b"11010",
+ b"0111" when b"00111" | b"10001" | b"11011",
+ b"1000" when b"01000" | b"10010" | b"11100",
+ b"1001" when b"01001" | b"10011" | b"11101",
+ (others => '0') when others;
+ with I select
+ Y <=
+ b"0000" when b"00000" | b"00001" | b"00010" | b"00011" | b"00100" | b"00101" | b"00110" | b"00111" | b"01000" | b"01001",
+ b"0001" when b"01010" | b"01011" | b"01100" | b"01101" | b"01110" | b"01111" | b"10000" | b"10001" | b"10010" | b"10011",
+ b"0010" when b"10100" | b"10101" | b"10110" | b"10111" | b"11000" | b"11001" | b"11010" | b"11011" | b"11100" | b"11101",
+ b"0011" when b"11110" | b"11111",
+ (others => '0') when others;
+end Behavioral;
+
diff --git a/src/bin2bcd_tb.vhd b/src/bin2bcd5_tb.vhd
index a8d3ba8..a8d3ba8 100644
--- a/src/bin2bcd_tb.vhd
+++ b/src/bin2bcd5_tb.vhd
diff --git a/src/bin2bcd8.vhd b/src/bin2bcd8.vhd
deleted file mode 100644
index 47a88d2..0000000
--- a/src/bin2bcd8.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
--- use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity bin2bcd8 is
- port(
- A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit)
- X: out std_logic_vector(3 downto 0); -- bcd output
- R: out std_logic_vector(7 downto 0)); -- remainder after operation
-end bin2bcd8;
-
-architecture Behavioral of bin2bcd8 is
-begin
- X <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) mod 10, 4));
- R <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) / 10, 8));
-end Behavioral;
diff --git a/src/bin2bcd8_tb.vhd b/src/bin2bcd8_tb.vhd
deleted file mode 100644
index 4e24471..0000000
--- a/src/bin2bcd8_tb.vhd
+++ /dev/null
@@ -1,48 +0,0 @@
-library ieee;
-library unisim;
-
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use unisim.vcomponents.all;
-
-entity bin2bcd8_tb is
-end bin2bcd8_tb;
-
-architecture Behavioral of bin2bcd8_tb is
-component bin2bcd8 port(
- A: in std_logic_vector(7 downto 0); -- binary input (unsigned 8-bit)
- X: out std_logic_vector(3 downto 0); -- bcd output
- R: out std_logic_vector(7 downto 0)); -- remainder after operation
-end component;
--- test input
-signal I: std_logic_vector(7 downto 0) := (others => '0');
--- test output
-signal X: std_logic_vector(3 downto 0);
-signal R: std_logic_vector(7 downto 0);
-
-signal test_case: std_logic_vector(7 downto 0);
-signal OK: boolean := true;
-begin
- test: bin2bcd8 port map(
- A => I,
- X => X,
- R => R);
-
- tb: process
- -- expected output
- variable X_t: integer := 0;
- variable Y_t: integer := 0;
- begin
-
- for test_i in 0 to 255 loop
- test_case <= std_logic_vector(to_unsigned(test_i,8));
- wait for 1 ps;
-
- I <= test_case;
-
- wait for 10 ns;
- end loop;
- wait; -- stop simulator
- end process;
-end Behavioral;
-
diff --git a/src/main-alu.vhd b/src/main-alu.vhd
index 8bb2f0e..ffc46f8 100644
--- a/src/main-alu.vhd
+++ b/src/main-alu.vhd
@@ -22,14 +22,16 @@ architecture Behavioral of main is
end component;
component stopp
port(
- A: in std_logic_vector(7 downto 0);
- X: out std_logic_vector(7 downto 0));
+ A: in std_logic_vector(8 downto 0);
+ X: out std_logic_vector(8 downto 0));
end component;
- component bin2bcd8
+ component bin2bcd
+ generic(
+ width: integer := 9);
port(
- A: in std_logic_vector(7 downto 0);
+ A: in std_logic_vector(width-1 downto 0);
X: out std_logic_vector(3 downto 0);
- R: out std_logic_vector(7 downto 0));
+ R: out std_logic_vector(width-1 downto 0));
end component;
component bcd2disp
port(
@@ -39,12 +41,12 @@ architecture Behavioral of main is
DS: out std_logic_vector(3 downto 0));
end component;
- signal ALU_OUT: std_logic_vector(7 downto 0);
- signal ALU_COUT, ALU_EQ: std_logic;
- signal DISP_NUM: std_logic_vector(7 downto 0);
+ signal CALC_NUM: std_logic_vector(8 downto 0);
+ signal ALU_EQ: std_logic;
+ signal DISP_NUM: std_logic_vector(8 downto 0);
signal N0, N1, N2, N3: std_logic_vector(3 downto 0);
- signal NC0, NC1: std_logic_vector(7 downto 0); -- carry from bin2bcd8
- signal CLK_T: std_logic_vector(18 downto 0); -- clock counter for display clock
+ signal NC0, NC1: std_logic_vector(8 downto 0); -- carry from bin2bcd8
+ signal CLK_T: std_logic_vector(17 downto 0); -- clock counter for display clock
begin
process(CLK)
begin
@@ -58,35 +60,36 @@ begin
A => A,
B => B,
Op => Op,
- Res => ALU_OUT,
- Cout => ALU_COUT,
+ Res => CALC_NUM(7 downto 0),
+ Cout => CALC_NUM(8),
Equal => ALU_EQ);
topos: component stopp
port map(
- A => ALU_OUT,
+ A => CALC_NUM,
X => DISP_NUM);
- bcd0: component bin2bcd8
+ bcd0: component bin2bcd
port map(
A => DISP_NUM,
X => N0,
R => NC0);
- bcd1: component bin2bcd8
+ bcd1: component bin2bcd
port map(
A => NC0,
X => N1,
R => NC1);
- bcd2: component bin2bcd8
+ bcd2: component bin2bcd
port map(
A => NC1,
X => N2,
R => open);
+ N3 <= "1011" when CALC_NUM(8) = '1' else "1010";
disp: component bcd2disp
port map(
- CLK => CLK_T(18),
- N0 => "0000",
+ CLK => CLK_T(17),
+ N0 => N3,
N1 => N2,
N2 => N1,
N3 => N0,
diff --git a/src/min8b.vhd b/src/min8b.vhd
index 898d3c7..2a7b51e 100644
--- a/src/min8b.vhd
+++ b/src/min8b.vhd
@@ -17,6 +17,7 @@ architecture Behavioral of min8b is
component twoc
port (
A: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
X: out std_logic_vector(7 downto 0);
Cout: out std_logic);
end component;
@@ -36,6 +37,7 @@ begin
complement: component twoc
port map (
A => B,
+ Cin => B(7),
X => Bmin,
Cout => Bcom);
add8: component add8b
diff --git a/src/stopp.vhd b/src/stopp.vhd
index b601b61..40ec728 100644
--- a/src/stopp.vhd
+++ b/src/stopp.vhd
@@ -3,20 +3,25 @@ use ieee.std_logic_1164.all;
entity stopp is
port(
- A: in std_logic_vector(7 downto 0);
- X: out std_logic_vector(7 downto 0));
+ A: in std_logic_vector(8 downto 0);
+ X: out std_logic_vector(8 downto 0));
end stopp;
architecture Behavioral of stopp is
component twoc
port (
A: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
X: out std_logic_vector(7 downto 0);
- Cout: out std_logic);
+ Cout: out std_logic);
end component;
- signal ntop: std_logic_vector(7 downto 0);
+ signal ntop: std_logic_vector(8 downto 0);
begin
inv: component twoc
- port map(A => A, X => ntop);
- X <= ntop when A(7) = '1' else A;
+ port map(
+ A => A(7 downto 0),
+ Cin => A(8),
+ X => ntop(7 downto 0),
+ Cout => ntop(8));
+ X <= ntop when A(8) = '1' else A;
end Behavioral;
diff --git a/src/twoc.vhd b/src/twoc.vhd
index 7a2c89d..16293ac 100644
--- a/src/twoc.vhd
+++ b/src/twoc.vhd
@@ -5,29 +5,45 @@ USE ieee.numeric_std.all;
entity twoc is
port (
A: in std_logic_vector(7 downto 0);
+ Cin: in std_logic;
X: out std_logic_vector(7 downto 0);
Cout: out std_logic);
end twoc;
architecture Behavioral of twoc is
signal NA: std_logic_vector(7 downto 0); -- not A
- signal A0: std_logic; -- A = 0
+ signal NC: std_logic; -- not Cin
+ signal C: std_logic; -- carry from 8-bit adder to 1-bit adder
component add8b is
port (
- A: in std_logic_vector(7 downto 0);
- B: in std_logic_vector(7 downto 0);
+ A, B: in std_logic_vector(7 downto 0);
Cin: in std_logic;
X: out std_logic_vector(7 downto 0);
Cout: out std_logic);
end component;
+ component add1b is
+ port (
+ A, B: in std_logic;
+ Cin: in std_logic;
+ X: out std_logic;
+ Cout: out std_logic);
+ end component;
begin
NA <= not A; -- invert A
- add: component add8b -- add one
+ NC <= not Cin; -- invert Cin
+
+ add1: component add8b -- add one
port map (
A => NA,
B => x"01",
Cin => '0',
X => X,
- Cout => A0);
- Cout <= not (A0 or A(7));
+ Cout => C);
+ add2: component add1b -- sign bit
+ port map (
+ A => NC,
+ B => '0',
+ Cin => C,
+ X => Cout,
+ Cout => open);
end Behavioral;