diff options
Diffstat (limited to 'src/vga.vhd')
| -rw-r--r-- | src/vga.vhd | 37 |
1 files changed, 9 insertions, 28 deletions
diff --git a/src/vga.vhd b/src/vga.vhd index 6e06afb..16becca 100644 --- a/src/vga.vhd +++ b/src/vga.vhd @@ -6,33 +6,16 @@ use ieee.std_logic_unsigned.all; entity vga is
port (
clk25, reset: in std_logic;
- red, green, blue: out std_logic;
+ x, y: out std_logic_vector(9 downto 0);
+ rgb: in std_logic_vector(11 downto 0);
+ red, green, blue: out std_logic_vector(3 downto 0);
hsync, vsync: out std_logic);
end vga;
architecture Behavioral of vga is
signal hcount: std_logic_vector(9 downto 0);
signal vcount: std_logic_vector(9 downto 0);
- component pixeldata
- port (
- pixel_clk, bounce_clk, reset: in std_logic;
- x, y: in std_logic_vector(9 downto 0);
- red, green, blue: out std_logic);
- end component;
- signal bounce_clk: std_logic;
- signal x, y: std_logic_vector(9 downto 0);
- signal pr, pg, pb: std_logic;
begin
- pixel: component pixeldata
- port map (
- pixel_clk => clk25,
- bounce_clk => bounce_clk,
- reset => reset,
- x => x,
- y => y,
- red => pr,
- green => pg,
- blue => pb);
process (clk25)
begin
@@ -40,13 +23,13 @@ begin if (hcount >= 144) and (hcount < 784) and (vcount >= 31) and (vcount < 511) then
x <= hcount - 144;
y <= vcount - 31;
- red <= pr;
- green <= pg;
- blue <= pb;
+ red <= rgb(11 downto 8);
+ green <= rgb(7 downto 4);
+ blue <= rgb(3 downto 0);
else
- red <= '0';
- green <= '0';
- blue <= '0';
+ red <= x"0";
+ green <= x"0";
+ blue <= x"0";
end if;
if hcount < 97 then
@@ -57,10 +40,8 @@ begin if vcount < 3 then
vsync <= '0';
- bounce_clk <= '1';
else
vsync <= '1';
- bounce_clk <= '0';
end if;
hcount <= hcount + 1;
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