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l---------[-rw-r--r--]full-adder/full-adder.srcs/sim_1/add1b_tb.vhd73
l---------[-rw-r--r--]full-adder/full-adder.srcs/sim_1/add4b_tb.vhd92
l---------[-rw-r--r--]full-adder/full-adder.srcs/sources_1/add1b.vhd44
l---------[-rw-r--r--]full-adder/full-adder.srcs/sources_1/add4b.vhd59
l---------[-rw-r--r--]full-adder/full-adder.srcs/sources_1/half_add.vhd19
-rw-r--r--full-adder/full-adder.xpr2
6 files changed, 6 insertions, 283 deletions
diff --git a/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd b/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd
index 18f05eb..b512ac5 100644..120000
--- a/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd
+++ b/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd
@@ -1,72 +1 @@
-library ieee;
-library unisim;
-
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use unisim.vcomponents.all;
-
-entity add1b_tb is
-end add1b_tb;
-
-architecture behavioral of add1b_tb is
-component add1b
-port (
- A: in std_logic;
- B: in std_logic;
- Cin: in std_logic;
- X: out std_logic;
- Cout: out std_logic);
-end component;
-
-signal A: std_logic;
-signal B: std_logic;
-signal Cin: std_logic;
-signal X: std_logic;
-signal Cout: std_logic;
-signal test_case: std_logic_vector(2 downto 0);
-signal ok: boolean := true;
-
-begin
- test_port: add1b port map(
- A => A,
- B => B,
- X => X,
- Cout => Cout,
- Cin => Cin);
-
- tb: process
- variable A_t: std_logic;
- variable B_t: std_logic;
- variable Cin_t: std_logic;
- variable X_t: std_logic;
- variable Cout_t: std_logic;
- variable Out_t: std_logic_vector(1 downto 0);
-
- begin
- for i in 0 to 7 loop
- test_case <= std_logic_vector(to_unsigned(i,3));
- wait for 1 ps;
-
- A <= test_case(0);
- B <= test_case(1);
- Cin <= test_case(2);
-
- A_t := test_case(0);
- B_t := test_case(1);
- Cin_t := test_case(2);
-
- X_t := A_t xor B_t xor Cin_t;
- Cout_t := (A_t and B_t) or (B_t and Cin_t) or (Cin_t and A_t);
-
- wait for 5 ns;
- If X /= X_t then
- OK <= false;
- end if;
- if Cout /= Cout_t then
- OK <= false;
- end if;
- wait for 5 ns;
- end loop;
- wait; -- stop for simulator
- end process;
-end;
+../../../src/add1b_tb.vhd \ No newline at end of file
diff --git a/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd
index e5e548c..8b698f7 100644..120000
--- a/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd
+++ b/full-adder/full-adder.srcs/sim_1/add4b_tb.vhd
@@ -1,91 +1 @@
-library ieee;
-library unisim;
-
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use unisim.vcomponents.all;
-
-entity add4b_tb is
-end add4b_tb;
-
-architecture behavioral of add4b_tb is component add4b
- port (
- A: in std_logic_vector(3 downto 0);
- B: in std_logic_vector(3 downto 0);
- Cin: in std_logic;
- X: out std_logic_vector(3 downto 0);
- Cout: out std_logic);
-end component;
-
-signal A: std_logic_vector(3 downto 0);
-signal B: std_logic_vector(3 downto 0);
-signal S: std_logic_vector(3 downto 0);
-signal C_out : STD_LOGIC;
-signal C_in : STD_LOGIC;
-signal Test_case: STD_LOGIC_VECTOR (7 downto 0):= (others =>'0');
-signal OK: boolean := true;
-
-begin
- UUT: add4b port map(
- A => A,
- B => B,
- X => S,
- Cout => C_out,
- Cin => C_in);
-
- tb: process
- variable S0_t : STD_LOGIC;
- variable S1_t : STD_LOGIC;
- variable S2_t : STD_LOGIC;
- variable S3_t : STD_LOGIC;
- variable C_out_t : STD_LOGIC;
- variable A_t : integer;
- variable B_t : integer;
- variable sum : integer;
-
- begin
- C_in <= '0'; -- C_in is ignored in this test
- for I in 0 to 255 loop
-
- Test_case <= Std_logic_vector(to_unsigned(I,8));
- wait for 1 ps;
- A(0) <= Test_case(0);
- A(1) <= Test_case(1);
- A(2) <= Test_case(2);
- A(3) <= Test_case(3);
- B(0) <= Test_case(4);
- B(1) <= Test_case(5);
- B(2) <= Test_case(6);
- B(3) <= Test_case(7);
-
- A_t := To_integer(unsigned(test_case(3 downto 0)));
- B_t := To_integer(unsigned(test_case(7 downto 4)));
- sum := A_t+B_t;
-
- S0_t := to_unsigned(sum,5)(0);
- S1_t := to_unsigned(sum,5)(1);
- S2_t := to_unsigned(sum,5)(2);
- S3_t := to_unsigned(sum,5)(3);
- C_out_t := to_unsigned(sum,5)(4);
-
- wait for 5 ns;
- If S(0) /= S0_t then
- OK <= false;
- end if;
- if S(1) /= S1_t then
- OK <= false;
- end if;
- if S(2) /= S2_t then
- OK <= false;
- end if;
- if S(3) /= S3_t then
- OK <= false;
- end if;
- if C_out /= C_out_t then
- OK <= false;
- end if;
- wait for 5 ns;
- end loop;
- wait; -- stop for simulator
- end process;
-end;
+../../../src/add4b_tb.vhd \ No newline at end of file
diff --git a/full-adder/full-adder.srcs/sources_1/add1b.vhd b/full-adder/full-adder.srcs/sources_1/add1b.vhd
index a2d4068..9ad3f1e 100644..120000
--- a/full-adder/full-adder.srcs/sources_1/add1b.vhd
+++ b/full-adder/full-adder.srcs/sources_1/add1b.vhd
@@ -1,43 +1 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- full adder entity
-entity add1b is
- port (
- A: in std_logic;
- B: in std_logic;
- Cin: in std_logic;
- X: out std_logic;
- Cout: out std_logic);
-end add1b;
-
-architecture Behavioral of add1b is
- signal s0: std_logic;
- signal s1: std_logic;
- signal s2: std_logic;
- component half_add
- port (
- A: in std_logic;
- B: in std_logic;
- X: out std_logic;
- Cout: out std_logic);
- end component;
-begin
- -- first add A and B with HA
- add0: component half_add
- port map (
- A => A,
- B => B,
- X => s0,
- Cout => s1);
- -- then add first result with Cin to get final result
- add1: component half_add
- port map (
- A => Cin,
- B => s0,
- X => X,
- Cout => s2);
- -- calculate Cout by OR-ing the Cout of both half adders
- Cout <= (s2 OR s1);
-end Behavioral;
+../../../src/add1b.vhd \ No newline at end of file
diff --git a/full-adder/full-adder.srcs/sources_1/add4b.vhd b/full-adder/full-adder.srcs/sources_1/add4b.vhd
index 07e5a22..5245cd0 100644..120000
--- a/full-adder/full-adder.srcs/sources_1/add4b.vhd
+++ b/full-adder/full-adder.srcs/sources_1/add4b.vhd
@@ -1,58 +1 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- full 4-bit adder entity
-entity add4b is
- port (
- A: in std_logic_vector(3 downto 0);
- B: in std_logic_vector(3 downto 0);
- Cin: in std_logic;
- X: out std_logic_vector(3 downto 0);
- Cout: out std_logic);
-end add4b;
-
-architecture Behavioral of add4b is
- signal C0: std_logic; -- Cout0 -> Cin1
- signal C1: std_logic; -- Cout1 -> Cin2
- signal C2: std_logic; -- Cout2 -> Cin3
- component add1b
- port (
- A: in std_logic;
- B: in std_logic;
- Cin: in std_logic;
- X: out std_logic;
- Cout: out std_logic);
- end component;
-begin
- -- full adder ladder (e.g. Cin -> Cin0, Cout0 -> Cin1, ..., Cout3 -> Cout)
- add0: component add1b
- port map (
- A => A(0),
- B => B(0),
- Cin => Cin,
- X => X(0),
- Cout => C0);
- add1: component add1b
- port map (
- A => A(1),
- B => B(1),
- Cin => C0,
- X => X(1),
- Cout => C1);
- add2: component add1b
- port map (
- A => A(2),
- B => B(2),
- Cin => C1,
- X => X(2),
- Cout => C2);
- add3: component add1b
- port map (
- A => A(3),
- B => B(3),
- Cin => C2,
- X => X(3),
- Cout => Cout);
-end Behavioral;
-
+../../../src/add4b.vhd \ No newline at end of file
diff --git a/full-adder/full-adder.srcs/sources_1/half_add.vhd b/full-adder/full-adder.srcs/sources_1/half_add.vhd
index d2d340a..32b41e7 100644..120000
--- a/full-adder/full-adder.srcs/sources_1/half_add.vhd
+++ b/full-adder/full-adder.srcs/sources_1/half_add.vhd
@@ -1,18 +1 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- half adder entity
-entity half_add is
- port (
- A: in std_logic;
- B: in std_logic;
- X: out std_logic;
- Cout: out std_logic);
-end half_add;
-
-architecture Behavioral of half_add is
-begin
- Cout <= (A AND B);
- X <= (A XOR B);
-end Behavioral;
+../../../src/half_add.vhd \ No newline at end of file
diff --git a/full-adder/full-adder.xpr b/full-adder/full-adder.xpr
index 7da21b3..11b20c0 100644
--- a/full-adder/full-adder.xpr
+++ b/full-adder/full-adder.xpr
@@ -43,6 +43,7 @@
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
+ <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@@ -130,7 +131,6 @@
</File>
<File Path="$PSRCDIR/sim_1/add1b_tb.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>