3 files changed, 3 insertions, 119 deletions
diff --git a/full-adder/full-adder.srcs/sources_1/add1b.vhd b/full-adder/full-adder.srcs/sources_1/add1b.vhd
index a2d4068..9ad3f1e 100644..120000
--- a/full-adder/full-adder.srcs/sources_1/add1b.vhd
+++ b/full-adder/full-adder.srcs/sources_1/add1b.vhd
@@ -1,43 +1 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- full adder entity
-entity add1b is
-  port (
-    A: in std_logic;
-    B: in std_logic;
-    Cin: in std_logic;
-    X: out std_logic;
-    Cout: out std_logic);
-end add1b;
-
-architecture Behavioral of add1b is
-  signal s0: std_logic;
-  signal s1: std_logic;
-  signal s2: std_logic;
-  component half_add
-	port (
-	  A: in std_logic;
-      B: in std_logic;
-      X: out std_logic;
-      Cout: out std_logic);
-  end component;
-begin
-	-- first add A and B with HA
-	add0: component half_add
-    port map (
-      A => A,
-      B => B,
-      X => s0,
-      Cout => s1);
-	-- then add first result with Cin to get final result
-  add1: component half_add
-    port map (
-      A => Cin,
-      B => s0,
-      X => X,
-      Cout => s2);
-	-- calculate Cout by OR-ing the Cout of both half adders
-  Cout <= (s2 OR s1);
-end Behavioral;
+../../../src/add1b.vhd
+\ No newline at end of file
diff --git a/full-adder/full-adder.srcs/sources_1/add4b.vhd b/full-adder/full-adder.srcs/sources_1/add4b.vhd
index 07e5a22..5245cd0 100644..120000
--- a/full-adder/full-adder.srcs/sources_1/add4b.vhd
+++ b/full-adder/full-adder.srcs/sources_1/add4b.vhd
@@ -1,58 +1 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- full 4-bit adder entity
-entity add4b is
-  port (
-    A: in std_logic_vector(3 downto 0);
-    B: in std_logic_vector(3 downto 0);
-    Cin: in std_logic;
-    X: out std_logic_vector(3 downto 0);
-    Cout: out std_logic);
-end add4b;
-
-architecture Behavioral of add4b is
-  signal C0: std_logic; -- Cout0 -> Cin1
-  signal C1: std_logic; -- Cout1 -> Cin2
-  signal C2: std_logic; -- Cout2 -> Cin3
-  component add1b 
-    port (
-      A: in std_logic;
-      B: in std_logic;
-      Cin: in std_logic;
-      X: out std_logic;
-      Cout: out std_logic);
-  end component;
-begin
-	-- full adder ladder (e.g. Cin -> Cin0, Cout0 -> Cin1, ..., Cout3 -> Cout)
-  add0: component add1b
-    port map (
-      A => A(0),
-      B => B(0),
-      Cin => Cin,
-      X => X(0),
-      Cout => C0);
-  add1: component add1b
-    port map (
-      A => A(1),
-      B => B(1),
-      Cin => C0,
-      X => X(1),
-      Cout => C1);
-  add2: component add1b
-    port map (
-      A => A(2),
-      B => B(2),
-      Cin => C1,
-      X => X(2),
-      Cout => C2);
-  add3: component add1b
-    port map (
-      A => A(3),
-      B => B(3),
-      Cin => C2,
-      X => X(3),
-      Cout => Cout);
-end Behavioral;
-
+../../../src/add4b.vhd
+\ No newline at end of file
diff --git a/full-adder/full-adder.srcs/sources_1/half_add.vhd b/full-adder/full-adder.srcs/sources_1/half_add.vhd
index d2d340a..32b41e7 100644..120000
--- a/full-adder/full-adder.srcs/sources_1/half_add.vhd
+++ b/full-adder/full-adder.srcs/sources_1/half_add.vhd
@@ -1,18 +1 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- half adder entity
-entity half_add is
-  port (
-    A: in std_logic;
-    B: in std_logic;
-    X: out std_logic;
-    Cout: out std_logic);
-end half_add;
-
-architecture Behavioral of half_add is
-begin
-  Cout <= (A AND B);
-  X <= (A XOR B);
-end Behavioral;
+../../../src/half_add.vhd
+\ No newline at end of file