diff options
Diffstat (limited to 'adder-and-display/adder-and-display.srcs/sources_1')
3 files changed, 80 insertions, 0 deletions
diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd new file mode 100644 index 0000000..7322509 --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd @@ -0,0 +1,22 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity bcddec is port( + A: in std_logic_vector(3 downto 0); + X: out std_logic_vector(6 downto 0)); +end bcddec; + +architecture Behavioral of bcddec is +begin + X <= "0111111" when A = "0000" else + "0000110" when A = "0001" else + "1011011" when A = "0010" else + "1001111" when A = "0011" else + "1100110" when A = "0100" else + "1101101" when A = "0101" else + "1111101" when A = "0110" else + "0100111" when A = "0111" else + "1111111" when A = "1000" else + "1101111" when A = "1001"; +end Behavioral; + diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd new file mode 100644 index 0000000..fa6fdea --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd @@ -0,0 +1,22 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bin2bcd is + port ( + A: in std_logic_vector(4 downto 0); + X: out std_logic_vector(3 downto 0); + Y: out std_logic_vector(3 downto 0)); +end bin2bcd; + +architecture Behavioral of bin2bcd is + signal X_tmp: unsigned(3 downto 0); + signal Y_tmp: unsigned(3 downto 0); +begin + X_tmp <= (unsigned(A(X_tmp'range)) / 10); + Y_tmp <= (unsigned(A(Y_tmp'range)) mod 10); + + X <= std_logic_vector(X_tmp); + Y <= std_logic_vector(Y_tmp); +end Behavioral; diff --git a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd new file mode 100644 index 0000000..448d0a7 --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd @@ -0,0 +1,36 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity main is + port ( + A: in std_logic_vector(3 downto 0); + B: in std_logic_vector(3 downto 0); + Cin: in std_logic; + D1: out std_logic_vector(6 downto 0); + D2: out std_logic_vector(6 downto 0); + Cout: out std_logic); +end main; + +architecture Behavioral of main is +signal RESULT: std_logic_vector(3 downto 0); +signal BCD1: std_logic_vector(3 downto 0); +signal BCD2: std_logic_vector(3 downto 0); +begin + add: entity work.add4b port map ( + A => A, + B => B, + Cin => Cin, + X => RESULT, + Cout => Cout); + bcdconv: entity work.bin2bcd port map ( + A => RESULT, + X => BCD1, + Y => BCD2); + bcddec1: entity work.bcddec port map ( + A => BCD1, + X => D1); + bcddec2: entity work.bcddec port map ( + A => BCD2, + X => D2); +end Behavioral; + |