1 files changed, 51 insertions, 26 deletions
diff --git a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd
index 448d0a7..af68d2b 100644
--- a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd
+++ b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd
@@ -2,35 +2,60 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
 entity main is
-  port (
-    A: in std_logic_vector(3 downto 0);
-    B: in std_logic_vector(3 downto 0);
-    Cin: in std_logic;
-    D1: out std_logic_vector(6 downto 0);
-    D2: out std_logic_vector(6 downto 0);
-    Cout: out std_logic);
+	port(
+		CLK: in std_logic; -- clk for display refresh
+		A: in std_logic_vector(3 downto 0); -- adder A input
+		B: in std_logic_vector(3 downto 0); -- adder B input
+		DD: out std_logic_vector(7 downto 0); -- display segment data
+		DS: out std_logic_vector(3 downto 0)); -- display select
 end main;
 
+bcd2disp  bcddec  dispdrv
 architecture Behavioral of main is
-signal RESULT: std_logic_vector(3 downto 0);
-signal BCD1: std_logic_vector(3 downto 0);
-signal BCD2: std_logic_vector(3 downto 0);
+  component add4b
+    port (
+      A: in std_logic_vector(3 downto 0);
+      B: in std_logic_vector(3 downto 0);
+      Cin: in std_logic;
+      X: out std_logic_vector(3 downto 0);
+      Cout: out std_logic);
+  end component;
+  component bin2bcd
+    port (
+      I: in std_logic_vector(3 downto 0);
+      X: out std_logic_vector(3 downto 0);
+      Y: out std_logic_vector(3 downto 0);
+  end component;
+  component bcd2disp
+    port (
+			CLK: in std_logic;
+			N0: in std_logic_vector(3 downto 0);
+			N1: in std_logic_vector(3 downto 0);
+			N2: in std_logic_vector(3 downto 0);
+			N3: in std_logic_vector(3 downto 0));
+  end component;
+  signal X: std_logic_vector(4 downto 0); -- add out
+  signal BCD0: std_logic_vector(4 downto 0); -- bcd 10^0
+  signal BCD1: std_logic_vector(4 downto 0); -- bcd 10^1
 begin
-	add: entity work.add4b port map (
-		A => A,
-		B => B,
-		Cin => Cin,
-		X => RESULT,
-		Cout => Cout);
-	bcdconv: entity work.bin2bcd port map (
-		A => RESULT,
-		X => BCD1,
-		Y => BCD2);
-	bcddec1: entity work.bcddec port map (
-		A => BCD1,
-		X => D1);
-	bcddec2: entity work.bcddec port map (
-		A => BCD2,
-		X => D2);
+  add: component add4b
+    port map (
+      A => A,
+      B => B,
+      Cin => 0,
+      X => X,
+      Cout => 0);
+  bcd: component bin2bcd
+    port map (
+      I => X,
+      X => BCD0,
+      Y => BCD1);
+  disp: component bcd2disp
+    port map (
+      CLK => CLK,
+      N0 => BCD0,
+      N1 => BCD1,
+      N2 => 0,
+      N3 => 0);
 end Behavioral;