diff options
5 files changed, 142 insertions, 59 deletions
diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bcd2disp.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bcd2disp.vhd new file mode 100644 index 0000000..dd0fa11 --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sources_1/bcd2disp.vhd @@ -0,0 +1,46 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity bcd2disp is port( + CLK: in std_logic; + N0: in std_logic_vector(3 downto 0); + N1: in std_logic_vector(3 downto 0); + N2: in std_logic_vector(3 downto 0); + N3: in std_logic_vector(3 downto 0)); + + DD: out std_logic_vector(7 downto 0); -- display segment data + DS: out std_logic_vector(3 downto 0)); -- display select +end bcd2disp; + +architecture Behavioral of bcd2disp is + component bcddec + port( + A: in std_logic_vector(3 downto 0); + X: out std_logic_vector(7 downto 0)); + end component; + signal D0: std_logic_vector(7 downto 0); -- display 0 segment bits + signal D1: std_logic_vector(7 downto 0); -- display 1 segment bits + signal D2: std_logic_vector(7 downto 0); -- display 2 segment bits + signal D3: std_logic_vector(7 downto 0); -- display 3 segment bits + + signal SX: std_logic_vector(1 downto 0); -- output display mux select + signal DX: std_logic_vector(7 downto 0); -- output display segment bits +begin + bcddec0: component bcddec + port map ( + A => N0, + X => D0); + bcddec1: component bcddec + port map ( + A => N1, + X => D1); + bcddec2: component bcddec + port map ( + A => N2, + X => D2); + bcddec3: component bcddec + port map ( + A => N3, + X => D3); +end Behavioral; + diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd index 7322509..cee9a97 100644 --- a/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd +++ b/adder-and-display/adder-and-display.srcs/sources_1/bcddec.vhd @@ -3,20 +3,20 @@ use IEEE.STD_LOGIC_1164.ALL; entity bcddec is port( A: in std_logic_vector(3 downto 0); - X: out std_logic_vector(6 downto 0)); + X: out std_logic_vector(7 downto 0)); end bcddec; architecture Behavioral of bcddec is begin - X <= "0111111" when A = "0000" else - "0000110" when A = "0001" else - "1011011" when A = "0010" else - "1001111" when A = "0011" else - "1100110" when A = "0100" else - "1101101" when A = "0101" else - "1111101" when A = "0110" else - "0100111" when A = "0111" else - "1111111" when A = "1000" else - "1101111" when A = "1001"; + X <= "00111111" when A = "0000" else + "00000110" when A = "0001" else + "01011011" when A = "0010" else + "01001111" when A = "0011" else + "01100110" when A = "0100" else + "01101101" when A = "0101" else + "01111101" when A = "0110" else + "00100111" when A = "0111" else + "01111111" when A = "1000" else + "01101111" when A = "1001"; end Behavioral; diff --git a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd b/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd deleted file mode 100644 index fa6fdea..0000000 --- a/adder-and-display/adder-and-display.srcs/sources_1/bin2bcd.vhd +++ /dev/null @@ -1,22 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity bin2bcd is - port ( - A: in std_logic_vector(4 downto 0); - X: out std_logic_vector(3 downto 0); - Y: out std_logic_vector(3 downto 0)); -end bin2bcd; - -architecture Behavioral of bin2bcd is - signal X_tmp: unsigned(3 downto 0); - signal Y_tmp: unsigned(3 downto 0); -begin - X_tmp <= (unsigned(A(X_tmp'range)) / 10); - Y_tmp <= (unsigned(A(Y_tmp'range)) mod 10); - - X <= std_logic_vector(X_tmp); - Y <= std_logic_vector(Y_tmp); -end Behavioral; diff --git a/adder-and-display/adder-and-display.srcs/sources_1/dispdrv.vhd b/adder-and-display/adder-and-display.srcs/sources_1/dispdrv.vhd new file mode 100644 index 0000000..96b2c97 --- /dev/null +++ b/adder-and-display/adder-and-display.srcs/sources_1/dispdrv.vhd @@ -0,0 +1,34 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity dispdrv is + port ( + CLK: in std_logic; + D0: in std_logic_vector(7 downto 0); + D1: in std_logic_vector(7 downto 0); + D2: in std_logic_vector(7 downto 0); + D3: in std_logic_vector(7 downto 0); + D: out std_logic_vector(7 downto 0); + S: out std_logic_vector(1 downto 0)); +end dispdrv; + +architecture Behavioral of dispdrv is +signal disp_idx: std_logic_vector(1 downto 0); +begin + process(CLK) + begin + if rising_edge(CLK) then + disp_idx <= (disp_idx + 1); + end if; + end process; + + S <= disp_idx; + with disp_idx select + D <= + D0 when "00", + D1 when "01", + D2 when "10", + D3 when "11", + (others => '0') when others; +end Behavioral; + diff --git a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd index 448d0a7..af68d2b 100644 --- a/adder-and-display/adder-and-display.srcs/sources_1/main.vhd +++ b/adder-and-display/adder-and-display.srcs/sources_1/main.vhd @@ -2,35 +2,60 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity main is - port ( - A: in std_logic_vector(3 downto 0); - B: in std_logic_vector(3 downto 0); - Cin: in std_logic; - D1: out std_logic_vector(6 downto 0); - D2: out std_logic_vector(6 downto 0); - Cout: out std_logic); + port( + CLK: in std_logic; -- clk for display refresh + A: in std_logic_vector(3 downto 0); -- adder A input + B: in std_logic_vector(3 downto 0); -- adder B input + DD: out std_logic_vector(7 downto 0); -- display segment data + DS: out std_logic_vector(3 downto 0)); -- display select end main; +bcd2disp bcddec dispdrv architecture Behavioral of main is -signal RESULT: std_logic_vector(3 downto 0); -signal BCD1: std_logic_vector(3 downto 0); -signal BCD2: std_logic_vector(3 downto 0); + component add4b + port ( + A: in std_logic_vector(3 downto 0); + B: in std_logic_vector(3 downto 0); + Cin: in std_logic; + X: out std_logic_vector(3 downto 0); + Cout: out std_logic); + end component; + component bin2bcd + port ( + I: in std_logic_vector(3 downto 0); + X: out std_logic_vector(3 downto 0); + Y: out std_logic_vector(3 downto 0); + end component; + component bcd2disp + port ( + CLK: in std_logic; + N0: in std_logic_vector(3 downto 0); + N1: in std_logic_vector(3 downto 0); + N2: in std_logic_vector(3 downto 0); + N3: in std_logic_vector(3 downto 0)); + end component; + signal X: std_logic_vector(4 downto 0); -- add out + signal BCD0: std_logic_vector(4 downto 0); -- bcd 10^0 + signal BCD1: std_logic_vector(4 downto 0); -- bcd 10^1 begin - add: entity work.add4b port map ( - A => A, - B => B, - Cin => Cin, - X => RESULT, - Cout => Cout); - bcdconv: entity work.bin2bcd port map ( - A => RESULT, - X => BCD1, - Y => BCD2); - bcddec1: entity work.bcddec port map ( - A => BCD1, - X => D1); - bcddec2: entity work.bcddec port map ( - A => BCD2, - X => D2); + add: component add4b + port map ( + A => A, + B => B, + Cin => 0, + X => X, + Cout => 0); + bcd: component bin2bcd + port map ( + I => X, + X => BCD0, + Y => BCD1); + disp: component bcd2disp + port map ( + CLK => CLK, + N0 => BCD0, + N1 => BCD1, + N2 => 0, + N3 => 0); end Behavioral; |