diff options
| -rw-r--r-- | full-adder/full-adder.srcs/sim_1/add1b_tb.vhd | 72 | ||||
| -rw-r--r-- | full-adder/full-adder.srcs/sources_1/add1b.vhd | 43 | ||||
| -rw-r--r-- | full-adder/full-adder.srcs/sources_1/add4b.vhd | 67 | ||||
| -rw-r--r-- | full-adder/full-adder.srcs/sources_1/half_add.vhd | 18 | ||||
| -rw-r--r-- | full-adder/full-adder.xpr | 40 |
5 files changed, 156 insertions, 84 deletions
diff --git a/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd b/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd new file mode 100644 index 0000000..18f05eb --- /dev/null +++ b/full-adder/full-adder.srcs/sim_1/add1b_tb.vhd @@ -0,0 +1,72 @@ +library ieee; +library unisim; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use unisim.vcomponents.all; + +entity add1b_tb is +end add1b_tb; + +architecture behavioral of add1b_tb is +component add1b +port ( + A: in std_logic; + B: in std_logic; + Cin: in std_logic; + X: out std_logic; + Cout: out std_logic); +end component; + +signal A: std_logic; +signal B: std_logic; +signal Cin: std_logic; +signal X: std_logic; +signal Cout: std_logic; +signal test_case: std_logic_vector(2 downto 0); +signal ok: boolean := true; + +begin + test_port: add1b port map( + A => A, + B => B, + X => X, + Cout => Cout, + Cin => Cin); + + tb: process + variable A_t: std_logic; + variable B_t: std_logic; + variable Cin_t: std_logic; + variable X_t: std_logic; + variable Cout_t: std_logic; + variable Out_t: std_logic_vector(1 downto 0); + + begin + for i in 0 to 7 loop + test_case <= std_logic_vector(to_unsigned(i,3)); + wait for 1 ps; + + A <= test_case(0); + B <= test_case(1); + Cin <= test_case(2); + + A_t := test_case(0); + B_t := test_case(1); + Cin_t := test_case(2); + + X_t := A_t xor B_t xor Cin_t; + Cout_t := (A_t and B_t) or (B_t and Cin_t) or (Cin_t and A_t); + + wait for 5 ns; + If X /= X_t then + OK <= false; + end if; + if Cout /= Cout_t then + OK <= false; + end if; + wait for 5 ns; + end loop; + wait; -- stop for simulator + end process; +end; diff --git a/full-adder/full-adder.srcs/sources_1/add1b.vhd b/full-adder/full-adder.srcs/sources_1/add1b.vhd new file mode 100644 index 0000000..a2d4068 --- /dev/null +++ b/full-adder/full-adder.srcs/sources_1/add1b.vhd @@ -0,0 +1,43 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +-- full adder entity +entity add1b is + port ( + A: in std_logic; + B: in std_logic; + Cin: in std_logic; + X: out std_logic; + Cout: out std_logic); +end add1b; + +architecture Behavioral of add1b is + signal s0: std_logic; + signal s1: std_logic; + signal s2: std_logic; + component half_add + port ( + A: in std_logic; + B: in std_logic; + X: out std_logic; + Cout: out std_logic); + end component; +begin + -- first add A and B with HA + add0: component half_add + port map ( + A => A, + B => B, + X => s0, + Cout => s1); + -- then add first result with Cin to get final result + add1: component half_add + port map ( + A => Cin, + B => s0, + X => X, + Cout => s2); + -- calculate Cout by OR-ing the Cout of both half adders + Cout <= (s2 OR s1); +end Behavioral; diff --git a/full-adder/full-adder.srcs/sources_1/add4b.vhd b/full-adder/full-adder.srcs/sources_1/add4b.vhd index 184d360..07e5a22 100644 --- a/full-adder/full-adder.srcs/sources_1/add4b.vhd +++ b/full-adder/full-adder.srcs/sources_1/add4b.vhd @@ -2,73 +2,6 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; --- half adder entity -entity half_add is - port ( - A: in std_logic; - B: in std_logic; - X: out std_logic; - Cout: out std_logic); -end half_add; - -architecture Behavioral of half_add is -begin - Cout <= (A AND B); - X <= (A XOR B); -end Behavioral; - - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - --- full adder entity -entity add1b is - port ( - A: in std_logic; - B: in std_logic; - Cin: in std_logic; - X: out std_logic; - Cout: out std_logic); -end add1b; - -architecture Behavioral of add1b is - signal s0: std_logic; - signal s1: std_logic; - signal s2: std_logic; - component half_add - port ( - A: in std_logic; - B: in std_logic; - X: out std_logic; - Cout: out std_logic); - end component; -begin - -- first add A and B with HA - add0: component half_add - port map ( - A => A, - B => B, - X => s0, - Cout => s1); - -- then add first result with Cin to get final result - add1: component half_add - port map ( - A => Cin, - B => s0, - X => X, - Cout => s2); - -- calculate Cout by OR-ing the Cout of both half adders - Cout <= (s2 OR s1); -end Behavioral; - - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -- full 4-bit adder entity entity add4b is port ( diff --git a/full-adder/full-adder.srcs/sources_1/half_add.vhd b/full-adder/full-adder.srcs/sources_1/half_add.vhd new file mode 100644 index 0000000..d2d340a --- /dev/null +++ b/full-adder/full-adder.srcs/sources_1/half_add.vhd @@ -0,0 +1,18 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +-- half adder entity +entity half_add is + port ( + A: in std_logic; + B: in std_logic; + X: out std_logic; + Cout: out std_logic); +end half_add; + +architecture Behavioral of half_add is +begin + Cout <= (A AND B); + X <= (A XOR B); +end Behavioral; diff --git a/full-adder/full-adder.xpr b/full-adder/full-adder.xpr index 853afea..7da21b3 100644 --- a/full-adder/full-adder.xpr +++ b/full-adder/full-adder.xpr @@ -58,7 +58,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> - <Option Name="WTXSimLaunchSim" Val="4"/> + <Option Name="WTXSimLaunchSim" Val="11"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/> @@ -89,6 +89,18 @@ <FileSets Version="1" Minor="31"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/add1b.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/half_add.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <File Path="$PSRCDIR/sources_1/add4b.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> @@ -116,11 +128,17 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> + <File Path="$PSRCDIR/sim_1/add1b_tb.vhd"> + <FileInfo> + <Attr Name="AutoDisabled" Val="1"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="add4b_tb"/> <Option Name="TopLib" Val="xil_defaultlib"/> - <Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/> <Option Name="SelectedSimModel" Val="rtl"/> @@ -133,14 +151,6 @@ </FileSet> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> <Filter Type="Utils"/> - <File Path="$PSRCDIR/utils_1/imports/synth_1/add4b_tb.dcp"> - <FileInfo> - <Attr Name="UsedIn" Val="synthesis"/> - <Attr Name="UsedIn" Val="implementation"/> - <Attr Name="UsedInSteps" Val="synth_1"/> - <Attr Name="AutoDcp" Val="1"/> - </FileInfo> - </File> <Config> <Option Name="TopAutoSet" Val="TRUE"/> </Config> @@ -168,11 +178,9 @@ </Simulator> </Simulators> <Runs Version="1" Minor="19"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/add4b_tb.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> </Strategy> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> @@ -182,9 +190,7 @@ </Run> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> |