diff options
| -rw-r--r-- | src/main-stopwatch.vhd | 26 | ||||
| -rw-r--r-- | src/stopwatch.vhd | 41 | ||||
| -rw-r--r-- | stopwatch/stopwatch.srcs/constrs_1/main.xdc | 2 | ||||
| -rw-r--r-- | stopwatch/stopwatch.xpr | 14 |
4 files changed, 67 insertions, 16 deletions
diff --git a/src/main-stopwatch.vhd b/src/main-stopwatch.vhd index f8d0ac0..ac5ff2d 100644 --- a/src/main-stopwatch.vhd +++ b/src/main-stopwatch.vhd @@ -53,19 +53,19 @@ begin end if; end process; - controller: component FSM_controller - port map( - clk => clk, - sysReset => sysReset, - buttons => buttons, - watchRunning => watchRunning, - watchReset => watchReset); + -- controller: component FSM_controller + -- port map( + -- clk => clk, + -- sysReset => sysReset, + -- buttons => buttons, + -- watchRunning => watchRunning, + -- watchReset => watchReset); stopwatch: component Watch port map( clk => clk, sysReset => sysReset, - watchRunning => watchRunning, - watchReset => watchReset, + watchRunning => buttons(0), + watchReset => buttons(1), mins => mins, secs => secs); bcd0: component bin2bcd @@ -91,10 +91,10 @@ begin disp: component bcd2disp port map( CLK => CLK_T(16), - N0 => N0, - N1 => N1, - N2 => N2, - N3 => N3, + N0 => N3, + N1 => N2, + N2 => N1, + N3 => N0, DD => DD, DS => DS); end Behavioral; diff --git a/src/stopwatch.vhd b/src/stopwatch.vhd index cfbd7ff..01300fc 100644 --- a/src/stopwatch.vhd +++ b/src/stopwatch.vhd @@ -1,5 +1,7 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; entity Watch is port( @@ -9,4 +11,43 @@ end Watch; architecture Behavioral of Watch is begin + process(clk, sysReset) + variable subsec: std_logic_vector(26 downto 0) := (others => '0'); -- floor(log2(100_000_000)) + -- = 26 (bits needed to count to 1 second for 100Mhz clock) + variable minute, second: std_logic_vector(5 downto 0) := (others => '0'); + begin + if sysReset = '1' then + subsec := (others => '0'); + second := (others => '0'); + minute := (others => '0'); + elsif rising_edge(clk) then + if watchRunning = '1' then + subsec := (subsec + 1); + + -- if subsec is 100_000_000 (second complete) + if subsec = "101111101011110000100000000" then + subsec := (others => '0'); + second := (second + 1); + + -- if second is 60 (minute complete) + if second = "111100" then + second := (others => '0'); + minute := (minute + 1); + + -- if minute is 60 (hour complete) + if minute = "111100" then + minute := (others => '0'); + end if; + end if; + end if; + elsif watchReset = '1' then + subsec := (others => '0'); + second := (others => '0'); + minute := (others => '0'); + end if; + end if; + + mins <= minute; + secs <= second; + end process; end Behavioral; diff --git a/stopwatch/stopwatch.srcs/constrs_1/main.xdc b/stopwatch/stopwatch.srcs/constrs_1/main.xdc index a729a03..99e3dcc 100644 --- a/stopwatch/stopwatch.srcs/constrs_1/main.xdc +++ b/stopwatch/stopwatch.srcs/constrs_1/main.xdc @@ -18,7 +18,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {DS[3]}] set_property PACKAGE_PIN T17 [get_ports {buttons[0]}] set_property PACKAGE_PIN W19 [get_ports {buttons[1]}] set_property PACKAGE_PIN W5 [get_ports clk] -set_property PACKAGE_PIN U17 [get_ports {sysReset}] +set_property PACKAGE_PIN T18 [get_ports {sysReset}] set_property PACKAGE_PIN V7 [get_ports {DD[7]}] set_property PACKAGE_PIN U7 [get_ports {DD[6]}] set_property PACKAGE_PIN V5 [get_ports {DD[5]}] diff --git a/stopwatch/stopwatch.xpr b/stopwatch/stopwatch.xpr index f844288..f166a0d 100644 --- a/stopwatch/stopwatch.xpr +++ b/stopwatch/stopwatch.xpr @@ -169,6 +169,14 @@ </FileSet> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> <Filter Type="Utils"/> + <File Path="$PSRCDIR/utils_1/imports/synth_1/main.dcp"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedInSteps" Val="synth_1"/> + <Attr Name="AutoDcp" Val="1"/> + </FileInfo> + </File> <Config> <Option Name="TopAutoSet" Val="TRUE"/> </Config> @@ -196,16 +204,17 @@ </Simulator> </Simulators> <Runs Version="1" Minor="19"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -218,6 +227,7 @@ <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> |