diff options
-rw-r--r-- | constraints-deel2/constraints-deel2.xpr | 75 | ||||
-rw-r--r-- | constraints/constraints.xpr | 32 | ||||
-rw-r--r-- | keyboard/keyboard.xpr | 46 | ||||
l--------- | sound/sound.srcs/sources_1/audio.coe | 1 | ||||
-rw-r--r-- | sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci | 16 | ||||
-rw-r--r-- | sound/sound.xpr | 59 | ||||
-rw-r--r-- | src/note-synth.vhd | 2 |
7 files changed, 107 insertions, 124 deletions
diff --git a/constraints-deel2/constraints-deel2.xpr b/constraints-deel2/constraints-deel2.xpr index 4c8b342..6a2d165 100644 --- a/constraints-deel2/constraints-deel2.xpr +++ b/constraints-deel2/constraints-deel2.xpr @@ -1,9 +1,10 @@ <?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2022.2 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Product Version: Vivado v2023.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --> -<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/constraints-deel2/constraints-deel2.xpr"> +<Project Product="Vivado" Version="7" Minor="65" Path="/home/loek/docs/repos/progh-huiswerk/constraints-deel2/constraints-deel2.xpr"> <DefaultLaunch Dir="$PRUNDIR"/> <Configuration> <Option Name="Id" Val="a5b3700692c54208a72337240cb41b13"/> @@ -28,14 +29,14 @@ <Option Name="SimulatorGccInstallDirVCS" Val=""/> <Option Name="SimulatorGccInstallDirRiviera" Val=""/> <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> - <Option Name="SimulatorVersionXsim" Val="2022.2"/> - <Option Name="SimulatorVersionModelSim" Val="2022.2"/> - <Option Name="SimulatorVersionQuesta" Val="2022.2"/> - <Option Name="SimulatorVersionXcelium" Val="21.09.009"/> - <Option Name="SimulatorVersionVCS" Val="S-2021.09"/> - <Option Name="SimulatorVersionRiviera" Val="2022.04"/> + <Option Name="SimulatorVersionXsim" Val="2023.2"/> + <Option Name="SimulatorVersionModelSim" Val="2023.2"/> + <Option Name="SimulatorVersionQuesta" Val="2023.2"/> + <Option Name="SimulatorVersionXcelium" Val="23.03.002"/> + <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/> + <Option Name="SimulatorVersionRiviera" Val="2022.10"/> <Option Name="SimulatorVersionActiveHdl" Val="13.0"/> - <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> @@ -43,8 +44,7 @@ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> <Option Name="TargetLanguage" Val="VHDL"/> - <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> - <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/> + <Option Name="BoardPart" Val=""/> <Option Name="ActiveSimSet" Val="sim_1"/> <Option Name="DefaultLib" Val="xil_defaultlib"/> <Option Name="ProjectType" Val="Default"/> @@ -60,6 +60,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> + <Option Name="FeatureSet" Val="FeatureSet_Classic"/> <Option Name="WTXSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> @@ -88,40 +89,40 @@ <Option Name="ClassicSocBoot" Val="FALSE"/> <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> </Configuration> - <FileSets Version="1" Minor="31"> + <FileSets Version="1" Minor="32"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <Filter Type="Srcs"/> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/ff.vhdl"> + <File Path="$PPRDIR/../copyright/prog2/ff.vhdl"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/fulladder1bit.vhdl"> + <File Path="$PPRDIR/../copyright/prog2/fulladder1bit.vhdl"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/fulladder2bit.vhd"> + <File Path="$PPRDIR/../copyright/prog2/fulladder2bit.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/gen_ff.vhdl"> + <File Path="$PPRDIR/../copyright/prog2/gen_ff.vhdl"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/gen_sync_ff.vhdl"> + <File Path="$PPRDIR/../copyright/prog2/gen_sync_ff.vhdl"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/hdl/adder16bit2bitfa.vhd"> + <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa.vhd"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> @@ -131,29 +132,29 @@ <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="adder16bit2bitfa"/> <Option Name="TopAutoSet" Val="TRUE"/> - <Option Name="dataflowViewerSettings" Val="min_width=16"/> </Config> </FileSet> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> <Filter Type="Constrs"/> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/constraints/adder16bit2bitfa.xdc"> + <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa.xdc"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="implementation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/constraints/io.xdc"> + <File Path="$PPRDIR/../copyright/prog2/io.xdc"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="implementation"/> </FileInfo> </File> <Config> - <Option Name="TargetConstrsFile" Val="$PPRDIR/../copyright/prog2/adder16bit2bitfa..src/constraints/adder16bit2bitfa.xdc"/> + <Option Name="TargetConstrsFile" Val="$PPRDIR/../copyright/prog2/adder16bit2bitfa.xdc"/> <Option Name="ConstrsType" Val="XDC"/> </Config> </FileSet> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Filter Type="Srcs"/> <Config> <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="adder16bit2bitfa"/> @@ -171,14 +172,6 @@ </FileSet> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> <Filter Type="Utils"/> - <File Path="$PSRCDIR/utils_1/imports/synth_1/adder16bit2bitfa.dcp"> - <FileInfo> - <Attr Name="UsedIn" Val="synthesis"/> - <Attr Name="UsedIn" Val="implementation"/> - <Attr Name="UsedInSteps" Val="synth_1"/> - <Attr Name="AutoDcp" Val="1"/> - </FileInfo> - </File> <Config> <Option Name="TopAutoSet" Val="TRUE"/> </Config> @@ -205,12 +198,10 @@ <Option Name="Description" Val="Riviera-PRO Simulator"/> </Simulator> </Simulators> - <Runs Version="1" Minor="19"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/adder16bit2bitfa.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> + <Runs Version="1" Minor="21"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"> <Option Id="FlattenHierarchy">0</Option> </Step> @@ -220,11 +211,9 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 1 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> @@ -241,9 +230,7 @@ <RQSFiles/> </Run> </Runs> - <Board> - <Jumpers/> - </Board> + <Board/> <DashboardSummary Version="1" Minor="0"> <Dashboards> <Dashboard Name="default_dashboard"> diff --git a/constraints/constraints.xpr b/constraints/constraints.xpr index cdf79ff..7ecc182 100644 --- a/constraints/constraints.xpr +++ b/constraints/constraints.xpr @@ -1,9 +1,10 @@ <?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2022.2 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Product Version: Vivado v2023.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --> -<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/constraints/constraints.xpr"> +<Project Product="Vivado" Version="7" Minor="65" Path="/home/loek/docs/repos/progh-huiswerk/constraints/constraints.xpr"> <DefaultLaunch Dir="$PRUNDIR"/> <Configuration> <Option Name="Id" Val="b1670db726f8431ab206287bfc0019a9"/> @@ -28,14 +29,14 @@ <Option Name="SimulatorGccInstallDirVCS" Val=""/> <Option Name="SimulatorGccInstallDirRiviera" Val=""/> <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> - <Option Name="SimulatorVersionXsim" Val="2022.2"/> - <Option Name="SimulatorVersionModelSim" Val="2022.2"/> - <Option Name="SimulatorVersionQuesta" Val="2022.2"/> - <Option Name="SimulatorVersionXcelium" Val="21.09.009"/> - <Option Name="SimulatorVersionVCS" Val="S-2021.09"/> - <Option Name="SimulatorVersionRiviera" Val="2022.04"/> + <Option Name="SimulatorVersionXsim" Val="2023.2"/> + <Option Name="SimulatorVersionModelSim" Val="2023.2"/> + <Option Name="SimulatorVersionQuesta" Val="2023.2"/> + <Option Name="SimulatorVersionXcelium" Val="23.03.002"/> + <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/> + <Option Name="SimulatorVersionRiviera" Val="2022.10"/> <Option Name="SimulatorVersionActiveHdl" Val="13.0"/> - <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> @@ -44,7 +45,6 @@ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> <Option Name="TargetLanguage" Val="VHDL"/> <Option Name="BoardPart" Val=""/> - <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/> <Option Name="SourceMgmtMode" Val="None"/> <Option Name="ActiveSimSet" Val="sim_1"/> <Option Name="DefaultLib" Val="xil_defaultlib"/> @@ -61,6 +61,7 @@ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="FeatureSet" Val="FeatureSet_Classic"/> <Option Name="WTXSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> @@ -89,7 +90,7 @@ <Option Name="ClassicSocBoot" Val="FALSE"/> <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> </Configuration> - <FileSets Version="1" Minor="31"> + <FileSets Version="1" Minor="32"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <Filter Type="Srcs"/> <File Path="$PSRCDIR/sources_1/imports/Sources/top.edif"> @@ -198,8 +199,8 @@ <Option Name="Description" Val="Riviera-PRO Simulator"/> </Simulator> </Simulators> - <Runs Version="1" Minor="19"> - <Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc7k70tfbg676-2" ConstrsSet="lab1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Runs Version="1" Minor="21"> + <Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc7k70tfbg676-2" ConstrsSet="lab1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 1 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -212,6 +213,7 @@ <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> diff --git a/keyboard/keyboard.xpr b/keyboard/keyboard.xpr index baaab08..adf88d2 100644 --- a/keyboard/keyboard.xpr +++ b/keyboard/keyboard.xpr @@ -1,9 +1,10 @@ <?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2022.2 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Product Version: Vivado v2023.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --> -<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/keyboard/keyboard.xpr"> +<Project Product="Vivado" Version="7" Minor="65" Path="/home/loek/docs/repos/progh-huiswerk/keyboard/keyboard.xpr"> <DefaultLaunch Dir="$PRUNDIR"/> <Configuration> <Option Name="Id" Val="3e3f6c54fcfe4f7f856c3f021895ffaf"/> @@ -28,22 +29,21 @@ <Option Name="SimulatorGccInstallDirVCS" Val=""/> <Option Name="SimulatorGccInstallDirRiviera" Val=""/> <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> - <Option Name="SimulatorVersionXsim" Val="2022.2"/> - <Option Name="SimulatorVersionModelSim" Val="2022.2"/> - <Option Name="SimulatorVersionQuesta" Val="2022.2"/> - <Option Name="SimulatorVersionXcelium" Val="21.09.009"/> - <Option Name="SimulatorVersionVCS" Val="S-2021.09"/> - <Option Name="SimulatorVersionRiviera" Val="2022.04"/> + <Option Name="SimulatorVersionXsim" Val="2023.2"/> + <Option Name="SimulatorVersionModelSim" Val="2023.2"/> + <Option Name="SimulatorVersionQuesta" Val="2023.2"/> + <Option Name="SimulatorVersionXcelium" Val="23.03.002"/> + <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/> + <Option Name="SimulatorVersionRiviera" Val="2022.10"/> <Option Name="SimulatorVersionActiveHdl" Val="13.0"/> - <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> - <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> - <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/> + <Option Name="BoardPart" Val=""/> <Option Name="ActiveSimSet" Val="sim_1"/> <Option Name="DefaultLib" Val="xil_defaultlib"/> <Option Name="ProjectType" Val="Default"/> @@ -59,6 +59,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> + <Option Name="FeatureSet" Val="FeatureSet_Classic"/> <Option Name="WTXSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> @@ -87,7 +88,7 @@ <Option Name="ClassicSocBoot" Val="FALSE"/> <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> </Configuration> - <FileSets Version="1" Minor="31"> + <FileSets Version="1" Minor="32"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <Filter Type="Srcs"/> <File Path="$PSRCDIR/bcd2disp.vhd"> @@ -142,7 +143,6 @@ <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="main"/> <Option Name="TopAutoSet" Val="TRUE"/> - <Option Name="dataflowViewerSettings" Val="min_width=16"/> </Config> </FileSet> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> @@ -211,12 +211,10 @@ <Option Name="Description" Val="Riviera-PRO Simulator"/> </Simulator> </Simulators> - <Runs Version="1" Minor="19"> + <Runs Version="1" Minor="21"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> <Step Id="synth_design"/> </Strategy> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> @@ -224,11 +222,9 @@ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 1 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> <Step Id="opt_design"/> <Step Id="power_opt_design"/> @@ -245,9 +241,7 @@ <RQSFiles/> </Run> </Runs> - <Board> - <Jumpers/> - </Board> + <Board/> <DashboardSummary Version="1" Minor="0"> <Dashboards> <Dashboard Name="default_dashboard"> diff --git a/sound/sound.srcs/sources_1/audio.coe b/sound/sound.srcs/sources_1/audio.coe new file mode 120000 index 0000000..f1857a0 --- /dev/null +++ b/sound/sound.srcs/sources_1/audio.coe @@ -0,0 +1 @@ +../../../copyright/rick.coe
\ No newline at end of file diff --git a/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci b/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci index 04a828f..095eaf6 100644 --- a/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci +++ b/sound/sound.srcs/sources_1/ip/BertErnie44Audio/BertErnie44Audio.xci @@ -3,7 +3,7 @@ "ip_inst": { "xci_name": "BertErnie44Audio", "component_reference": "xilinx.com:ip:blk_mem_gen:8.4", - "ip_revision": "5", + "ip_revision": "7", "gen_directory": "../../../../sound.gen/sources_1/ip/BertErnie44Audio", "parameters": { "component_parameters": { @@ -34,11 +34,11 @@ "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Write_Width_A": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "Write_Depth_A": [ { "value": "200000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Read_Width_A": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Read_Width_A": [ { "value": "8", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "Write_Width_B": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Read_Width_B": [ { "value": "8", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Write_Width_B": [ { "value": "8", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Read_Width_B": [ { "value": "8", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -51,7 +51,7 @@ "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Coe_File": [ { "value": "../../../../../copyright/rick.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Coe_File": [ { "value": "../../audio.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -65,7 +65,7 @@ "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Port_A_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Port_A_Write_Rate": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -174,12 +174,12 @@ }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], - "IPREVISION": [ { "value": "5" } ], + "IPREVISION": [ { "value": "7" } ], "MANAGED": [ { "value": "TRUE" } ], "OUTPUTDIR": [ { "value": "../../../../sound.gen/sources_1/ip/BertErnie44Audio" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], - "SWVERSION": [ { "value": "2022.2" } ], + "SWVERSION": [ { "value": "2023.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } }, diff --git a/sound/sound.xpr b/sound/sound.xpr index 94fb553..ac437ac 100644 --- a/sound/sound.xpr +++ b/sound/sound.xpr @@ -1,9 +1,10 @@ <?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2022.2 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Product Version: Vivado v2023.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --> -<Project Version="7" Minor="61" Path="/home/loek/docs/repos/progh-huiswerk/sound/sound.xpr"> +<Project Product="Vivado" Version="7" Minor="65" Path="/home/loek/docs/repos/progh-huiswerk/sound/sound.xpr"> <DefaultLaunch Dir="$PRUNDIR"/> <Configuration> <Option Name="Id" Val="660c6843b7274ff5a0e3f2f1e38067d9"/> @@ -28,22 +29,21 @@ <Option Name="SimulatorGccInstallDirVCS" Val=""/> <Option Name="SimulatorGccInstallDirRiviera" Val=""/> <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> - <Option Name="SimulatorVersionXsim" Val="2022.2"/> - <Option Name="SimulatorVersionModelSim" Val="2022.2"/> - <Option Name="SimulatorVersionQuesta" Val="2022.2"/> - <Option Name="SimulatorVersionXcelium" Val="21.09.009"/> - <Option Name="SimulatorVersionVCS" Val="S-2021.09"/> - <Option Name="SimulatorVersionRiviera" Val="2022.04"/> + <Option Name="SimulatorVersionXsim" Val="2023.2"/> + <Option Name="SimulatorVersionModelSim" Val="2023.2"/> + <Option Name="SimulatorVersionQuesta" Val="2023.2"/> + <Option Name="SimulatorVersionXcelium" Val="23.03.002"/> + <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/> + <Option Name="SimulatorVersionRiviera" Val="2022.10"/> <Option Name="SimulatorVersionActiveHdl" Val="13.0"/> - <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> - <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> - <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2022.2/xhub/board_store/xilinx_board_store"/> + <Option Name="BoardPart" Val=""/> <Option Name="ActiveSimSet" Val="sim_1"/> <Option Name="DefaultLib" Val="xil_defaultlib"/> <Option Name="ProjectType" Val="Default"/> @@ -59,6 +59,7 @@ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> <Option Name="DSABoardId" Val="basys3"/> + <Option Name="FeatureSet" Val="FeatureSet_Classic"/> <Option Name="WTXSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> @@ -66,13 +67,13 @@ <Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/> - <Option Name="WTXSimExportSim" Val="3"/> - <Option Name="WTModelSimExportSim" Val="3"/> - <Option Name="WTQuestaExportSim" Val="3"/> + <Option Name="WTXSimExportSim" Val="5"/> + <Option Name="WTModelSimExportSim" Val="5"/> + <Option Name="WTQuestaExportSim" Val="5"/> <Option Name="WTIesExportSim" Val="0"/> - <Option Name="WTVcsExportSim" Val="3"/> - <Option Name="WTRivieraExportSim" Val="3"/> - <Option Name="WTActivehdlExportSim" Val="3"/> + <Option Name="WTVcsExportSim" Val="5"/> + <Option Name="WTRivieraExportSim" Val="5"/> + <Option Name="WTActivehdlExportSim" Val="5"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="XSimRadix" Val="hex"/> <Option Name="XSimTimeUnit" Val="ns"/> @@ -87,7 +88,7 @@ <Option Name="ClassicSocBoot" Val="FALSE"/> <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> </Configuration> - <FileSets Version="1" Minor="31"> + <FileSets Version="1" Minor="32"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> <Filter Type="Srcs"/> <File Path="$PSRCDIR/AudioOut.vhd"> @@ -108,7 +109,7 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> - <File Path="$PPRDIR/../copyright/rick.coe"> + <File Path="$PSRCDIR/sources_1/audio.coe"> <FileInfo> <Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="simulation"/> @@ -199,7 +200,7 @@ <Option Name="Description" Val="Riviera-PRO Simulator"/> </Simulator> </Simulators> - <Runs Version="1" Minor="19"> + <Runs Version="1" Minor="21"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/PlayAudio.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/> @@ -212,17 +213,17 @@ </Run> <Run Id="BertErnie44Audio_synth_1" Type="Ft3:Synth" SrcSet="BertErnie44Audio" Part="xc7a35tcpg236-1" ConstrsSet="BertErnie44Audio" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/BertErnie44Audio_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/BertErnie44Audio_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/BertErnie44Audio_synth_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"> <Desc>Vivado Synthesis Defaults</Desc> </StratHandle> <Step Id="synth_design"/> </Strategy> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> - <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 1 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1"> <Strategy Version="1" Minor="2"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/> <Step Id="init_design"/> @@ -242,7 +243,7 @@ </Run> <Run Id="BertErnie44Audio_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="BertErnie44Audio" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="BertErnie44Audio_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/BertErnie44Audio_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/BertErnie44Audio_impl_1"> <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"> <Desc>Default settings for Implementation.</Desc> </StratHandle> <Step Id="init_design"/> @@ -255,14 +256,12 @@ <Step Id="post_route_phys_opt_design"/> <Step Id="write_bitstream"/> </Strategy> - <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <RQSFiles/> </Run> </Runs> - <Board> - <Jumpers/> - </Board> + <Board/> <DashboardSummary Version="1" Minor="0"> <Dashboards> <Dashboard Name="default_dashboard"> diff --git a/src/note-synth.vhd b/src/note-synth.vhd index 3d37022..72a1cd1 100644 --- a/src/note-synth.vhd +++ b/src/note-synth.vhd @@ -45,7 +45,7 @@ begin CLK_FOR_F5; PWM_OUT <= PWM_OUT_TEMP and NOTE_PLAY; - process(CLK) + process(CLK, RESET) variable CLK_COUNTER : integer := 0; begin if RESET = '1' then |