3 files changed, 18 insertions, 9 deletions

diff --git a/src/bounce.vhd b/src/bounce.vhd
index de1e0e1..2a5c187 100644
--- a/src/bounce.vhd
+++ b/src/bounce.vhd
@@ -5,6 +5,7 @@ use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 
 entity bounce is
+	-- bounce motion
 	port (
 		clk, reset: in std_logic;
 		x, y: out std_logic_vector(9 downto 0));
@@ -16,35 +17,37 @@ architecture Behavioral of bounce is
 	signal direction: std_logic_vector(1 downto 0) := "00";
 	constant velocity: natural := 1;
 
+	-- current square position
 	signal temp_x, temp_y: std_logic_vector(9 downto 0) := (others => '0');
 begin
-    x <= temp_x;
-    y <= temp_y;
+	x <= temp_x;
+	y <= temp_y;
 	process(clk, reset)
 	begin
 		if reset = '1' then
-			direction <= "00";
+			-- async reset
+			direction <= "00"; -- reset direction to bottom right
 			temp_x <= (others => '0');
 			temp_y <= (others => '0');
 		elsif rising_edge(clk) then
 			if direction(0) = '0' then
-				temp_x <= temp_x + velocity;
+				temp_x <= temp_x + velocity; -- move left
 				if (temp_x + velocity) > 630 then
 					direction(0) <= '1';
 				end if;
 			else
-				temp_x <= temp_x - velocity;
+				temp_x <= temp_x - velocity; -- move right
 				if (temp_x - velocity) <= 0 then
 					direction(0) <= '0';
 				end if;
 			end if;
 			if direction(1) = '0' then
-				temp_y <= temp_y + 1;
+				temp_y <= temp_y + 1; -- move down
 				if (temp_y + velocity) > 470 then
 					direction(1) <= '1';
 				end if;
 			else
-				temp_y <= temp_y - 1;
+				temp_y <= temp_y - 1; -- move up
 				if (temp_y - velocity) <= 0 then
 					direction(1) <= '0';
 				end if;
diff --git a/src/main-bouncing-square.vhd b/src/main-bouncing-square.vhd
index 51f4cce..d3e93e2 100644
--- a/src/main-bouncing-square.vhd
+++ b/src/main-bouncing-square.vhd
@@ -31,6 +31,7 @@ architecture Behavioral of main is
 	signal x, y: std_logic_vector(9 downto 0); -- current pixel xy
 	signal rgb: std_logic_vector(11 downto 0); -- pixel rgb out -> vga in
 begin
+	-- clock divider
 	process(clk)
 	begin
 		if rising_edge(clk) then
@@ -38,6 +39,7 @@ begin
 		end if;
 	end process;
 
+	-- get current pixel color
 	pixel: component pixeldata
 		port map (
 			pixel_clk => clk25(1),
@@ -48,8 +50,10 @@ begin
 			red => r,
 			green => g,
 			blue => b);
+	-- convert binary r, g, and b to 12-bit rgb
 	rgb <= r & r & r & r & g & g & g & g & b & b & b & b;
 
+	-- display on vga monitor
 	display: component vga
 	port map(
 		reset => reset,
@@ -62,8 +66,8 @@ begin
 		red => red,
 		green => green,
 		blue => blue);
-	vsync <= vsync_temp;
-	vsync_inv <= not vsync_temp;
+	vsync <= vsync_temp; -- vsync output
+	vsync_inv <= not vsync_temp; -- frame clock output
 
 
 end Behavioral;
diff --git a/src/pixeldata.vhd b/src/pixeldata.vhd
index 722d2d6..0fa229f 100644
--- a/src/pixeldata.vhd
+++ b/src/pixeldata.vhd
@@ -28,10 +28,12 @@ begin
 	begin
 		if rising_edge(pixel_clk) then
 			if (x >= sx) and (x < sx + 10) and (y >= sy) and (y < sy + 10) then
+				-- draw 10x10 pixel box in white
 				red <= '1';
 				green <= '1';
 				blue <= '1';
 			else
+				-- blue background
 				red <= '0';
 				green <= '0';
 				blue <= '1';