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authorlonkaars <loek@pipeframe.xyz>2024-05-14 15:02:34 +0200
committerlonkaars <loek@pipeframe.xyz>2024-05-14 15:02:34 +0200
commitdb8a968971df853c2f20b5ba0aa877cd89026ea5 (patch)
tree90345143fc6d4006c295a883d1a1023f32664c84 /dts/am335x-boneblack-uboot.dts
parent7429778133f01e278422bf68154470f190cd5572 (diff)
add decompiled dts
Diffstat (limited to 'dts/am335x-boneblack-uboot.dts')
-rw-r--r--dts/am335x-boneblack-uboot.dts3893
1 files changed, 3893 insertions, 0 deletions
diff --git a/dts/am335x-boneblack-uboot.dts b/dts/am335x-boneblack-uboot.dts
new file mode 100644
index 0000000..f944011
--- /dev/null
+++ b/dts/am335x-boneblack-uboot.dts
@@ -0,0 +1,3893 @@
+/dts-v1/;
+
+/ {
+ compatible = "ti,am335x-bone-black\0ti,am335x-bone\0ti,am33xx";
+ interrupt-parent = <0x01>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ model = "TI AM335x BeagleBone Black";
+
+ chosen {
+ stdout-path = "/ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0";
+ base_dtb = "am335x-boneblack-uboot.dts";
+ base_dtb_timestamp = "Tue Mar 5 15:17:41 2024";
+ };
+
+ aliases {
+ i2c0 = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0";
+ i2c1 = "/ocp/interconnect@48000000/segment@0/target-module@2a000/i2c@0";
+ i2c2 = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0";
+ serial0 = "/ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0";
+ serial1 = "/ocp/interconnect@48000000/segment@0/target-module@22000/serial@0";
+ serial2 = "/ocp/interconnect@48000000/segment@0/target-module@24000/serial@0";
+ serial3 = "/ocp/interconnect@48000000/segment@100000/target-module@a6000/serial@0";
+ serial4 = "/ocp/interconnect@48000000/segment@100000/target-module@a8000/serial@0";
+ serial5 = "/ocp/interconnect@48000000/segment@100000/target-module@aa000/serial@0";
+ d-can0 = "/ocp/interconnect@48000000/segment@100000/target-module@cc000/can@0";
+ d-can1 = "/ocp/interconnect@48000000/segment@100000/target-module@d0000/can@0";
+ usb0 = "/ocp/target-module@47400000/usb@1400";
+ usb1 = "/ocp/target-module@47400000/usb@1800";
+ phy0 = "/ocp/target-module@47400000/usb-phy@1300";
+ phy1 = "/ocp/target-module@47400000/usb-phy@1b00";
+ ethernet0 = "/ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/ethernet-ports/port@1";
+ ethernet1 = "/ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/ethernet-ports/port@2";
+ spi0 = "/ocp/interconnect@48000000/segment@0/target-module@30000/spi@0";
+ spi1 = "/ocp/interconnect@48000000/segment@100000/target-module@a0000/spi@0";
+ mmc0 = "/ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0";
+ mmc1 = "/ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0";
+ mmc2 = "/ocp/target-module@47810000/mmc@0";
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a8";
+ enable-method = "ti,am3352";
+ device_type = "cpu";
+ reg = <0x00>;
+ operating-points-v2 = <0x02>;
+ clocks = <0x03>;
+ clock-names = "cpu";
+ clock-latency = <0x493e0>;
+ cpu-idle-states = <0x04>;
+ cpu0-supply = <0x05>;
+ };
+
+ idle-states {
+
+ mpu_gate {
+ compatible = "arm,idle-state";
+ entry-latency-us = <0x28>;
+ exit-latency-us = <0x5a>;
+ min-residency-us = <0x12c>;
+ ti,idle-wkup-m3;
+ phandle = <0x04>;
+ };
+ };
+ };
+
+ opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <0x06>;
+ phandle = <0x02>;
+
+ opp-50-300000000 {
+ opp-hz = <0x00 0x11e1a300>;
+ opp-microvolt = <0xe7ef0 0xe34b8 0xec928>;
+ opp-supported-hw = <0x06 0x10>;
+ opp-suspend;
+ };
+
+ opp-100-275000000 {
+ opp-hz = <0x00 0x10642ac0>;
+ opp-microvolt = <0x10c8e0 0x1072f0 0x111ed0>;
+ opp-supported-hw = <0x01 0xff>;
+ opp-suspend;
+ };
+
+ opp-100-300000000 {
+ opp-hz = <0x00 0x11e1a300>;
+ opp-microvolt = <0x10c8e0 0x1072f0 0x111ed0>;
+ opp-supported-hw = <0x06 0x20>;
+ opp-suspend;
+ };
+
+ opp-100-500000000 {
+ opp-hz = <0x00 0x1dcd6500>;
+ opp-microvolt = <0x10c8e0 0x1072f0 0x111ed0>;
+ opp-supported-hw = <0x01 0xffff>;
+ };
+
+ opp-100-600000000 {
+ opp-hz = <0x00 0x23c34600>;
+ opp-microvolt = <0x10c8e0 0x1072f0 0x111ed0>;
+ opp-supported-hw = <0x06 0x40>;
+ };
+
+ opp-120-600000000 {
+ opp-hz = <0x00 0x23c34600>;
+ opp-microvolt = <0x124f80 0x11f1c0 0x12ad40>;
+ opp-supported-hw = <0x01 0xffff>;
+ };
+
+ opp-120-720000000 {
+ opp-hz = <0x00 0x2aea5400>;
+ opp-microvolt = <0x124f80 0x11f1c0 0x12ad40>;
+ opp-supported-hw = <0x06 0x80>;
+ };
+
+ opp-720000000 {
+ opp-hz = <0x00 0x2aea5400>;
+ opp-microvolt = <0x1339e0 0x12d770 0x139c50>;
+ opp-supported-hw = <0x01 0xffff>;
+ };
+
+ opp-800000000 {
+ opp-hz = <0x00 0x2faf0800>;
+ opp-microvolt = <0x1339e0 0x12d770 0x139c50>;
+ opp-supported-hw = <0x06 0x100>;
+ };
+
+ opp-1000000000 {
+ opp-hz = <0x00 0x3b9aca00>;
+ opp-microvolt = <0x1437c8 0x13d044 0x149f4c>;
+ opp-supported-hw = <0x04 0x200>;
+ };
+
+ oppnitro-1000000000 {
+ opp-supported-hw = <0x06 0x100>;
+ };
+ };
+
+ target-module@4b000000 {
+ compatible = "ti,sysc-omap4-simple\0ti,sysc";
+ clocks = <0x07 0xb8 0x00>;
+ clock-names = "fck";
+ ti,no-idle;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x4b000000 0x1000000>;
+
+ target-module@140000 {
+ compatible = "ti,sysc-omap4-simple\0ti,sysc";
+ clocks = <0x08 0x00 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x140000 0xec0000>;
+
+ pmu@0 {
+ compatible = "arm,cortex-a8-pmu";
+ interrupts = <0x03>;
+ };
+ };
+ };
+
+ soc {
+ compatible = "ti,omap-infra";
+ };
+
+ ocp {
+ compatible = "simple-pm-bus";
+ power-domains = <0x09>;
+ clocks = <0x07 0xbc 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges;
+ phandle = <0x5f>;
+
+ interconnect@44c00000 {
+ compatible = "ti,am33xx-l4-wkup\0simple-pm-bus";
+ power-domains = <0x0a>;
+ clocks = <0x0b 0x0c 0x00>;
+ clock-names = "fck";
+ reg = <0x44c00000 0x800 0x44c00800 0x800 0x44c01000 0x400 0x44c01400 0x400>;
+ reg-names = "ap\0la\0ia0\0ia1";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x44c00000 0x100000 0x100000 0x44d00000 0x100000 0x200000 0x44e00000 0x100000>;
+ phandle = <0x60>;
+
+ segment@0 {
+ compatible = "simple-pm-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x800 0x800 0x800 0x800 0x1000 0x1000 0x400 0x1400 0x1400 0x400>;
+ };
+
+ segment@100000 {
+ compatible = "simple-pm-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x100000 0x4000 0x4000 0x104000 0x1000 0x80000 0x180000 0x2000 0x82000 0x182000 0x1000>;
+
+ target-module@0 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x00 0x04>;
+ reg-names = "rev";
+ clocks = <0x0c 0x00 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x4000 0x80000 0x80000 0x2000>;
+
+ cpu@0 {
+ compatible = "ti,am3352-wkup-m3";
+ reg = <0x00 0x4000 0x80000 0x2000>;
+ reg-names = "umem\0dmem";
+ resets = <0x0a 0x03>;
+ reset-names = "rstctrl";
+ ti,pm-firmware = "am335x-pm-firmware.elf";
+ phandle = <0x2e>;
+ };
+ };
+ };
+
+ segment@200000 {
+ compatible = "simple-pm-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x200000 0x2000 0x2000 0x202000 0x1000 0x3000 0x203000 0x1000 0x4000 0x204000 0x1000 0x5000 0x205000 0x1000 0x6000 0x206000 0x1000 0x7000 0x207000 0x1000 0x8000 0x208000 0x1000 0x9000 0x209000 0x1000 0xa000 0x20a000 0x1000 0xb000 0x20b000 0x1000 0xc000 0x20c000 0x1000 0xd000 0x20d000 0x1000 0xf000 0x20f000 0x1000 0x10000 0x210000 0x10000 0x20000 0x220000 0x10000 0x30000 0x230000 0x1000 0x31000 0x231000 0x1000 0x32000 0x232000 0x1000 0x33000 0x233000 0x1000 0x34000 0x234000 0x1000 0x35000 0x235000 0x1000 0x36000 0x236000 0x1000 0x37000 0x237000 0x1000 0x38000 0x238000 0x1000 0x39000 0x239000 0x1000 0x3a000 0x23a000 0x1000 0x3e000 0x23e000 0x1000 0x3f000 0x23f000 0x1000 0xe000 0x20e000 0x1000 0x40000 0x240000 0x40000 0x80000 0x280000 0x1000>;
+
+ target-module@0 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x00 0x04>;
+ reg-names = "rev";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x2000>;
+
+ prcm@0 {
+ compatible = "ti,am3-prcm\0simple-bus";
+ reg = <0x00 0x2000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x2000>;
+ phandle = <0x61>;
+
+ clocks {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x62>;
+
+ clock-clk-32768 {
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ clock-output-names = "clk_32768_ck";
+ clock-frequency = <0x8000>;
+ phandle = <0x1c>;
+ };
+
+ clock-clk-rc32k {
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ clock-output-names = "clk_rc32k_ck";
+ clock-frequency = <0x7d00>;
+ phandle = <0x1b>;
+ };
+
+ clock-virt-19200000 {
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
+ clock-frequency = <0x124f800>;
+ phandle = <0x29>;
+ };
+
+ clock-virt-24000000 {
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ clock-output-names = "virt_24000000_ck";
+ clock-frequency = <0x16e3600>;
+ phandle = <0x2a>;
+ };
+
+ clock-virt-25000000 {
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ clock-output-names = "virt_25000000_ck";
+ clock-frequency = <0x17d7840>;
+ phandle = <0x2b>;
+ };
+
+ clock-virt-26000000 {
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
+ clock-frequency = <0x18cba80>;
+ phandle = <0x2c>;
+ };
+
+ clock-tclkin {
+ #clock-cells = <0x00>;
+ compatible = "fixed-clock";
+ clock-output-names = "tclkin_ck";
+ clock-frequency = <0xb71b00>;
+ phandle = <0x1a>;
+ };
+
+ clock@490 {
+ #clock-cells = <0x00>;
+ compatible = "ti,am3-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
+ clocks = <0x0d 0x0d>;
+ reg = <0x490 0x45c 0x468 0x460 0x464>;
+ phandle = <0x0e>;
+ };
+
+ clock-dpll-core-x2 {
+ #clock-cells = <0x00>;
+ compatible = "ti,am3-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
+ clocks = <0x0e>;
+ phandle = <0x0f>;
+ };
+
+ clock-dpll-core-m4@480 {
+ #clock-cells = <0x00>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4_ck";
+ clocks = <0x0f>;
+ ti,max-div = <0x1f>;
+ reg = <0x480>;
+ ti,index-starts-at-one;
+ phandle = <0x16>;
+ };
+
+ clock-dpll-core-m5@484 {
+ #clock-cells = <0x00>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5_ck";
+ clocks = <0x0f>;
+ ti,max-div = <0x1f>;
+ reg = <0x484>;
+ ti,index-starts-at-one;
+ phandle = <0x1e>;
+ };
+
+ clock-dpll-core-m6@4d8 {
+ #clock-cells = <0x00>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6_ck";
+ clocks = <0x0f>;
+ ti,max-div = <0x1f>;
+ reg = <0x4d8>;
+ ti,index-starts-at-one;
+ phandle = <0x63>;
+ };
+
+ clock@488 {
+ #clock-cells = <0x00>;
+ compatible = "ti,am3-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
+ clocks = <0x0d 0x0d>;
+ reg = <0x488 0x420 0x42c 0x424 0x428>;
+ phandle = <0x03>;
+ };
+
+ clock-dpll-mpu-m2@4a8 {
+ #clock-cells = <0x00>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
+ clocks = <0x03>;
+ ti,max-div = <0x1f>;
+ reg = <0x4a8>;
+ ti,index-starts-at-one;
+ phandle = <0x64>;
+ };
+
+ clock@494 {
+ #clock-cells = <0x00>;
+ compatible = "ti,am3-dpll-no-gate-clock";
+ clock-output-names = "dpll_ddr_ck";
+ clocks = <0x0d 0x0d>;
+ reg = <0x494 0x434 0x440 0x438 0x43c>;
+ phandle = <0x10>;
+ };
+
+ clock-dpll-ddr-m2@4a0 {
+ #clock-cells = <0x00>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll_ddr_m2_ck";
+ clocks = <0x10>;
+ ti,max-div = <0x1f>;
+ reg = <0x4a0>;
+ ti,index-starts-at-one;
+ phandle = <0x11>;
+ };
+
+ clock-dpll-ddr-m2-div2 {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_ddr_m2_div2_ck";
+ clocks = <0x11>;
+ clock-mult = <0x01>;
+ clock-div = <0x02>;
+ phandle = <0x65>;
+ };
+
+ clock@498 {
+ #clock-cells = <0x00>;
+ compatible = "ti,am3-dpll-no-gate-clock";
+ clock-output-names = "dpll_disp_ck";
+ clocks = <0x0d 0x0d>;
+ reg = <0x498 0x448 0x454 0x44c 0x450>;
+ phandle = <0x12>;
+ };
+
+ clock-dpll-disp-m2@4a4 {
+ #clock-cells = <0x00>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll_disp_m2_ck";
+ clocks = <0x12>;
+ ti,max-div = <0x1f>;
+ reg = <0x4a4>;
+ ti,index-starts-at-one;
+ ti,set-rate-parent;
+ phandle = <0x18>;
+ };
+
+ clock@48c {
+ #clock-cells = <0x00>;
+ compatible = "ti,am3-dpll-no-gate-j-type-clock";
+ clock-output-names = "dpll_per_ck";
+ clocks = <0x0d 0x0d>;
+ reg = <0x48c 0x470 0x49c 0x474 0x478>;
+ phandle = <0x13>;
+ };
+
+ clock-dpll-per-m2@4ac {
+ #clock-cells = <0x00>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
+ clocks = <0x13>;
+ ti,max-div = <0x1f>;
+ reg = <0x4ac>;
+ ti,index-starts-at-one;
+ phandle = <0x14>;
+ };
+
+ clock-dpll-per-m2-div4-wkupdm {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
+ clocks = <0x14>;
+ clock-mult = <0x01>;
+ clock-div = <0x04>;
+ phandle = <0x66>;
+ };
+
+ clock-dpll-per-m2-div4 {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_per_m2_div4_ck";
+ clocks = <0x14>;
+ clock-mult = <0x01>;
+ clock-div = <0x04>;
+ phandle = <0x67>;
+ };
+
+ clock-clk-24mhz {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "clk_24mhz";
+ clocks = <0x14>;
+ clock-mult = <0x01>;
+ clock-div = <0x08>;
+ phandle = <0x15>;
+ };
+
+ clock-clkdiv32k {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "clkdiv32k_ck";
+ clocks = <0x15>;
+ clock-mult = <0x01>;
+ clock-div = <0x2dc>;
+ phandle = <0x68>;
+ };
+
+ clock-l3-gclk {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "l3_gclk";
+ clocks = <0x16>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x17>;
+ };
+
+ clock-pruss-ocp-gclk@530 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "pruss_ocp_gclk";
+ clocks = <0x17 0x18>;
+ reg = <0x530>;
+ phandle = <0x53>;
+ };
+
+ clock-mmu-fck-1@914 {
+ #clock-cells = <0x00>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "mmu_fck";
+ clocks = <0x16>;
+ ti,bit-shift = <0x01>;
+ reg = <0x914>;
+ phandle = <0x69>;
+ };
+
+ clock-timer1-fck@528 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "timer1_fck";
+ clocks = <0x0d 0x19 0x00 0x00 0x1a 0x1b 0x1c>;
+ reg = <0x528>;
+ phandle = <0x31>;
+ };
+
+ clock-timer2-fck@508 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "timer2_fck";
+ clocks = <0x1a 0x0d 0x19 0x00 0x00>;
+ reg = <0x508>;
+ phandle = <0x36>;
+ };
+
+ clock-timer3-fck@50c {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "timer3_fck";
+ clocks = <0x1a 0x0d 0x19 0x00 0x00>;
+ reg = <0x50c>;
+ phandle = <0x6a>;
+ };
+
+ clock-timer4-fck@510 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "timer4_fck";
+ clocks = <0x1a 0x0d 0x19 0x00 0x00>;
+ reg = <0x510>;
+ phandle = <0x6b>;
+ };
+
+ clock-timer5-fck@518 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "timer5_fck";
+ clocks = <0x1a 0x0d 0x19 0x00 0x00>;
+ reg = <0x518>;
+ phandle = <0x6c>;
+ };
+
+ clock-timer6-fck@51c {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "timer6_fck";
+ clocks = <0x1a 0x0d 0x19 0x00 0x00>;
+ reg = <0x51c>;
+ phandle = <0x6d>;
+ };
+
+ clock-timer7-fck@504 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "timer7_fck";
+ clocks = <0x1a 0x0d 0x19 0x00 0x00>;
+ reg = <0x504>;
+ phandle = <0x6e>;
+ };
+
+ clock-usbotg-fck-8@47c {
+ #clock-cells = <0x00>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "usbotg_fck";
+ clocks = <0x13>;
+ ti,bit-shift = <0x08>;
+ reg = <0x47c>;
+ phandle = <0x6f>;
+ };
+
+ clock-dpll-core-m4-div2 {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_core_m4_div2_ck";
+ clocks = <0x16>;
+ clock-mult = <0x01>;
+ clock-div = <0x02>;
+ phandle = <0x1d>;
+ };
+
+ clock-ieee5000-fck-1@e4 {
+ #clock-cells = <0x00>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ieee5000_fck";
+ clocks = <0x1d>;
+ ti,bit-shift = <0x01>;
+ reg = <0xe4>;
+ phandle = <0x70>;
+ };
+
+ clock-wdt1-fck@538 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "wdt1_fck";
+ clocks = <0x1b 0x19 0x00 0x00>;
+ reg = <0x538>;
+ phandle = <0x71>;
+ };
+
+ clock-l4-rtc-gclk {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "l4_rtc_gclk";
+ clocks = <0x16>;
+ clock-mult = <0x01>;
+ clock-div = <0x02>;
+ phandle = <0x72>;
+ };
+
+ clock-l4hs-gclk {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "l4hs_gclk";
+ clocks = <0x16>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x73>;
+ };
+
+ clock-l3s-gclk {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "l3s_gclk";
+ clocks = <0x1d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x74>;
+ };
+
+ clock-l4fw-gclk {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "l4fw_gclk";
+ clocks = <0x1d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x75>;
+ };
+
+ clock-l4ls-gclk {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "l4ls_gclk";
+ clocks = <0x1d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x2d>;
+ };
+
+ clock-sysclk-div {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "sysclk_div_ck";
+ clocks = <0x16>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x76>;
+ };
+
+ clock-cpsw-125mhz-gclk {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "cpsw_125mhz_gclk";
+ clocks = <0x1e>;
+ clock-mult = <0x01>;
+ clock-div = <0x02>;
+ phandle = <0x49>;
+ };
+
+ clock-cpsw-cpts-rft@520 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "cpsw_cpts_rft_clk";
+ clocks = <0x1e 0x16>;
+ reg = <0x520>;
+ phandle = <0x4a>;
+ };
+
+ clock-gpio0-dbclk-mux@53c {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "gpio0_dbclk_mux_ck";
+ clocks = <0x1b 0x1c 0x19 0x00 0x00>;
+ reg = <0x53c>;
+ phandle = <0x77>;
+ };
+
+ clock-lcd-gclk@534 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "lcd_gclk";
+ clocks = <0x18 0x1e 0x14>;
+ reg = <0x534>;
+ ti,set-rate-parent;
+ phandle = <0x20>;
+ };
+
+ clock-mmc {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "mmc_clk";
+ clocks = <0x14>;
+ clock-mult = <0x01>;
+ clock-div = <0x02>;
+ phandle = <0x78>;
+ };
+
+ clock@52c {
+ compatible = "ti,clksel";
+ reg = <0x52c>;
+ #clock-cells = <0x02>;
+ #address-cells = <0x00>;
+
+ clock-gfx-fclk-clksel {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "gfx_fclk_clksel_ck";
+ clocks = <0x16 0x14>;
+ ti,bit-shift = <0x01>;
+ phandle = <0x1f>;
+ };
+
+ clock-gfx-fck-div {
+ #clock-cells = <0x00>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "gfx_fck_div_ck";
+ clocks = <0x1f>;
+ ti,max-div = <0x02>;
+ phandle = <0x79>;
+ };
+ };
+
+ clock@700 {
+ compatible = "ti,clksel";
+ reg = <0x700>;
+ #clock-cells = <0x02>;
+ #address-cells = <0x00>;
+
+ clock-sysclkout-pre {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "sysclkout_pre_ck";
+ clocks = <0x1c 0x17 0x11 0x14 0x20>;
+ phandle = <0x21>;
+ };
+
+ clock-clkout2-div {
+ #clock-cells = <0x00>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "clkout2_div_ck";
+ clocks = <0x21>;
+ ti,bit-shift = <0x03>;
+ ti,max-div = <0x08>;
+ phandle = <0x22>;
+ };
+
+ clock-clkout2 {
+ #clock-cells = <0x00>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "clkout2_ck";
+ clocks = <0x22>;
+ ti,bit-shift = <0x07>;
+ phandle = <0x7a>;
+ };
+ };
+ };
+
+ clockdomains {
+ phandle = <0x7b>;
+ };
+
+ clock@0 {
+ compatible = "ti,omap4-cm";
+ clock-output-names = "per_cm";
+ reg = <0x00 0x400>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x400>;
+ phandle = <0x7c>;
+
+ clock@38 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4ls_clkctrl";
+ reg = <0x38 0x2c 0x6c 0x28 0xac 0x0c 0xc0 0x1c 0xec 0x0c 0x10c 0x08 0x130 0x04>;
+ #clock-cells = <0x02>;
+ phandle = <0x34>;
+ };
+
+ clock@1c {
+ compatible = "ti,clkctrl";
+ clock-output-names = "l3s_clkctrl";
+ reg = <0x1c 0x04 0x30 0x08 0x68 0x04 0xf8 0x04>;
+ #clock-cells = <0x02>;
+ phandle = <0x35>;
+ };
+
+ clock@24 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "l3_clkctrl";
+ reg = <0x24 0x0c 0x94 0x10 0xbc 0x04 0xdc 0x08 0xfc 0x08>;
+ #clock-cells = <0x02>;
+ phandle = <0x07>;
+ };
+
+ clock@120 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4hs_clkctrl";
+ reg = <0x120 0x04>;
+ #clock-cells = <0x02>;
+ phandle = <0x47>;
+ };
+
+ clock@e8 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "pruss_ocp_clkctrl";
+ reg = <0xe8 0x04>;
+ #clock-cells = <0x02>;
+ phandle = <0x52>;
+ };
+
+ clock@0 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "cpsw_125mhz_clkctrl";
+ reg = <0x00 0x18>;
+ #clock-cells = <0x02>;
+ phandle = <0x48>;
+ };
+
+ clock@18 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "lcdc_clkctrl";
+ reg = <0x18 0x04>;
+ #clock-cells = <0x02>;
+ phandle = <0x46>;
+ };
+
+ clock@14c {
+ compatible = "ti,clkctrl";
+ clock-output-names = "clk_24mhz_clkctrl";
+ reg = <0x14c 0x04>;
+ #clock-cells = <0x02>;
+ phandle = <0x19>;
+ };
+ };
+
+ clock@400 {
+ compatible = "ti,omap4-cm";
+ clock-output-names = "wkup_cm";
+ reg = <0x400 0x100>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x400 0x100>;
+ phandle = <0x7d>;
+
+ clock@0 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
+ reg = <0x00 0x10 0xb4 0x24>;
+ #clock-cells = <0x02>;
+ phandle = <0x0b>;
+ };
+
+ clock@14 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "l3_aon_clkctrl";
+ reg = <0x14 0x04>;
+ #clock-cells = <0x02>;
+ phandle = <0x08>;
+ };
+
+ clock@b0 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_aon_clkctrl";
+ reg = <0xb0 0x04>;
+ #clock-cells = <0x02>;
+ phandle = <0x0c>;
+ };
+ };
+
+ clock@600 {
+ compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
+ reg = <0x600 0x100>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x600 0x100>;
+ phandle = <0x7e>;
+
+ clock@0 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
+ reg = <0x00 0x08>;
+ #clock-cells = <0x02>;
+ phandle = <0x40>;
+ };
+ };
+
+ clock@800 {
+ compatible = "ti,omap4-cm";
+ clock-output-names = "l4_rtc_cm";
+ reg = <0x800 0x100>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x800 0x100>;
+ phandle = <0x7f>;
+
+ clock@0 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4_rtc_clkctrl";
+ reg = <0x00 0x04>;
+ #clock-cells = <0x02>;
+ phandle = <0x33>;
+ };
+ };
+
+ clock@900 {
+ compatible = "ti,omap4-cm";
+ clock-output-names = "gfx_l3_cm";
+ reg = <0x900 0x100>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x900 0x100>;
+ phandle = <0x80>;
+
+ clock@0 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "gfx_l3_clkctrl";
+ reg = <0x00 0x08>;
+ #clock-cells = <0x02>;
+ phandle = <0x5c>;
+ };
+ };
+
+ clock@a00 {
+ compatible = "ti,omap4-cm";
+ clock-output-names = "l4_cefuse_cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xa00 0x100>;
+ phandle = <0x81>;
+
+ clock@0 {
+ compatible = "ti,clkctrl";
+ clock-output-names = "l4_cefuse_clkctrl";
+ reg = <0x00 0x24>;
+ #clock-cells = <0x02>;
+ phandle = <0x82>;
+ };
+ };
+
+ prm@c00 {
+ compatible = "ti,am3-prm-inst\0ti,omap-prm-inst";
+ reg = <0xc00 0x100>;
+ #reset-cells = <0x01>;
+ #power-domain-cells = <0x00>;
+ phandle = <0x09>;
+ };
+
+ prm@d00 {
+ compatible = "ti,am3-prm-inst\0ti,omap-prm-inst";
+ reg = <0xd00 0x100>;
+ #reset-cells = <0x01>;
+ #power-domain-cells = <0x00>;
+ phandle = <0x0a>;
+ };
+
+ prm@e00 {
+ compatible = "ti,am3-prm-inst\0ti,omap-prm-inst";
+ reg = <0xe00 0x100>;
+ #power-domain-cells = <0x00>;
+ phandle = <0x3f>;
+ };
+
+ prm@f00 {
+ compatible = "ti,am3-prm-inst\0ti,omap-prm-inst";
+ reg = <0xf00 0x100>;
+ #reset-cells = <0x01>;
+ phandle = <0x83>;
+ };
+
+ prm@1000 {
+ compatible = "ti,am3-prm-inst\0ti,omap-prm-inst";
+ reg = <0x1000 0x100>;
+ #power-domain-cells = <0x00>;
+ phandle = <0x32>;
+ };
+
+ prm@1100 {
+ compatible = "ti,am3-prm-inst\0ti,omap-prm-inst";
+ reg = <0x1100 0x100>;
+ #power-domain-cells = <0x00>;
+ #reset-cells = <0x01>;
+ phandle = <0x5d>;
+ };
+
+ prm@1200 {
+ compatible = "ti,am3-prm-inst\0ti,omap-prm-inst";
+ reg = <0x1200 0x100>;
+ #power-domain-cells = <0x00>;
+ phandle = <0x84>;
+ };
+ };
+ };
+
+ target-module@3000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x3000 0x1000>;
+ };
+
+ target-module@5000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x5000 0x1000>;
+ };
+
+ target-module@7000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x7000 0x04 0x7010 0x04 0x7114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x0b 0x08 0x00 0x0b 0x08 0x12>;
+ clock-names = "fck\0dbclk";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x7000 0x1000>;
+ phandle = <0x85>;
+
+ gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-ranges = <0x23 0x00 0x52 0x08 0x23 0x08 0x34 0x04 0x23 0x0c 0x5e 0x04 0x23 0x10 0x47 0x02 0x23 0x12 0x87 0x01 0x23 0x13 0x6c 0x02 0x23 0x15 0x49 0x01 0x23 0x16 0x08 0x02 0x23 0x1a 0x0a 0x02 0x23 0x1c 0x4a 0x01 0x23 0x1d 0x51 0x01 0x23 0x1e 0x1c 0x02>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x60>;
+ gpio-line-names = "[mdio_data]\0[mdio_clk]\0P9_22 [spi0_sclk]\0P9_21 [spi0_d0]\0P9_18 [spi0_d1]\0P9_17 [spi0_cs0]\0[mmc0_cd]\0P9_42A [ecappwm0]\0P8_35 [lcd d12]\0P8_33 [lcd d13]\0P8_31 [lcd d14]\0P8_32 [lcd d15]\0P9_20 [i2c2_sda]\0P9_19 [i2c2_scl]\0P9_26 [uart1_rxd]\0P9_24 [uart1_txd]\0[rmii1_txd3]\0[rmii1_txd2]\0[usb0_drvvbus]\0[hdmi cec]\0P9_41B\0[rmii1_txd1]\0P8_19 [ehrpwm2a]\0P8_13 [ehrpwm2b]\0NC\0NC\0P8_14\0P8_17\0[rmii1_txd0]\0[rmii1_refclk]\0P9_11 [uart4_rxd]\0P9_13 [uart4_txd]";
+ phandle = <0x38>;
+ };
+ };
+
+ target-module@9000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x9050 0x04 0x9054 0x04 0x9058 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x0b 0xb4 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x9000 0x1000>;
+
+ serial@0 {
+ compatible = "ti,am3352-uart\0ti,omap3-uart";
+ clock-frequency = <0x2dc6c00>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x48>;
+ status = "okay";
+ dmas = <0x24 0x1a 0x00 0x24 0x1b 0x00>;
+ dma-names = "tx\0rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x25>;
+ symlink = "bone/uart/0";
+ phandle = <0x86>;
+ };
+ };
+
+ target-module@b000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0xb000 0x08 0xb010 0x08 0xb090 0x08>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x307>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x0b 0xb8 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xb000 0x1000>;
+
+ i2c@0 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x46>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x26>;
+ clock-frequency = <0x61a80>;
+ symlink = "bone/i2c/0";
+ phandle = <0x87>;
+
+ tps@24 {
+ reg = <0x24>;
+ compatible = "ti,tps65217";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ interrupts = <0x07>;
+ interrupt-parent = <0x01>;
+ ti,pmic-shutdown-controller;
+ phandle = <0x5a>;
+
+ charger {
+ compatible = "ti,tps65217-charger";
+ interrupts = <0x00 0x01>;
+ interrupt-names = "USB\0AC";
+ status = "okay";
+ };
+
+ pwrbutton {
+ compatible = "ti,tps65217-pwrbutton";
+ interrupts = <0x02>;
+ status = "okay";
+ };
+
+ regulators {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ regulator@0 {
+ reg = <0x00>;
+ regulator-compatible = "dcdc1";
+ regulator-name = "vdds_dpr";
+ regulator-always-on;
+ phandle = <0x88>;
+ };
+
+ regulator@1 {
+ reg = <0x01>;
+ regulator-compatible = "dcdc2";
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <0xe1d48>;
+ regulator-max-microvolt = <0x149f4c>;
+ regulator-boot-on;
+ regulator-always-on;
+ phandle = <0x05>;
+ };
+
+ regulator@2 {
+ reg = <0x02>;
+ regulator-compatible = "dcdc3";
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <0xe1d48>;
+ regulator-max-microvolt = <0x118c30>;
+ regulator-boot-on;
+ regulator-always-on;
+ phandle = <0x89>;
+ };
+
+ regulator@3 {
+ reg = <0x03>;
+ regulator-compatible = "ldo1";
+ regulator-name = "vio,vrtc,vdds";
+ regulator-always-on;
+ phandle = <0x8a>;
+ };
+
+ regulator@4 {
+ reg = <0x04>;
+ regulator-compatible = "ldo2";
+ regulator-name = "vdd_3v3aux";
+ regulator-always-on;
+ phandle = <0x8b>;
+ };
+
+ regulator@5 {
+ reg = <0x05>;
+ regulator-compatible = "ldo3";
+ regulator-name = "vdd_1v8";
+ regulator-always-on;
+ regulator-min-microvolt = <0x1b7740>;
+ regulator-max-microvolt = <0x1b7740>;
+ phandle = <0x8c>;
+ };
+
+ regulator@6 {
+ reg = <0x06>;
+ regulator-compatible = "ldo4";
+ regulator-name = "vdd_3v3a";
+ regulator-always-on;
+ phandle = <0x27>;
+ };
+ };
+ };
+
+ baseboard_eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ vcc-supply = <0x27>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ phandle = <0x8d>;
+
+ baseboard_data@0 {
+ reg = <0x00 0x100>;
+ phandle = <0x8e>;
+ };
+ };
+ };
+ };
+
+ target-module@d000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0xd000 0x04 0xd010 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x0b 0xbc 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xd000 0x1000 0x1000 0xe000 0x1000>;
+
+ tscadc@0 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x00 0x1000>;
+ interrupts = <0x10>;
+ clocks = <0x28>;
+ clock-names = "fck";
+ status = "disabled";
+ dmas = <0x24 0x35 0x00 0x24 0x39 0x00>;
+ dma-names = "fifo0\0fifo1";
+ phandle = <0x8f>;
+
+ tsc {
+ compatible = "ti,am3359-tsc";
+ };
+
+ adc {
+ #io-channel-cells = <0x01>;
+ compatible = "ti,am3359-adc";
+ ti,adc-channels = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>;
+ ti,chan-step-avg = <0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10>;
+ ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>;
+ ti,chan-step-sampledelay = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
+ phandle = <0x90>;
+ };
+ };
+ };
+
+ target-module@10000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x10000 0x04>;
+ reg-names = "rev";
+ clocks = <0x0b 0x04 0x00>;
+ clock-names = "fck";
+ ti,no-idle;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x10000 0x10000 0x10000 0x20000 0x10000>;
+
+ scm@0 {
+ compatible = "ti,am3-scm\0simple-bus";
+ reg = <0x00 0x2000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ #pinctrl-cells = <0x01>;
+ ranges = <0x00 0x00 0x2000>;
+ phandle = <0x91>;
+
+ pinmux@800 {
+ compatible = "pinctrl-single";
+ reg = <0x800 0x238>;
+ #pinctrl-cells = <0x01>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <0x7f>;
+ phandle = <0x23>;
+
+ pinmux_comms_can_pins {
+ pinctrl-single,pins = <0x184 0x32 0x180 0x12>;
+ phandle = <0x3e>;
+ };
+
+ pinmux_comms_rs485_pins {
+ pinctrl-single,pins = <0x74 0x0e 0x70 0x2e>;
+ phandle = <0x3b>;
+ };
+
+ user-leds-s0-pins {
+ pinctrl-single,pins = <0x54 0x07 0x58 0x17 0x5c 0x07 0x60 0x17>;
+ phandle = <0x5e>;
+ };
+
+ i2c0-pins {
+ pinctrl-single,pins = <0x188 0x30 0x18c 0x30>;
+ phandle = <0x26>;
+ };
+
+ i2c2-pins {
+ pinctrl-single,pins = <0x178 0x33 0x17c 0x33>;
+ phandle = <0x3a>;
+ };
+
+ uart0-pins {
+ pinctrl-single,pins = <0x170 0x30 0x174 0x00>;
+ phandle = <0x25>;
+ };
+
+ cpsw-default-pins {
+ pinctrl-single,pins = <0x110 0x30 0x114 0x00 0x118 0x30 0x11c 0x00 0x120 0x00 0x124 0x00 0x128 0x00 0x12c 0x30 0x130 0x30 0x134 0x30 0x138 0x30 0x13c 0x30 0x140 0x30>;
+ phandle = <0x4c>;
+ };
+
+ cpsw-sleep-pins {
+ pinctrl-single,pins = <0x110 0x27 0x114 0x27 0x118 0x27 0x11c 0x27 0x120 0x27 0x124 0x27 0x128 0x27 0x12c 0x27 0x130 0x27 0x134 0x27 0x138 0x27 0x13c 0x27 0x140 0x27>;
+ phandle = <0x4d>;
+ };
+
+ davinci-mdio-default-pins {
+ pinctrl-single,pins = <0x148 0x30 0x14c 0x10 0x168 0x17>;
+ phandle = <0x4f>;
+ };
+
+ davinci-mdio-sleep-pins {
+ pinctrl-single,pins = <0x148 0x27 0x14c 0x27 0x168 0x27>;
+ phandle = <0x50>;
+ };
+
+ mmc1-pins {
+ pinctrl-single,pins = <0x160 0x2f 0xfc 0x30 0xf8 0x30 0xf4 0x30 0xf0 0x30 0x104 0x30 0x100 0x30>;
+ phandle = <0x37>;
+ };
+
+ emmc-pins {
+ pinctrl-single,pins = <0x80 0x32 0x84 0x32 0x00 0x31 0x04 0x31 0x08 0x31 0x0c 0x31 0x10 0x31 0x14 0x31 0x18 0x31 0x1c 0x31>;
+ phandle = <0x92>;
+ };
+ };
+
+ scm_conf@0 {
+ compatible = "syscon\0simple-bus";
+ reg = <0x00 0x800>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x800>;
+ phandle = <0x06>;
+
+ phy-gmii-sel {
+ compatible = "ti,am3352-phy-gmii-sel";
+ reg = <0x650 0x04>;
+ #phy-cells = <0x02>;
+ phandle = <0x4b>;
+ };
+
+ clocks {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ phandle = <0x93>;
+
+ clock-sys-clkin-22@40 {
+ #clock-cells = <0x00>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
+ clocks = <0x29 0x2a 0x2b 0x2c>;
+ ti,bit-shift = <0x16>;
+ reg = <0x40>;
+ phandle = <0x0d>;
+ };
+
+ clock-adc-tsc-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "adc_tsc_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x28>;
+ };
+
+ clock-dcan0-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "dcan0_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x3c>;
+ };
+
+ clock-dcan1-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "dcan1_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x3d>;
+ };
+
+ clock-mcasp0-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp0_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x94>;
+ };
+
+ clock-mcasp1-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "mcasp1_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x95>;
+ };
+
+ clock-smartreflex0-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex0_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x96>;
+ };
+
+ clock-smartreflex1-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "smartreflex1_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x97>;
+ };
+
+ clock-sha0-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "sha0_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x98>;
+ };
+
+ clock-aes0-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "aes0_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x99>;
+ };
+
+ clock-rng-fck {
+ #clock-cells = <0x00>;
+ compatible = "fixed-factor-clock";
+ clock-output-names = "rng_fck";
+ clocks = <0x0d>;
+ clock-mult = <0x01>;
+ clock-div = <0x01>;
+ phandle = <0x9a>;
+ };
+
+ clock@664 {
+ compatible = "ti,clksel";
+ reg = <0x664>;
+ #clock-cells = <0x02>;
+ #address-cells = <0x00>;
+
+ clock-ehrpwm0-tbclk {
+ #clock-cells = <0x00>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm0_tbclk";
+ clocks = <0x2d>;
+ ti,bit-shift = <0x00>;
+ phandle = <0x43>;
+ };
+
+ clock-ehrpwm1-tbclk {
+ #clock-cells = <0x00>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm1_tbclk";
+ clocks = <0x2d>;
+ ti,bit-shift = <0x01>;
+ phandle = <0x44>;
+ };
+
+ clock-ehrpwm2-tbclk {
+ #clock-cells = <0x00>;
+ compatible = "ti,gate-clock";
+ clock-output-names = "ehrpwm2_tbclk";
+ clocks = <0x2d>;
+ ti,bit-shift = <0x02>;
+ phandle = <0x45>;
+ };
+ };
+ };
+ };
+
+ control@620 {
+ compatible = "ti,am335x-usb-ctrl-module";
+ reg = <0x620 0x10 0x648 0x04>;
+ reg-names = "phy_ctrl\0wakeup";
+ phandle = <0x57>;
+ };
+
+ wkup_m3_ipc@1324 {
+ compatible = "ti,am3352-wkup-m3-ipc";
+ reg = <0x1324 0x24>;
+ interrupts = <0x4e>;
+ ti,rproc = <0x2e>;
+ mboxes = <0x2f 0x30>;
+ firmware-name = "am335x-bone-scale-data.bin";
+ phandle = <0x9b>;
+ };
+
+ dma-router@f90 {
+ compatible = "ti,am335x-edma-crossbar";
+ reg = <0xf90 0x40>;
+ #dma-cells = <0x03>;
+ dma-requests = <0x20>;
+ dma-masters = <0x24>;
+ phandle = <0x9c>;
+ };
+
+ clockdomains {
+ phandle = <0x9d>;
+ };
+ };
+ };
+
+ target-module@31000 {
+ compatible = "ti,sysc-omap2-timer\0ti,sysc";
+ reg = <0x31000 0x04 0x31010 0x04 0x31014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x303>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x0b 0xc4 0x00 0x0b 0x0c 0x00>;
+ clock-names = "fck\0ick";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x31000 0x1000>;
+ ti,no-reset-on-init;
+ ti,no-idle;
+ phandle = <0x9e>;
+
+ timer@0 {
+ compatible = "ti,am335x-timer-1ms";
+ reg = <0x00 0x400>;
+ interrupts = <0x43>;
+ ti,timer-alwon;
+ clocks = <0x31>;
+ clock-names = "fck";
+ assigned-clocks = <0x31>;
+ assigned-clock-parents = <0x0d>;
+ phandle = <0x9f>;
+ };
+ };
+
+ target-module@33000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x33000 0x1000>;
+ };
+
+ target-module@35000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x35000 0x04 0x35010 0x04 0x35014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x22>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x0b 0xd4 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x35000 0x1000>;
+
+ wdt@0 {
+ compatible = "ti,omap3-wdt";
+ reg = <0x00 0x1000>;
+ interrupts = <0x5b>;
+ phandle = <0xa0>;
+ };
+ };
+
+ target-module@37000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x37000 0x1000>;
+ };
+
+ target-module@39000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x39000 0x1000>;
+ };
+
+ target-module@3e000 {
+ compatible = "ti,sysc-omap4-simple\0ti,sysc";
+ reg = <0x3e074 0x04 0x3e078 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ power-domains = <0x32>;
+ clocks = <0x33 0x00 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x3e000 0x1000>;
+
+ rtc@0 {
+ compatible = "ti,am3352-rtc\0ti,da830-rtc";
+ reg = <0x00 0x1000>;
+ interrupts = <0x4b 0x4c>;
+ clocks = <0x1c 0x19 0x00 0x00>;
+ clock-names = "ext-clk\0int-clk";
+ system-power-controller;
+ phandle = <0xa1>;
+ };
+ };
+
+ target-module@40000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x40000 0x40000>;
+ };
+ };
+ };
+
+ interconnect@48000000 {
+ compatible = "ti,am33xx-l4-per\0simple-pm-bus";
+ power-domains = <0x09>;
+ clocks = <0x34 0x28 0x00>;
+ clock-names = "fck";
+ reg = <0x48000000 0x800 0x48000800 0x800 0x48001000 0x400 0x48001400 0x400 0x48001800 0x400 0x48001c00 0x400>;
+ reg-names = "ap\0la\0ia0\0ia1\0ia2\0ia3";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x48000000 0x100000 0x100000 0x48100000 0x100000 0x200000 0x48200000 0x100000 0x300000 0x48300000 0x100000 0x46000000 0x46000000 0x400000 0x46400000 0x46400000 0x400000>;
+ phandle = <0xa2>;
+
+ segment@0 {
+ compatible = "simple-pm-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x800 0x800 0x800 0x800 0x1000 0x1000 0x400 0x1400 0x1400 0x400 0x1800 0x1800 0x400 0x1c00 0x1c00 0x400 0x8000 0x8000 0x1000 0x9000 0x9000 0x1000 0x16000 0x16000 0x1000 0x17000 0x17000 0x1000 0x22000 0x22000 0x1000 0x23000 0x23000 0x1000 0x24000 0x24000 0x1000 0x25000 0x25000 0x1000 0x2a000 0x2a000 0x1000 0x2b000 0x2b000 0x1000 0x38000 0x38000 0x2000 0x3a000 0x3a000 0x1000 0x14000 0x14000 0x1000 0x15000 0x15000 0x1000 0x3c000 0x3c000 0x2000 0x3e000 0x3e000 0x1000 0x40000 0x40000 0x1000 0x41000 0x41000 0x1000 0x42000 0x42000 0x1000 0x43000 0x43000 0x1000 0x44000 0x44000 0x1000 0x45000 0x45000 0x1000 0x46000 0x46000 0x1000 0x47000 0x47000 0x1000 0x48000 0x48000 0x1000 0x49000 0x49000 0x1000 0x4c000 0x4c000 0x1000 0x4d000 0x4d000 0x1000 0x50000 0x50000 0x2000 0x52000 0x52000 0x1000 0x60000 0x60000 0x1000 0x61000 0x61000 0x1000 0x80000 0x80000 0x10000 0x90000 0x90000 0x1000 0xa0000 0xa0000 0x10000 0xb0000 0xb0000 0x1000 0x30000 0x30000 0x1000 0x31000 0x31000 0x1000 0x4a000 0x4a000 0x1000 0x4b000 0x4b000 0x1000 0xc8000 0xc8000 0x1000 0xc9000 0xc9000 0x1000 0xcc000 0xcc000 0x1000 0xcd000 0xcd000 0x1000 0xca000 0xca000 0x1000 0xcb000 0xcb000 0x1000 0x46000000 0x46000000 0x400000 0x46400000 0x46400000 0x400000>;
+
+ target-module@8000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x8000 0x1000>;
+ };
+
+ target-module@14000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x14000 0x1000>;
+ };
+
+ target-module@16000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x16000 0x1000>;
+ };
+
+ target-module@22000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x22050 0x04 0x22054 0x04 0x22058 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x34 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x22000 0x1000>;
+
+ serial@0 {
+ compatible = "ti,am3352-uart\0ti,omap3-uart";
+ clock-frequency = <0x2dc6c00>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x49>;
+ status = "disabled";
+ dmas = <0x24 0x1c 0x00 0x24 0x1d 0x00>;
+ dma-names = "tx\0rx";
+ phandle = <0xa3>;
+ };
+ };
+
+ target-module@24000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x24050 0x04 0x24054 0x04 0x24058 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x38 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x24000 0x1000>;
+
+ serial@0 {
+ compatible = "ti,am3352-uart\0ti,omap3-uart";
+ clock-frequency = <0x2dc6c00>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x4a>;
+ status = "disabled";
+ dmas = <0x24 0x1e 0x00 0x24 0x1f 0x00>;
+ dma-names = "tx\0rx";
+ phandle = <0xa4>;
+ };
+ };
+
+ target-module@2a000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x2a000 0x08 0x2a010 0x08 0x2a090 0x08>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x307>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0x10 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x2a000 0x1000>;
+
+ i2c@0 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x47>;
+ status = "disabled";
+ phandle = <0xa5>;
+ };
+ };
+
+ target-module@30000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x30000 0x04 0x30110 0x04 0x30114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x303>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0x14 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x30000 0x1000>;
+
+ spi@0 {
+ compatible = "ti,omap4-mcspi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x400>;
+ interrupts = <0x41>;
+ ti,spi-num-cs = <0x02>;
+ dmas = <0x24 0x10 0x00 0x24 0x11 0x00 0x24 0x12 0x00 0x24 0x13 0x00>;
+ dma-names = "tx0\0rx0\0tx1\0rx1";
+ status = "disabled";
+ phandle = <0xa6>;
+ };
+ };
+
+ target-module@38000 {
+ compatible = "ti,sysc-omap4-simple\0ti,sysc";
+ reg = <0x38000 0x04 0x38004 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ clocks = <0x35 0x18 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x38000 0x2000 0x46000000 0x46000000 0x400000>;
+
+ mcasp@0 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x2000 0x46000000 0x400000>;
+ reg-names = "mpu\0dat";
+ interrupts = <0x50 0x51>;
+ interrupt-names = "tx\0rx";
+ status = "disabled";
+ dmas = <0x24 0x08 0x02 0x24 0x09 0x02>;
+ dma-names = "tx\0rx";
+ phandle = <0xa7>;
+ };
+ };
+
+ target-module@3c000 {
+ compatible = "ti,sysc-omap4-simple\0ti,sysc";
+ reg = <0x3c000 0x04 0x3c004 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ clocks = <0x35 0x4c 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x3c000 0x2000 0x46400000 0x46400000 0x400000>;
+
+ mcasp@0 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x2000 0x46400000 0x400000>;
+ reg-names = "mpu\0dat";
+ interrupts = <0x52 0x53>;
+ interrupt-names = "tx\0rx";
+ status = "disabled";
+ dmas = <0x24 0x0a 0x02 0x24 0x0b 0x02>;
+ dma-names = "tx\0rx";
+ phandle = <0xa8>;
+ };
+ };
+
+ target-module@40000 {
+ compatible = "ti,sysc-omap4-timer\0ti,sysc";
+ reg = <0x40000 0x04 0x40010 0x04 0x40014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x48 0x00 0x34 0x28 0x00>;
+ clock-names = "fck\0ick";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x40000 0x1000>;
+ ti,no-reset-on-init;
+ ti,no-idle;
+ phandle = <0xa9>;
+
+ timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x00 0x400>;
+ interrupts = <0x44>;
+ clocks = <0x36>;
+ clock-names = "fck";
+ assigned-clocks = <0x36>;
+ assigned-clock-parents = <0x0d>;
+ phandle = <0xaa>;
+ };
+ };
+
+ target-module@42000 {
+ compatible = "ti,sysc-omap4-timer\0ti,sysc";
+ reg = <0x42000 0x04 0x42010 0x04 0x42014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x4c 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x42000 0x1000>;
+
+ timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x00 0x400>;
+ interrupts = <0x45>;
+ phandle = <0xab>;
+ };
+ };
+
+ target-module@44000 {
+ compatible = "ti,sysc-omap4-timer\0ti,sysc";
+ reg = <0x44000 0x04 0x44010 0x04 0x44014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x50 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x44000 0x1000>;
+
+ timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x00 0x400>;
+ interrupts = <0x5c>;
+ ti,timer-pwm;
+ phandle = <0xac>;
+ };
+ };
+
+ target-module@46000 {
+ compatible = "ti,sysc-omap4-timer\0ti,sysc";
+ reg = <0x46000 0x04 0x46010 0x04 0x46014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0xb4 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x46000 0x1000>;
+
+ timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x00 0x400>;
+ interrupts = <0x5d>;
+ ti,timer-pwm;
+ phandle = <0xad>;
+ };
+ };
+
+ target-module@48000 {
+ compatible = "ti,sysc-omap4-timer\0ti,sysc";
+ reg = <0x48000 0x04 0x48010 0x04 0x48014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0xb8 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x48000 0x1000>;
+
+ timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x00 0x400>;
+ interrupts = <0x5e>;
+ ti,timer-pwm;
+ phandle = <0xae>;
+ };
+ };
+
+ target-module@4a000 {
+ compatible = "ti,sysc-omap4-timer\0ti,sysc";
+ reg = <0x4a000 0x04 0x4a010 0x04 0x4a014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x44 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x4a000 0x1000>;
+
+ timer@0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x00 0x400>;
+ interrupts = <0x5f>;
+ ti,timer-pwm;
+ phandle = <0xaf>;
+ };
+ };
+
+ target-module@4c000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x4c000 0x04 0x4c010 0x04 0x4c114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0x74 0x00 0x34 0x74 0x12>;
+ clock-names = "fck\0dbclk";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x4c000 0x1000>;
+
+ gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-ranges = <0x23 0x00 0x00 0x08 0x23 0x08 0x5a 0x04 0x23 0x0c 0x0c 0x10 0x23 0x1c 0x1e 0x04>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x62>;
+ gpio-line-names = "P8_25 [mmc1_dat0]\0[mmc1_dat1]\0P8_5 [mmc1_dat2]\0P8_6 [mmc1_dat3]\0P8_23 [mmc1_dat4]\0P8_22 [mmc1_dat5]\0P8_3 [mmc1_dat6]\0P8_4 [mmc1_dat7]\0NC\0NC\0NC\0NC\0P8_12\0P8_11\0P8_16\0P8_15\0P9_15A\0P9_23\0P9_14 [ehrpwm1a]\0P9_16 [ehrpwm1b]\0[emmc rst]\0[usr0 led]\0[usr1 led]\0[usr2 led]\0[usr3 led]\0[hdmi irq]\0[usb vbus oc]\0[hdmi audio]\0P9_12\0P8_26\0P8_21 [emmc]\0P8_20 [emmc]";
+ phandle = <0x51>;
+ };
+ };
+
+ target-module@50000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x50000 0x2000>;
+ };
+
+ target-module@60000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x602fc 0x04 0x60110 0x04 0x60114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x307>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0x04 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x60000 0x1000>;
+
+ mmc@0 {
+ compatible = "ti,am335-sdhci";
+ ti,needs-special-reset;
+ dmas = <0x24 0x18 0x00 0x24 0x19 0x00>;
+ dma-names = "tx\0rx";
+ interrupts = <0x40>;
+ reg = <0x00 0x1000>;
+ status = "okay";
+ bus-width = <0x04>;
+ pinctrl-names = "default";
+ pinctrl-0 = <0x37>;
+ cd-gpios = <0x38 0x06 0x01>;
+ vmmc-supply = <0x39>;
+ phandle = <0xb0>;
+ };
+ };
+
+ target-module@80000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x80000 0x04 0x80010 0x04 0x80014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x303>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0x08 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x80000 0x10000>;
+
+ elm@0 {
+ compatible = "ti,am3352-elm";
+ reg = <0x00 0x2000>;
+ interrupts = <0x04>;
+ status = "disabled";
+ phandle = <0xb1>;
+ };
+ };
+
+ target-module@a0000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xa0000 0x10000>;
+ };
+
+ target-module@c8000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0xc8000 0x04 0xc8010 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ clocks = <0x34 0xd8 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xc8000 0x1000>;
+
+ mailbox@0 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x00 0x200>;
+ interrupts = <0x4d>;
+ #mbox-cells = <0x01>;
+ ti,mbox-num-users = <0x04>;
+ ti,mbox-num-fifos = <0x08>;
+ phandle = <0x2f>;
+
+ mbox-wkup-m3 {
+ ti,mbox-send-noirq;
+ ti,mbox-tx = <0x00 0x00 0x00>;
+ ti,mbox-rx = <0x00 0x00 0x03>;
+ phandle = <0x30>;
+ };
+ };
+ };
+
+ target-module@ca000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0xca000 0x04 0xca010 0x04 0xca014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x307>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0xd4 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xca000 0x1000>;
+
+ spinlock@0 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x00 0x1000>;
+ #hwlock-cells = <0x01>;
+ phandle = <0xb2>;
+ };
+ };
+
+ target-module@cc000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xcc000 0x1000>;
+ };
+ };
+
+ segment@100000 {
+ compatible = "simple-pm-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x8c000 0x18c000 0x1000 0x8d000 0x18d000 0x1000 0x8e000 0x18e000 0x1000 0x8f000 0x18f000 0x1000 0x9c000 0x19c000 0x1000 0x9d000 0x19d000 0x1000 0xa6000 0x1a6000 0x1000 0xa7000 0x1a7000 0x1000 0xa8000 0x1a8000 0x1000 0xa9000 0x1a9000 0x1000 0xaa000 0x1aa000 0x1000 0xab000 0x1ab000 0x1000 0xac000 0x1ac000 0x1000 0xad000 0x1ad000 0x1000 0xae000 0x1ae000 0x1000 0xaf000 0x1af000 0x1000 0xb0000 0x1b0000 0x10000 0xc0000 0x1c0000 0x1000 0xcc000 0x1cc000 0x2000 0xce000 0x1ce000 0x2000 0xd0000 0x1d0000 0x2000 0xd2000 0x1d2000 0x2000 0xd8000 0x1d8000 0x1000 0xd9000 0x1d9000 0x1000 0xa0000 0x1a0000 0x1000 0xa1000 0x1a1000 0x1000 0xa2000 0x1a2000 0x1000 0xa3000 0x1a3000 0x1000 0xa4000 0x1a4000 0x1000 0xa5000 0x1a5000 0x1000>;
+
+ target-module@8c000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x8c000 0x1000>;
+ };
+
+ target-module@8e000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x8e000 0x1000>;
+ };
+
+ target-module@9c000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x9c000 0x08 0x9c010 0x08 0x9c090 0x08>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x307>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0x0c 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x9c000 0x1000>;
+
+ i2c@0 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x1e>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x3a>;
+ clock-frequency = <0x186a0>;
+ symlink = "bone/i2c/2";
+ phandle = <0xb3>;
+
+ cape_eeprom0@54 {
+ compatible = "atmel,24c256";
+ reg = <0x54>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ phandle = <0xb4>;
+
+ cape_data@0 {
+ reg = <0x00 0x100>;
+ phandle = <0xb5>;
+ };
+ };
+
+ cape_eeprom1@55 {
+ compatible = "atmel,24c256";
+ reg = <0x55>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ phandle = <0xb6>;
+
+ cape_data@0 {
+ reg = <0x00 0x100>;
+ phandle = <0xb7>;
+ };
+ };
+
+ cape_eeprom2@56 {
+ compatible = "atmel,24c256";
+ reg = <0x56>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ phandle = <0xb8>;
+
+ cape_data@0 {
+ reg = <0x00 0x100>;
+ phandle = <0xb9>;
+ };
+ };
+
+ cape_eeprom3@57 {
+ compatible = "atmel,24c256";
+ reg = <0x57>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ phandle = <0xba>;
+
+ cape_data@0 {
+ reg = <0x00 0x100>;
+ phandle = <0xbb>;
+ };
+ };
+ };
+ };
+
+ target-module@a0000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0xa0000 0x04 0xa0110 0x04 0xa0114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x303>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0x18 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xa0000 0x1000>;
+
+ spi@0 {
+ compatible = "ti,omap4-mcspi";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ reg = <0x00 0x400>;
+ interrupts = <0x7d>;
+ ti,spi-num-cs = <0x02>;
+ dmas = <0x24 0x2a 0x00 0x24 0x2b 0x00 0x24 0x2c 0x00 0x24 0x2d 0x00>;
+ dma-names = "tx0\0rx0\0tx1\0rx1";
+ status = "disabled";
+ phandle = <0xbc>;
+ };
+ };
+
+ target-module@a2000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xa2000 0x1000>;
+ };
+
+ target-module@a4000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xa4000 0x1000>;
+ };
+
+ target-module@a6000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0xa6050 0x04 0xa6054 0x04 0xa6058 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x3c 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xa6000 0x1000>;
+
+ serial@0 {
+ compatible = "ti,am3352-uart\0ti,omap3-uart";
+ clock-frequency = <0x2dc6c00>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x2c>;
+ status = "disabled";
+ phandle = <0xbd>;
+ };
+ };
+
+ target-module@a8000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0xa8050 0x04 0xa8054 0x04 0xa8058 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x40 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xa8000 0x1000>;
+
+ serial@0 {
+ compatible = "ti,am3352-uart\0ti,omap3-uart";
+ clock-frequency = <0x2dc6c00>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x2d>;
+ status = "disabled";
+ symlink = "bone/uart/4";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x3b>;
+ phandle = <0xbe>;
+ };
+ };
+
+ target-module@aa000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0xaa050 0x04 0xaa054 0x04 0xaa058 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x00 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xaa000 0x1000>;
+
+ serial@0 {
+ compatible = "ti,am3352-uart\0ti,omap3-uart";
+ clock-frequency = <0x2dc6c00>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x2e>;
+ status = "disabled";
+ phandle = <0xbf>;
+ };
+ };
+
+ target-module@ac000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0xac000 0x04 0xac010 0x04 0xac114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0x78 0x00 0x34 0x78 0x12>;
+ clock-names = "fck\0dbclk";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xac000 0x1000>;
+
+ gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-ranges = <0x23 0x00 0x22 0x12 0x23 0x12 0x4d 0x04 0x23 0x16 0x38 0x0a>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x20>;
+ gpio-line-names = "P9_15B\0P8_18\0P8_7\0P8_8\0P8_10\0P8_9\0P8_45 [hdmi]\0P8_46 [hdmi]\0P8_43 [hdmi]\0P8_44 [hdmi]\0P8_41 [hdmi]\0P8_42 [hdmi]\0P8_39 [hdmi]\0P8_40 [hdmi]\0P8_37 [hdmi]\0P8_38 [hdmi]\0P8_36 [hdmi]\0P8_34 [hdmi]\0[rmii1_rxd3]\0[rmii1_rxd2]\0[rmii1_rxd1]\0[rmii1_rxd0]\0P8_27 [hdmi]\0P8_29 [hdmi]\0P8_28 [hdmi]\0P8_30 [hdmi]\0[mmc0_dat3]\0[mmc0_dat2]\0[mmc0_dat1]\0[mmc0_dat0]\0[mmc0_clk]\0[mmc0_cmd]";
+ phandle = <0xc0>;
+ };
+ };
+
+ target-module@ae000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0xae000 0x04 0xae010 0x04 0xae114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x07>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0x7c 0x00 0x34 0x7c 0x12>;
+ clock-names = "fck\0dbclk";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xae000 0x1000>;
+ phandle = <0xc1>;
+
+ gpio@0 {
+ compatible = "ti,omap4-gpio";
+ gpio-ranges = <0x23 0x00 0x42 0x05 0x23 0x05 0x62 0x02 0x23 0x07 0x4b 0x02 0x23 0x0d 0x8d 0x01 0x23 0x0e 0x64 0x08>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ reg = <0x00 0x1000>;
+ interrupts = <0x3e>;
+ gpio-line-names = "[mii col]\0[mii crs]\0[mii rx err]\0[mii tx en]\0[mii rx dv]\0[i2c0 sda]\0[i2c0 scl]\0[jtag emu0]\0[jtag emu1]\0[mii tx clk]\0[mii rx clk]\0NC\0NC\0[usb vbus en]\0P9_31 [spi1_sclk]\0P9_29 [spi1_d0]\0P9_30 [spi1_d1]\0P9_28 [spi1_cs0]\0P9_42B [ecappwm0]\0P9_27\0P9_41A\0P9_25\0NC\0NC\0NC\0NC\0NC\0NC\0NC\0NC\0NC\0NC";
+ phandle = <0xc2>;
+ };
+ };
+
+ target-module@b0000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xb0000 0x10000>;
+ };
+
+ target-module@cc000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0xcc020 0x04>;
+ reg-names = "rev";
+ clocks = <0x34 0x88 0x00 0x3c>;
+ clock-names = "fck\0osc";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xcc000 0x2000>;
+
+ can@0 {
+ compatible = "ti,am3352-d_can";
+ reg = <0x00 0x2000>;
+ clocks = <0x3c>;
+ clock-names = "fck";
+ syscon-raminit = <0x06 0x644 0x00>;
+ interrupts = <0x34>;
+ status = "disabled";
+ phandle = <0xc3>;
+ };
+ };
+
+ target-module@d0000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0xd0020 0x04>;
+ reg-names = "rev";
+ clocks = <0x34 0x8c 0x00 0x3d>;
+ clock-names = "fck\0osc";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xd0000 0x2000>;
+
+ can@0 {
+ compatible = "ti,am3352-d_can";
+ reg = <0x00 0x2000>;
+ clocks = <0x3d>;
+ clock-names = "fck";
+ syscon-raminit = <0x06 0x644 0x01>;
+ interrupts = <0x37>;
+ status = "disabled";
+ symlink = "bone/can/1";
+ pinctrl-names = "default";
+ pinctrl-0 = <0x3e>;
+ phandle = <0xc4>;
+ };
+ };
+
+ target-module@d8000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0xd82fc 0x04 0xd8110 0x04 0xd8114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x307>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x34 0xbc 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xd8000 0x1000>;
+
+ mmc@0 {
+ compatible = "ti,am335-sdhci";
+ ti,needs-special-reset;
+ dmas = <0x24 0x02 0x00 0x24 0x03 0x00>;
+ dma-names = "tx\0rx";
+ interrupts = <0x1c>;
+ reg = <0x00 0x1000>;
+ status = "disabled";
+ phandle = <0xc5>;
+ };
+ };
+ };
+
+ segment@200000 {
+ compatible = "simple-pm-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x200000 0x10000>;
+
+ target-module@0 {
+ compatible = "ti,sysc-omap4-simple\0ti,sysc";
+ power-domains = <0x3f>;
+ clocks = <0x40 0x04 0x00>;
+ clock-names = "fck";
+ ti,no-idle;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x10000>;
+
+ mpu@0 {
+ compatible = "ti,omap3-mpu";
+ pm-sram = <0x41 0x42>;
+ };
+ };
+ };
+
+ segment@300000 {
+ compatible = "simple-pm-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x300000 0x1000 0x1000 0x301000 0x1000 0x2000 0x302000 0x1000 0x3000 0x303000 0x1000 0x4000 0x304000 0x1000 0x5000 0x305000 0x1000 0xe000 0x30e000 0x1000 0xf000 0x30f000 0x1000 0x18000 0x318000 0x4000 0x1c000 0x31c000 0x1000 0x10000 0x310000 0x2000 0x12000 0x312000 0x1000 0x15000 0x315000 0x1000 0x16000 0x316000 0x1000 0x17000 0x317000 0x1000 0x13000 0x313000 0x1000 0x14000 0x314000 0x1000 0x20000 0x320000 0x1000 0x21000 0x321000 0x1000 0x22000 0x322000 0x1000 0x23000 0x323000 0x1000 0x24000 0x324000 0x1000 0x25000 0x325000 0x1000>;
+
+ target-module@0 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x00 0x04 0x04 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-midle = <0x00 0x01 0x02 0x03>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x9c 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x1000>;
+
+ epwmss@0 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x00 0x10>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ status = "disabled";
+ ranges = <0x00 0x00 0x1000>;
+ phandle = <0xc6>;
+
+ pwm@100 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <0x03>;
+ reg = <0x100 0x80>;
+ clocks = <0x2d>;
+ clock-names = "fck";
+ status = "disabled";
+ phandle = <0xc7>;
+ };
+
+ counter@180 {
+ compatible = "ti,am3352-eqep";
+ reg = <0x180 0x80>;
+ clocks = <0x2d>;
+ clock-names = "sysclkout";
+ interrupts = <0x4f>;
+ status = "disabled";
+ phandle = <0xc8>;
+ };
+
+ pwm@200 {
+ compatible = "ti,am3352-ehrpwm";
+ #pwm-cells = <0x03>;
+ reg = <0x200 0x80>;
+ clocks = <0x43 0x2d>;
+ clock-names = "tbclk\0fck";
+ status = "disabled";
+ phandle = <0xc9>;
+ };
+ };
+ };
+
+ target-module@2000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x2000 0x04 0x2004 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-midle = <0x00 0x01 0x02 0x03>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0x94 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x2000 0x1000>;
+
+ epwmss@0 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x00 0x10>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ status = "disabled";
+ ranges = <0x00 0x00 0x1000>;
+ phandle = <0xca>;
+
+ pwm@100 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <0x03>;
+ reg = <0x100 0x80>;
+ clocks = <0x2d>;
+ clock-names = "fck";
+ status = "disabled";
+ phandle = <0xcb>;
+ };
+
+ counter@180 {
+ compatible = "ti,am3352-eqep";
+ reg = <0x180 0x80>;
+ clocks = <0x2d>;
+ clock-names = "sysclkout";
+ interrupts = <0x58>;
+ status = "disabled";
+ phandle = <0xcc>;
+ };
+
+ pwm@200 {
+ compatible = "ti,am3352-ehrpwm";
+ #pwm-cells = <0x03>;
+ reg = <0x200 0x80>;
+ clocks = <0x44 0x2d>;
+ clock-names = "tbclk\0fck";
+ status = "disabled";
+ phandle = <0xcd>;
+ };
+ };
+ };
+
+ target-module@4000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x4000 0x04 0x4004 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-midle = <0x00 0x01 0x02 0x03>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ clocks = <0x34 0xa0 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x4000 0x1000>;
+
+ epwmss@0 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x00 0x10>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ status = "disabled";
+ ranges = <0x00 0x00 0x1000>;
+ phandle = <0xce>;
+
+ pwm@100 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <0x03>;
+ reg = <0x100 0x80>;
+ clocks = <0x2d>;
+ clock-names = "fck";
+ status = "disabled";
+ phandle = <0xcf>;
+ };
+
+ counter@180 {
+ compatible = "ti,am3352-eqep";
+ reg = <0x180 0x80>;
+ clocks = <0x2d>;
+ clock-names = "sysclkout";
+ interrupts = <0x59>;
+ status = "disabled";
+ phandle = <0xd0>;
+ };
+
+ pwm@200 {
+ compatible = "ti,am3352-ehrpwm";
+ #pwm-cells = <0x03>;
+ reg = <0x200 0x80>;
+ clocks = <0x45 0x2d>;
+ clock-names = "tbclk\0fck";
+ status = "disabled";
+ phandle = <0xd1>;
+ };
+ };
+ };
+
+ target-module@e000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0xe000 0x04 0xe054 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-midle = <0x00 0x01 0x02>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ clocks = <0x46 0x00 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xe000 0x1000>;
+
+ lcdc@0 {
+ compatible = "ti,am33xx-tilcdc";
+ reg = <0x00 0x1000>;
+ interrupts = <0x24>;
+ status = "disabled";
+ phandle = <0xd2>;
+ };
+ };
+
+ target-module@10000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x11fe0 0x04 0x11fe4 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-sidle = <0x00 0x01>;
+ clocks = <0x34 0x58 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x10000 0x2000>;
+
+ rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x00 0x2000>;
+ interrupts = <0x6f>;
+ phandle = <0xd3>;
+ };
+ };
+
+ target-module@13000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x13000 0x1000>;
+ };
+
+ target-module@15000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x15000 0x1000 0x1000 0x16000 0x1000>;
+ };
+
+ target-module@18000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x18000 0x4000>;
+ };
+
+ target-module@20000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x20000 0x1000>;
+ };
+
+ target-module@22000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x22000 0x1000>;
+ };
+
+ target-module@24000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x24000 0x1000>;
+ };
+ };
+ };
+
+ interconnect@47c00000 {
+ compatible = "ti,am33xx-l4-fw\0simple-bus";
+ reg = <0x47c00000 0x800 0x47c00800 0x800 0x47c01000 0x400>;
+ reg-names = "ap\0la\0ia0";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x47c00000 0x1000000>;
+ phandle = <0xd4>;
+
+ segment@0 {
+ compatible = "simple-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x800 0x800 0x800 0x800 0x1000 0x1000 0x400 0xc000 0xc000 0x1000 0xd000 0xd000 0x1000 0xe000 0xe000 0x1000 0xf000 0xf000 0x1000 0x10000 0x10000 0x1000 0x11000 0x11000 0x1000 0x1a000 0x1a000 0x1000 0x1b000 0x1b000 0x1000 0x24000 0x24000 0x1000 0x25000 0x25000 0x1000 0x26000 0x26000 0x1000 0x27000 0x27000 0x1000 0x30000 0x30000 0x1000 0x31000 0x31000 0x1000 0x38000 0x38000 0x1000 0x39000 0x39000 0x1000 0x3a000 0x3a000 0x1000 0x3b000 0x3b000 0x1000 0x3e000 0x3e000 0x1000 0x3f000 0x3f000 0x1000 0x3c000 0x3c000 0x1000 0x40000 0x40000 0x1000 0x46000 0x46000 0x1000 0x47000 0x47000 0x1000 0x44000 0x44000 0x1000 0x45000 0x45000 0x1000 0x28000 0x28000 0x1000 0x29000 0x29000 0x1000 0x32000 0x32000 0x1000 0x33000 0x33000 0x1000 0x3d000 0x3d000 0x1000 0x41000 0x41000 0x1000 0x42000 0x42000 0x1000 0x43000 0x43000 0x1000 0x14000 0x14000 0x1000 0x15000 0x15000 0x1000>;
+
+ target-module@c000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xc000 0x1000>;
+ };
+
+ target-module@e000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0xe000 0x1000>;
+ };
+
+ target-module@10000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x10000 0x1000>;
+ };
+
+ target-module@14000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x14000 0x1000>;
+ };
+
+ target-module@1a000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x1a000 0x1000>;
+ };
+
+ target-module@24000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x24000 0x1000>;
+ };
+
+ target-module@26000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x26000 0x1000>;
+ };
+
+ target-module@28000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x28000 0x1000>;
+ };
+
+ target-module@30000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x30000 0x1000>;
+ };
+
+ target-module@32000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x32000 0x1000>;
+ };
+
+ target-module@38000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x38000 0x1000>;
+ };
+
+ target-module@3a000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x3a000 0x1000>;
+ };
+
+ target-module@3c000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x3c000 0x1000>;
+ };
+
+ target-module@3e000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x3e000 0x1000>;
+ };
+
+ target-module@40000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x40000 0x1000>;
+ };
+
+ target-module@42000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x42000 0x1000>;
+ };
+
+ target-module@44000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x44000 0x1000>;
+ };
+
+ target-module@46000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x46000 0x1000>;
+ };
+ };
+ };
+
+ interconnect@4a000000 {
+ compatible = "ti,am33xx-l4-fast\0simple-pm-bus";
+ power-domains = <0x09>;
+ clocks = <0x47 0x00 0x00>;
+ clock-names = "fck";
+ reg = <0x4a000000 0x800 0x4a000800 0x800 0x4a001000 0x400>;
+ reg-names = "ap\0la\0ia0";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x4a000000 0x1000000>;
+ phandle = <0xd5>;
+
+ segment@0 {
+ compatible = "simple-pm-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x800 0x800 0x800 0x800 0x1000 0x1000 0x400 0x100000 0x100000 0x8000 0x108000 0x108000 0x1000 0x180000 0x180000 0x20000 0x1a0000 0x1a0000 0x1000 0x200000 0x200000 0x80000 0x280000 0x280000 0x1000 0x300000 0x300000 0x80000 0x380000 0x380000 0x1000>;
+
+ target-module@100000 {
+ compatible = "ti,sysc-omap4-simple\0ti,sysc";
+ reg = <0x101200 0x04 0x101208 0x04 0x101204 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x00>;
+ ti,sysc-midle = <0x00 0x01>;
+ ti,sysc-sidle = <0x00 0x01>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x48 0x14 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x100000 0x8000>;
+
+ ethernet@0 {
+ compatible = "ti,am335x-cpsw\0ti,cpsw";
+ clocks = <0x49 0x4a>;
+ clock-names = "fck\0cpts";
+ cpdma_channels = <0x08>;
+ ale_entries = <0x400>;
+ bd_ram_size = <0x2000>;
+ mac_control = <0x20>;
+ slaves = <0x02>;
+ active_slave = <0x00>;
+ cpts_clock_mult = <0x80000000>;
+ cpts_clock_shift = <0x1d>;
+ reg = <0x00 0x800 0x1200 0x100>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ interrupts = <0x28 0x29 0x2a 0x2b>;
+ ranges = <0x00 0x00 0x8000>;
+ syscon = <0x06>;
+ status = "disabled";
+ phandle = <0xd6>;
+
+ mdio@1000 {
+ compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
+ clocks = <0x48 0x14 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ bus_freq = <0xf4240>;
+ reg = <0x1000 0x100>;
+ status = "disabled";
+ phandle = <0xd7>;
+ };
+
+ slave@200 {
+ mac-address = [00 00 00 00 00 00];
+ phys = <0x4b 0x01 0x01>;
+ phandle = <0xd8>;
+ };
+
+ slave@300 {
+ mac-address = [00 00 00 00 00 00];
+ phys = <0x4b 0x02 0x01>;
+ phandle = <0xd9>;
+ };
+ };
+
+ switch@0 {
+ compatible = "ti,am335x-cpsw-switch\0ti,cpsw-switch";
+ reg = <0x00 0x4000>;
+ ranges = <0x00 0x00 0x4000>;
+ clocks = <0x49>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ syscon = <0x06>;
+ status = "okay";
+ interrupts = <0x28 0x29 0x2a 0x2b>;
+ interrupt-names = "rx_thresh\0rx\0tx\0misc";
+ pinctrl-names = "default\0sleep";
+ pinctrl-0 = <0x4c>;
+ pinctrl-1 = <0x4d>;
+ phandle = <0xda>;
+
+ ethernet-ports {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ port@1 {
+ reg = <0x01>;
+ label = "port1";
+ mac-address = [00 00 00 00 00 00];
+ phys = <0x4b 0x01 0x01>;
+ phy-handle = <0x4e>;
+ phy-mode = "mii";
+ ti,dual-emac-pvid = <0x01>;
+ phandle = <0xdb>;
+ };
+
+ port@2 {
+ reg = <0x02>;
+ label = "port2";
+ mac-address = [00 00 00 00 00 00];
+ phys = <0x4b 0x02 0x01>;
+ status = "disabled";
+ phandle = <0xdc>;
+ };
+ };
+
+ mdio@1000 {
+ compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
+ clocks = <0x49>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ bus_freq = <0xf4240>;
+ reg = <0x1000 0x100>;
+ pinctrl-names = "default\0sleep";
+ pinctrl-0 = <0x4f>;
+ pinctrl-1 = <0x50>;
+ phandle = <0xdd>;
+
+ ethernet-phy@0 {
+ reg = <0x00>;
+ reset-gpios = <0x51 0x08 0x01>;
+ reset-assert-us = <0x12c>;
+ reset-deassert-us = <0x1964>;
+ phandle = <0x4e>;
+ };
+ };
+
+ cpts {
+ clocks = <0x4a>;
+ clock-names = "cpts";
+ };
+ };
+ };
+
+ target-module@180000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x180000 0x20000>;
+ };
+
+ target-module@200000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x200000 0x80000>;
+ };
+
+ target-module@300000 {
+ compatible = "ti,sysc-pruss\0ti,sysc";
+ reg = <0x326000 0x04 0x326004 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-mask = <0x30>;
+ ti,sysc-midle = <0x00 0x01 0x02>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ clocks = <0x52 0x00 0x00>;
+ clock-names = "fck";
+ resets = <0x09 0x01>;
+ reset-names = "rstctrl";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x300000 0x80000>;
+ status = "okay";
+ phandle = <0xde>;
+
+ pruss@0 {
+ compatible = "ti,am3356-pruss";
+ reg = <0x00 0x80000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges;
+ phandle = <0xdf>;
+
+ memories@0 {
+ reg = <0x00 0x2000 0x2000 0x2000 0x10000 0x3000>;
+ reg-names = "dram0\0dram1\0shrdram2";
+ phandle = <0xe0>;
+ };
+
+ cfg@26000 {
+ compatible = "ti,pruss-cfg\0syscon";
+ reg = <0x26000 0x2000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x26000 0x2000>;
+ phandle = <0xe1>;
+
+ clocks {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0x00>;
+ clocks = <0x17 0x53>;
+ phandle = <0xe2>;
+ };
+ };
+ };
+
+ mii-rt@32000 {
+ compatible = "ti,pruss-mii\0syscon";
+ reg = <0x32000 0x58>;
+ phandle = <0xe3>;
+ };
+
+ interrupt-controller@20000 {
+ compatible = "ti,pruss-intc";
+ reg = <0x20000 0x2000>;
+ interrupts = <0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b>;
+ interrupt-names = "host_intr0\0host_intr1\0host_intr2\0host_intr3\0host_intr4\0host_intr5\0host_intr6\0host_intr7";
+ interrupt-controller;
+ #interrupt-cells = <0x03>;
+ phandle = <0xe4>;
+ };
+
+ pru@34000 {
+ compatible = "ti,am3356-pru";
+ reg = <0x34000 0x2000 0x22000 0x400 0x22400 0x100>;
+ reg-names = "iram\0control\0debug";
+ firmware-name = "am335x-pru0-fw";
+ phandle = <0xe5>;
+ };
+
+ pru@38000 {
+ compatible = "ti,am3356-pru";
+ reg = <0x38000 0x2000 0x24000 0x400 0x24400 0x100>;
+ reg-names = "iram\0control\0debug";
+ firmware-name = "am335x-pru1-fw";
+ phandle = <0xe6>;
+ };
+
+ mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x90>;
+ clocks = <0x16>;
+ clock-names = "fck";
+ bus_freq = <0xf4240>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ phandle = <0xe7>;
+ };
+ };
+ };
+ };
+ };
+
+ interconnect@4b140000 {
+ compatible = "ti,am33xx-l4-mpuss\0simple-bus";
+ reg = <0x4b144400 0x100 0x4b144800 0x400>;
+ reg-names = "la\0ap";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x4b140000 0x8000>;
+ phandle = <0xe8>;
+
+ segment@0 {
+ compatible = "simple-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x4800 0x4800 0x400 0x1000 0x1000 0x1000 0x2000 0x2000 0x1000 0x4000 0x4000 0x400 0x5000 0x5000 0x400 0x00 0x00 0x1000 0x3000 0x3000 0x1000 0x800 0x800 0x800>;
+
+ target-module@0 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x00 0x1000 0x1000 0x1000 0x1000 0x2000 0x2000 0x1000>;
+ };
+
+ target-module@3000 {
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x3000 0x1000>;
+ };
+ };
+ };
+
+ interrupt-controller@48200000 {
+ compatible = "ti,am33xx-intc";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ reg = <0x48200000 0x1000>;
+ phandle = <0x01>;
+ };
+
+ target-module@49000000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x49000000 0x04>;
+ reg-names = "rev";
+ clocks = <0x07 0x98 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x49000000 0x10000>;
+
+ dma@0 {
+ compatible = "ti,edma3-tpcc";
+ reg = <0x00 0x10000>;
+ reg-names = "edma3_cc";
+ interrupts = <0x0c 0x0d 0x0e>;
+ interrupt-names = "edma3_ccint\0edma3_mperr\0edma3_ccerrint";
+ dma-requests = <0x40>;
+ #dma-cells = <0x02>;
+ ti,tptcs = <0x54 0x07 0x55 0x05 0x56 0x00>;
+ ti,edma-memcpy-channels = <0x14 0x15>;
+ phandle = <0x24>;
+ };
+ };
+
+ target-module@49800000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x49800000 0x04 0x49800010 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-midle = <0x00>;
+ ti,sysc-sidle = <0x00 0x02>;
+ clocks = <0x07 0x00 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x49800000 0x100000>;
+
+ dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0x00 0x100000>;
+ interrupts = <0x70>;
+ interrupt-names = "edma3_tcerrint";
+ phandle = <0x54>;
+ };
+ };
+
+ target-module@49900000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x49900000 0x04 0x49900010 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-midle = <0x00>;
+ ti,sysc-sidle = <0x00 0x02>;
+ clocks = <0x07 0xd8 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x49900000 0x100000>;
+
+ dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0x00 0x100000>;
+ interrupts = <0x71>;
+ interrupt-names = "edma3_tcerrint";
+ phandle = <0x55>;
+ };
+ };
+
+ target-module@49a00000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x49a00000 0x04 0x49a00010 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-mask = <0x01>;
+ ti,sysc-midle = <0x00>;
+ ti,sysc-sidle = <0x00 0x02>;
+ clocks = <0x07 0xdc 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x49a00000 0x100000>;
+
+ dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0x00 0x100000>;
+ interrupts = <0x72>;
+ interrupt-names = "edma3_tcerrint";
+ phandle = <0x56>;
+ };
+ };
+
+ target-module@47810000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x478102fc 0x04 0x47810110 0x04 0x47810114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x307>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x35 0xdc 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x47810000 0x1000>;
+
+ mmc@0 {
+ compatible = "ti,am335-sdhci";
+ ti,needs-special-reset;
+ interrupts = <0x1d>;
+ reg = <0x00 0x1000>;
+ status = "disabled";
+ phandle = <0xe9>;
+ };
+ };
+
+ target-module@47400000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x47400000 0x04 0x47400010 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-mask = <0x03>;
+ ti,sysc-midle = <0x00 0x01 0x02>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,sysc-delay-us = <0x02>;
+ clocks = <0x35 0x00 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x47400000 0x8000>;
+ phandle = <0xea>;
+
+ usb-phy@1300 {
+ compatible = "ti,am335x-usb-phy";
+ reg = <0x1300 0x100>;
+ reg-names = "phy";
+ ti,ctrl_mod = <0x57>;
+ #phy-cells = <0x00>;
+ phandle = <0x58>;
+ };
+
+ usb@1400 {
+ compatible = "ti,musb-am33xx";
+ reg = <0x1400 0x400 0x1000 0x200>;
+ reg-names = "mc\0control";
+ interrupts = <0x12>;
+ interrupt-names = "mc\0vbus";
+ dr_mode = "peripheral";
+ mentor,multipoint = <0x01>;
+ mentor,num-eps = <0x10>;
+ mentor,ram-bits = <0x0c>;
+ mentor,power = <0x1f4>;
+ phys = <0x58>;
+ dmas = <0x59 0x00 0x00 0x59 0x01 0x00 0x59 0x02 0x00 0x59 0x03 0x00 0x59 0x04 0x00 0x59 0x05 0x00 0x59 0x06 0x00 0x59 0x07 0x00 0x59 0x08 0x00 0x59 0x09 0x00 0x59 0x0a 0x00 0x59 0x0b 0x00 0x59 0x0c 0x00 0x59 0x0d 0x00 0x59 0x0e 0x00 0x59 0x00 0x01 0x59 0x01 0x01 0x59 0x02 0x01 0x59 0x03 0x01 0x59 0x04 0x01 0x59 0x05 0x01 0x59 0x06 0x01 0x59 0x07 0x01 0x59 0x08 0x01 0x59 0x09 0x01 0x59 0x0a 0x01 0x59 0x0b 0x01 0x59 0x0c 0x01 0x59 0x0d 0x01 0x59 0x0e 0x01>;
+ dma-names = "rx1\0rx2\0rx3\0rx4\0rx5\0rx6\0rx7\0rx8\0rx9\0rx10\0rx11\0rx12\0rx13\0rx14\0rx15\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0tx8\0tx9\0tx10\0tx11\0tx12\0tx13\0tx14\0tx15";
+ interrupts-extended = <0x01 0x12 0x5a 0x00>;
+ phandle = <0xeb>;
+ };
+
+ usb-phy@1b00 {
+ compatible = "ti,am335x-usb-phy";
+ reg = <0x1b00 0x100>;
+ reg-names = "phy";
+ ti,ctrl_mod = <0x57>;
+ #phy-cells = <0x00>;
+ phandle = <0x5b>;
+ };
+
+ usb@1800 {
+ compatible = "ti,musb-am33xx";
+ reg = <0x1c00 0x400 0x1800 0x200>;
+ reg-names = "mc\0control";
+ interrupts = <0x13>;
+ interrupt-names = "mc";
+ dr_mode = "host";
+ mentor,multipoint = <0x01>;
+ mentor,num-eps = <0x10>;
+ mentor,ram-bits = <0x0c>;
+ mentor,power = <0x1f4>;
+ phys = <0x5b>;
+ dmas = <0x59 0x0f 0x00 0x59 0x10 0x00 0x59 0x11 0x00 0x59 0x12 0x00 0x59 0x13 0x00 0x59 0x14 0x00 0x59 0x15 0x00 0x59 0x16 0x00 0x59 0x17 0x00 0x59 0x18 0x00 0x59 0x19 0x00 0x59 0x1a 0x00 0x59 0x1b 0x00 0x59 0x1c 0x00 0x59 0x1d 0x00 0x59 0x0f 0x01 0x59 0x10 0x01 0x59 0x11 0x01 0x59 0x12 0x01 0x59 0x13 0x01 0x59 0x14 0x01 0x59 0x15 0x01 0x59 0x16 0x01 0x59 0x17 0x01 0x59 0x18 0x01 0x59 0x19 0x01 0x59 0x1a 0x01 0x59 0x1b 0x01 0x59 0x1c 0x01 0x59 0x1d 0x01>;
+ dma-names = "rx1\0rx2\0rx3\0rx4\0rx5\0rx6\0rx7\0rx8\0rx9\0rx10\0rx11\0rx12\0rx13\0rx14\0rx15\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0tx8\0tx9\0tx10\0tx11\0tx12\0tx13\0tx14\0tx15";
+ phandle = <0xec>;
+ };
+
+ dma-controller@2000 {
+ compatible = "ti,am3359-cppi41";
+ reg = <0x00 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0x4000>;
+ reg-names = "glue\0controller\0scheduler\0queuemgr";
+ interrupts = <0x11>;
+ interrupt-names = "glue";
+ #dma-cells = <0x02>;
+ #dma-channels = <0x1e>;
+ dma-channels = <0x1e>;
+ #dma-requests = <0x100>;
+ dma-requests = <0x100>;
+ phandle = <0x59>;
+ };
+ };
+
+ target-module@40300000 {
+ compatible = "ti,sysc-omap4-simple\0ti,sysc";
+ clocks = <0x07 0x08 0x00>;
+ clock-names = "fck";
+ ti,no-idle;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x40300000 0x10000>;
+
+ sram@0 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x10000>;
+ ranges = <0x00 0x00 0x10000>;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ phandle = <0xed>;
+
+ pm-code-sram@0 {
+ compatible = "ti,sram";
+ reg = <0x00 0x1000>;
+ protect-exec;
+ phandle = <0x41>;
+ };
+
+ pm-data-sram@1000 {
+ compatible = "ti,sram";
+ reg = <0x1000 0x1000>;
+ pool;
+ phandle = <0x42>;
+ };
+ };
+ };
+
+ target-module@4c000000 {
+ compatible = "ti,sysc-omap4-simple\0ti,sysc";
+ reg = <0x4c000000 0x04>;
+ reg-names = "rev";
+ clocks = <0x07 0x04 0x00>;
+ clock-names = "fck";
+ ti,no-idle;
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x4c000000 0x1000000>;
+
+ emif@0 {
+ compatible = "ti,emif-am3352";
+ reg = <0x00 0x1000000>;
+ interrupts = <0x65>;
+ sram = <0x41 0x42>;
+ phandle = <0xee>;
+ };
+ };
+
+ target-module@50000000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x50000000 0x04 0x50000010 0x04 0x50000014 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x35 0x14 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x50000000 0x50000000 0x1000 0x00 0x00 0x40000000>;
+
+ gpmc@50000000 {
+ compatible = "ti,am3352-gpmc";
+ reg = <0x50000000 0x2000>;
+ interrupts = <0x64>;
+ dmas = <0x24 0x34 0x00>;
+ dma-names = "rxtx";
+ gpmc,num-cs = <0x07>;
+ gpmc,num-waitpins = <0x02>;
+ #address-cells = <0x02>;
+ #size-cells = <0x01>;
+ interrupt-controller;
+ #interrupt-cells = <0x02>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ status = "disabled";
+ phandle = <0xef>;
+ };
+ };
+
+ target-module@53100000 {
+ compatible = "ti,sysc-omap3-sham\0ti,sysc";
+ reg = <0x53100100 0x04 0x53100110 0x04 0x53100114 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x03>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x07 0x7c 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x53100000 0x1000>;
+ phandle = <0xf0>;
+
+ sham@0 {
+ compatible = "ti,omap4-sham";
+ reg = <0x00 0x200>;
+ interrupts = <0x6d>;
+ dmas = <0x24 0x24 0x00>;
+ dma-names = "rx";
+ status = "okay";
+ phandle = <0xf1>;
+ };
+ };
+
+ target-module@53500000 {
+ compatible = "ti,sysc-omap2\0ti,sysc";
+ reg = <0x53500080 0x04 0x53500084 0x04 0x53500088 0x04>;
+ reg-names = "rev\0sysc\0syss";
+ ti,sysc-mask = <0x03>;
+ ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
+ ti,syss-mask = <0x01>;
+ clocks = <0x07 0x70 0x00>;
+ clock-names = "fck";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x53500000 0x1000>;
+ phandle = <0xf2>;
+
+ aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0x00 0xa0>;
+ interrupts = <0x67>;
+ dmas = <0x24 0x06 0x00 0x24 0x05 0x00>;
+ dma-names = "tx\0rx";
+ status = "okay";
+ phandle = <0xf3>;
+ };
+ };
+
+ target-module@56000000 {
+ compatible = "ti,sysc-omap4\0ti,sysc";
+ reg = <0x5600fe00 0x04 0x5600fe10 0x04>;
+ reg-names = "rev\0sysc";
+ ti,sysc-midle = <0x00 0x01 0x02>;
+ ti,sysc-sidle = <0x00 0x01 0x02>;
+ clocks = <0x5c 0x04 0x00>;
+ clock-names = "fck";
+ power-domains = <0x5d>;
+ resets = <0x5d 0x00>;
+ reset-names = "rstctrl";
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ ranges = <0x00 0x56000000 0x1000000>;
+
+ gpu@0 {
+ compatible = "ti,omap3630-gpu\0img,powervr-sgx530";
+ reg = <0x00 0x10000>;
+ interrupts = <0x25>;
+ };
+ };
+ };
+
+ not_available {
+ phandle = <0xf4>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <0x5e>;
+ compatible = "gpio-leds";
+
+ led2 {
+ label = "beaglebone:green:usr0";
+ gpios = <0x51 0x15 0x00>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "beaglebone:green:usr1";
+ gpios = <0x51 0x16 0x00>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "beaglebone:green:usr2";
+ gpios = <0x51 0x17 0x00>;
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+
+ led5 {
+ label = "beaglebone:green:usr3";
+ gpios = <0x51 0x18 0x00>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+ };
+
+ fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <0x325aa0>;
+ regulator-max-microvolt = <0x325aa0>;
+ phandle = <0x39>;
+ };
+
+ __symbols__ {
+ mpu_gate = "/cpus/idle-states/mpu_gate";
+ cpu0_opp_table = "/opp-table";
+ ocp = "/ocp";
+ l4_wkup = "/ocp/interconnect@44c00000";
+ wkup_m3 = "/ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0";
+ prcm = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0";
+ prcm_clocks = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks";
+ clk_32768_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768";
+ clk_rc32k_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k";
+ virt_19200000_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000";
+ virt_24000000_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000";
+ virt_25000000_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000";
+ virt_26000000_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000";
+ tclkin_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin";
+ dpll_core_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490";
+ dpll_core_x2_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2";
+ dpll_core_m4_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480";
+ dpll_core_m5_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484";
+ dpll_core_m6_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8";
+ dpll_mpu_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488";
+ dpll_mpu_m2_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8";
+ dpll_ddr_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494";
+ dpll_ddr_m2_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0";
+ dpll_ddr_m2_div2_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2";
+ dpll_disp_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498";
+ dpll_disp_m2_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4";
+ dpll_per_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c";
+ dpll_per_m2_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac";
+ dpll_per_m2_div4_wkupdm_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm";
+ dpll_per_m2_div4_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4";
+ clk_24mhz = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz";
+ clkdiv32k_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k";
+ l3_gclk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk";
+ pruss_ocp_gclk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530";
+ mmu_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914";
+ timer1_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528";
+ timer2_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508";
+ timer3_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c";
+ timer4_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510";
+ timer5_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518";
+ timer6_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c";
+ timer7_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504";
+ usbotg_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c";
+ dpll_core_m4_div2_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2";
+ ieee5000_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4";
+ wdt1_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538";
+ l4_rtc_gclk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk";
+ l4hs_gclk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk";
+ l3s_gclk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk";
+ l4fw_gclk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk";
+ l4ls_gclk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk";
+ sysclk_div_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div";
+ cpsw_125mhz_gclk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk";
+ cpsw_cpts_rft_clk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520";
+ gpio0_dbclk_mux_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c";
+ lcd_gclk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534";
+ mmc_clk = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc";
+ gfx_fclk_clksel_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel";
+ gfx_fck_div_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div";
+ sysclkout_pre_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre";
+ clkout2_div_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div";
+ clkout2_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2";
+ prcm_clockdomains = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clockdomains";
+ per_cm = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0";
+ l4ls_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38";
+ l3s_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c";
+ l3_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24";
+ l4hs_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120";
+ pruss_ocp_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8";
+ cpsw_125mhz_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0";
+ lcdc_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18";
+ clk_24mhz_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c";
+ wkup_cm = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400";
+ l4_wkup_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0";
+ l3_aon_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14";
+ l4_wkup_aon_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0";
+ mpu_cm = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600";
+ mpu_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0";
+ l4_rtc_cm = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800";
+ l4_rtc_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0";
+ gfx_l3_cm = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900";
+ gfx_l3_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0";
+ l4_cefuse_cm = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00";
+ l4_cefuse_clkctrl = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0";
+ prm_per = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00";
+ prm_wkup = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00";
+ prm_mpu = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00";
+ prm_device = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00";
+ prm_rtc = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000";
+ prm_gfx = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100";
+ prm_cefuse = "/ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200";
+ gpio0_target = "/ocp/interconnect@44c00000/segment@200000/target-module@7000";
+ gpio0 = "/ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0";
+ uart0 = "/ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0";
+ i2c0 = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0";
+ tps = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24";
+ dcdc1_reg = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/regulators/regulator@0";
+ dcdc2_reg = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/regulators/regulator@1";
+ dcdc3_reg = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/regulators/regulator@2";
+ ldo1_reg = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/regulators/regulator@3";
+ ldo2_reg = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/regulators/regulator@4";
+ ldo3_reg = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/regulators/regulator@5";
+ ldo4_reg = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/regulators/regulator@6";
+ baseboard_eeprom = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50";
+ baseboard_data = "/ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/baseboard_data@0";
+ bone_adc = "/ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0";
+ tscadc = "/ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0";
+ am335x_adc = "/ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc";
+ scm = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0";
+ bone_pinmux = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800";
+ am33xx_pinmux = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800";
+ bborg_comms_can_pins = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/pinmux_comms_can_pins";
+ bborg_comms_rs485_pins = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/pinmux_comms_rs485_pins";
+ user_leds_s0 = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/user-leds-s0-pins";
+ i2c0_pins = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/i2c0-pins";
+ i2c2_pins = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/i2c2-pins";
+ uart0_pins = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/uart0-pins";
+ cpsw_default = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/cpsw-default-pins";
+ cpsw_sleep = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/cpsw-sleep-pins";
+ davinci_mdio_default = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/davinci-mdio-default-pins";
+ davinci_mdio_sleep = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/davinci-mdio-sleep-pins";
+ mmc1_pins = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/mmc1-pins";
+ emmc_pins = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/emmc-pins";
+ scm_conf = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0";
+ phy_gmii_sel = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel";
+ scm_clocks = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks";
+ sys_clkin_ck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40";
+ adc_tsc_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck";
+ dcan0_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck";
+ dcan1_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck";
+ mcasp0_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck";
+ mcasp1_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck";
+ smartreflex0_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck";
+ smartreflex1_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck";
+ sha0_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck";
+ aes0_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck";
+ rng_fck = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck";
+ ehrpwm0_tbclk = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk";
+ ehrpwm1_tbclk = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk";
+ ehrpwm2_tbclk = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk";
+ usb_ctrl_mod = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620";
+ wkup_m3_ipc = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324";
+ edma_xbar = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90";
+ scm_clockdomains = "/ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/clockdomains";
+ timer1_target = "/ocp/interconnect@44c00000/segment@200000/target-module@31000";
+ timer1 = "/ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0";
+ wdt2 = "/ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0";
+ rtc = "/ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0";
+ l4_per = "/ocp/interconnect@48000000";
+ uart1 = "/ocp/interconnect@48000000/segment@0/target-module@22000/serial@0";
+ uart2 = "/ocp/interconnect@48000000/segment@0/target-module@24000/serial@0";
+ i2c1 = "/ocp/interconnect@48000000/segment@0/target-module@2a000/i2c@0";
+ spi0 = "/ocp/interconnect@48000000/segment@0/target-module@30000/spi@0";
+ mcasp0 = "/ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0";
+ mcasp1 = "/ocp/interconnect@48000000/segment@0/target-module@3c000/mcasp@0";
+ timer2_target = "/ocp/interconnect@48000000/segment@0/target-module@40000";
+ timer2 = "/ocp/interconnect@48000000/segment@0/target-module@40000/timer@0";
+ timer3 = "/ocp/interconnect@48000000/segment@0/target-module@42000/timer@0";
+ timer4 = "/ocp/interconnect@48000000/segment@0/target-module@44000/timer@0";
+ timer5 = "/ocp/interconnect@48000000/segment@0/target-module@46000/timer@0";
+ timer6 = "/ocp/interconnect@48000000/segment@0/target-module@48000/timer@0";
+ timer7 = "/ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0";
+ gpio1 = "/ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0";
+ mmc1 = "/ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0";
+ elm = "/ocp/interconnect@48000000/segment@0/target-module@80000/elm@0";
+ mailbox = "/ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0";
+ mbox_wkupm3 = "/ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0/mbox-wkup-m3";
+ hwspinlock = "/ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0";
+ i2c2 = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0";
+ cape_eeprom0 = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54";
+ cape0_data = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/cape_data@0";
+ cape_eeprom1 = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55";
+ cape1_data = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/cape_data@0";
+ cape_eeprom2 = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56";
+ cape2_data = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/cape_data@0";
+ cape_eeprom3 = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57";
+ cape3_data = "/ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/cape_data@0";
+ spi1 = "/ocp/interconnect@48000000/segment@100000/target-module@a0000/spi@0";
+ uart3 = "/ocp/interconnect@48000000/segment@100000/target-module@a6000/serial@0";
+ bone_uart_4 = "/ocp/interconnect@48000000/segment@100000/target-module@a8000/serial@0";
+ uart4 = "/ocp/interconnect@48000000/segment@100000/target-module@a8000/serial@0";
+ uart5 = "/ocp/interconnect@48000000/segment@100000/target-module@aa000/serial@0";
+ gpio2 = "/ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0";
+ gpio3_target = "/ocp/interconnect@48000000/segment@100000/target-module@ae000";
+ gpio3 = "/ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0";
+ dcan0 = "/ocp/interconnect@48000000/segment@100000/target-module@cc000/can@0";
+ bone_can_1 = "/ocp/interconnect@48000000/segment@100000/target-module@d0000/can@0";
+ dcan1 = "/ocp/interconnect@48000000/segment@100000/target-module@d0000/can@0";
+ mmc2 = "/ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0";
+ epwmss0 = "/ocp/interconnect@48000000/segment@300000/target-module@0/epwmss@0";
+ ecap0 = "/ocp/interconnect@48000000/segment@300000/target-module@0/epwmss@0/pwm@100";
+ eqep0 = "/ocp/interconnect@48000000/segment@300000/target-module@0/epwmss@0/counter@180";
+ ehrpwm0 = "/ocp/interconnect@48000000/segment@300000/target-module@0/epwmss@0/pwm@200";
+ epwmss1 = "/ocp/interconnect@48000000/segment@300000/target-module@2000/epwmss@0";
+ ecap1 = "/ocp/interconnect@48000000/segment@300000/target-module@2000/epwmss@0/pwm@100";
+ eqep1 = "/ocp/interconnect@48000000/segment@300000/target-module@2000/epwmss@0/counter@180";
+ ehrpwm1 = "/ocp/interconnect@48000000/segment@300000/target-module@2000/epwmss@0/pwm@200";
+ epwmss2 = "/ocp/interconnect@48000000/segment@300000/target-module@4000/epwmss@0";
+ ecap2 = "/ocp/interconnect@48000000/segment@300000/target-module@4000/epwmss@0/pwm@100";
+ eqep2 = "/ocp/interconnect@48000000/segment@300000/target-module@4000/epwmss@0/counter@180";
+ ehrpwm2 = "/ocp/interconnect@48000000/segment@300000/target-module@4000/epwmss@0/pwm@200";
+ lcdc = "/ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0";
+ rng = "/ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0";
+ l4_fw = "/ocp/interconnect@47c00000";
+ l4_fast = "/ocp/interconnect@4a000000";
+ mac = "/ocp/interconnect@4a000000/segment@0/target-module@100000/ethernet@0";
+ davinci_mdio = "/ocp/interconnect@4a000000/segment@0/target-module@100000/ethernet@0/mdio@1000";
+ cpsw_emac0 = "/ocp/interconnect@4a000000/segment@0/target-module@100000/ethernet@0/slave@200";
+ cpsw_emac1 = "/ocp/interconnect@4a000000/segment@0/target-module@100000/ethernet@0/slave@300";
+ mac_sw = "/ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0";
+ cpsw_port1 = "/ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/ethernet-ports/port@1";
+ cpsw_port2 = "/ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/ethernet-ports/port@2";
+ davinci_mdio_sw = "/ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000";
+ ethphy0 = "/ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000/ethernet-phy@0";
+ pruss_tm = "/ocp/interconnect@4a000000/segment@0/target-module@300000";
+ pruss = "/ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0";
+ pruss_mem = "/ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/memories@0";
+ pruss_cfg = "/ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000";
+ pruss_iepclk_mux = "/ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000/clocks/iepclk-mux@30";
+ pruss_mii_rt = "/ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000";
+ pruss_intc = "/ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000";
+ pru0 = "/ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000";
+ pru1 = "/ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000";
+ pruss_mdio = "/ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mdio@32400";
+ l4_mpuss = "/ocp/interconnect@4b140000";
+ intc = "/ocp/interrupt-controller@48200000";
+ edma = "/ocp/target-module@49000000/dma@0";
+ edma_tptc0 = "/ocp/target-module@49800000/dma@0";
+ edma_tptc1 = "/ocp/target-module@49900000/dma@0";
+ edma_tptc2 = "/ocp/target-module@49a00000/dma@0";
+ mmc3 = "/ocp/target-module@47810000/mmc@0";
+ usb = "/ocp/target-module@47400000";
+ usb0_phy = "/ocp/target-module@47400000/usb-phy@1300";
+ usb0 = "/ocp/target-module@47400000/usb@1400";
+ usb1_phy = "/ocp/target-module@47400000/usb-phy@1b00";
+ usb1 = "/ocp/target-module@47400000/usb@1800";
+ cppi41dma = "/ocp/target-module@47400000/dma-controller@2000";
+ ocmcram = "/ocp/target-module@40300000/sram@0";
+ pm_sram_code = "/ocp/target-module@40300000/sram@0/pm-code-sram@0";
+ pm_sram_data = "/ocp/target-module@40300000/sram@0/pm-data-sram@1000";
+ emif = "/ocp/target-module@4c000000/emif@0";
+ gpmc = "/ocp/target-module@50000000/gpmc@50000000";
+ sham_target = "/ocp/target-module@53100000";
+ sham = "/ocp/target-module@53100000/sham@0";
+ aes_target = "/ocp/target-module@53500000";
+ aes = "/ocp/target-module@53500000/aes@0";
+ not_available = "/not_available";
+ vmmcsd_fixed = "/fixedregulator0";
+ };
+};