aboutsummaryrefslogtreecommitdiff
path: root/src/ARMInterpreter_LoadStore.h
blob: 80f33b2c201798adbcccdbbfce33914ef1f97f0f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
/*
    Copyright 2016-2021 Arisotura

    This file is part of melonDS.

    melonDS is free software: you can redistribute it and/or modify it under
    the terms of the GNU General Public License as published by the Free
    Software Foundation, either version 3 of the License, or (at your option)
    any later version.

    melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
    FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

    You should have received a copy of the GNU General Public License along
    with melonDS. If not, see http://www.gnu.org/licenses/.
*/

#ifndef ARMINTERPRETER_LOADSTORE_H
#define ARMINTERPRETER_LOADSTORE_H

namespace ARMInterpreter
{

#define A_PROTO_WB_LDRSTR(x) \
\
void A_##x##_IMM(ARM* cpu); \
void A_##x##_REG_LSL(ARM* cpu); \
void A_##x##_REG_LSR(ARM* cpu); \
void A_##x##_REG_ASR(ARM* cpu); \
void A_##x##_REG_ROR(ARM* cpu); \
void A_##x##_POST_IMM(ARM* cpu); \
void A_##x##_POST_REG_LSL(ARM* cpu); \
void A_##x##_POST_REG_LSR(ARM* cpu); \
void A_##x##_POST_REG_ASR(ARM* cpu); \
void A_##x##_POST_REG_ROR(ARM* cpu);

A_PROTO_WB_LDRSTR(STR)
A_PROTO_WB_LDRSTR(STRB)
A_PROTO_WB_LDRSTR(LDR)
A_PROTO_WB_LDRSTR(LDRB)

#define A_PROTO_HD_LDRSTR(x) \
\
void A_##x##_IMM(ARM* cpu); \
void A_##x##_REG(ARM* cpu); \
void A_##x##_POST_IMM(ARM* cpu); \
void A_##x##_POST_REG(ARM* cpu);

A_PROTO_HD_LDRSTR(STRH)
A_PROTO_HD_LDRSTR(LDRD)
A_PROTO_HD_LDRSTR(STRD)
A_PROTO_HD_LDRSTR(LDRH)
A_PROTO_HD_LDRSTR(LDRSB)
A_PROTO_HD_LDRSTR(LDRSH)

void A_LDM(ARM* cpu);
void A_STM(ARM* cpu);

void A_SWP(ARM* cpu);
void A_SWPB(ARM* cpu);


void T_LDR_PCREL(ARM* cpu);

void T_STR_REG(ARM* cpu);
void T_STRB_REG(ARM* cpu);
void T_LDR_REG(ARM* cpu);
void T_LDRB_REG(ARM* cpu);

void T_STRH_REG(ARM* cpu);
void T_LDRSB_REG(ARM* cpu);
void T_LDRH_REG(ARM* cpu);
void T_LDRSH_REG(ARM* cpu);

void T_STR_IMM(ARM* cpu);
void T_LDR_IMM(ARM* cpu);
void T_STRB_IMM(ARM* cpu);
void T_LDRB_IMM(ARM* cpu);

void T_STRH_IMM(ARM* cpu);
void T_LDRH_IMM(ARM* cpu);

void T_STR_SPREL(ARM* cpu);
void T_LDR_SPREL(ARM* cpu);

void T_PUSH(ARM* cpu);
void T_POP(ARM* cpu);
void T_STMIA(ARM* cpu);
void T_LDMIA(ARM* cpu);

}

#endif