From eb13bce6e7300ffb71f76dec11ce422e05154c28 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Thu, 2 Nov 2023 12:21:59 +0100 Subject: RTC: add the DSi alarm expansion registers --- src/RTC.cpp | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src') diff --git a/src/RTC.cpp b/src/RTC.cpp index ff40322..3d25226 100644 --- a/src/RTC.cpp +++ b/src/RTC.cpp @@ -324,6 +324,16 @@ void ProcessIRQ(int type) // 0=minute carry 1=periodic 2=status reg write if (State.Alarm1[2] & (1<<7)) cond = cond && ((State.Alarm1[2] & 0x7F) == State.DateTime[5]); + if (NDS::ConsoleType == 1) + { + if (State.AlarmDate1[1] & (1<<6)) + cond = cond && (State.AlarmDate1[0] == State.DateTime[0]); + if (State.AlarmDate1[1] & (1<<7)) + cond = cond && ((State.AlarmDate1[1] & 0x1F) == State.DateTime[1]); + if (State.AlarmDate1[2] & (1<<7)) + cond = cond && ((State.AlarmDate1[2] & 0x3F) == State.DateTime[2]); + } + if (cond) SetIRQ(0x10); else @@ -356,6 +366,16 @@ void ProcessIRQ(int type) // 0=minute carry 1=periodic 2=status reg write if (State.Alarm2[2] & (1<<7)) cond = cond && ((State.Alarm2[2] & 0x7F) == State.DateTime[5]); + if (NDS::ConsoleType == 1) + { + if (State.AlarmDate2[1] & (1<<6)) + cond = cond && (State.AlarmDate2[0] == State.DateTime[0]); + if (State.AlarmDate2[1] & (1<<7)) + cond = cond && ((State.AlarmDate2[1] & 0x1F) == State.DateTime[1]); + if (State.AlarmDate2[2] & (1<<7)) + cond = cond && ((State.AlarmDate2[2] & 0x3F) == State.DateTime[2]); + } + if (cond) SetIRQ(0x20); else -- cgit v1.2.3