From b76e5adc1dff673dfbe19a2835ee359abfcd9836 Mon Sep 17 00:00:00 2001
From: Arisotura <thetotalworm@gmail.com>
Date: Mon, 10 Oct 2022 00:22:46 +0200
Subject: unfuck the DSP code some

(still doesn't work)
---
 src/DSi.cpp     | 38 ++++++++++++++++++++++++++++----------
 src/DSi_DSP.cpp | 14 --------------
 2 files changed, 28 insertions(+), 24 deletions(-)

(limited to 'src')

diff --git a/src/DSi.cpp b/src/DSi.cpp
index cfce0ac..12cd954 100644
--- a/src/DSi.cpp
+++ b/src/DSi.cpp
@@ -2241,8 +2241,11 @@ u8 ARM9IORead8(u32 addr)
         return DSi_CamModule::Read8(addr);
     }
 
-    if (addr >= 0x04004300 && addr <= 0x04004400)
-        return DSi_DSP::Read16(addr);
+    if ((addr & 0xFFFFFF00) == 0x04004300)
+    {
+        if (!(SCFG_EXT[0] & (1<<18))) return 0;
+        return DSi_DSP::Read8(addr);
+    }
 
     return NDS::ARM9IORead8(addr);
 }
@@ -2273,8 +2276,11 @@ u16 ARM9IORead16(u32 addr)
         return DSi_CamModule::Read16(addr);
     }
 
-    if (addr >= 0x04004300 && addr <= 0x04004400)
-        return DSi_DSP::Read32(addr);
+    if ((addr & 0xFFFFFF00) == 0x04004300)
+    {
+        if (!(SCFG_EXT[0] & (1<<18))) return 0;
+        return DSi_DSP::Read16(addr);
+    }
 
     return NDS::ARM9IORead16(addr);
 }
@@ -2335,6 +2341,12 @@ u32 ARM9IORead32(u32 addr)
         return DSi_CamModule::Read32(addr);
     }
 
+    if ((addr & 0xFFFFFF00) == 0x04004300)
+    {
+        if (!(SCFG_EXT[0] & (1<<18))) return 0;
+        return DSi_DSP::Read32(addr);
+    }
+
     return NDS::ARM9IORead32(addr);
 }
 
@@ -2399,10 +2411,10 @@ void ARM9IOWrite8(u32 addr, u8 val)
         return DSi_CamModule::Write8(addr, val);
     }
 
-    if (addr >= 0x04004300 && addr <= 0x04004400)
+    if ((addr & 0xFFFFFF00) == 0x04004300)
     {
-        DSi_DSP::Write8(addr, val);
-        return;
+        if (!(SCFG_EXT[0] & (1<<18))) return;
+        return DSi_DSP::Write8(addr, val);
     }
 
     return NDS::ARM9IOWrite8(addr, val);
@@ -2459,10 +2471,10 @@ void ARM9IOWrite16(u32 addr, u16 val)
         return DSi_CamModule::Write16(addr, val);
     }
 
-    if (addr >= 0x04004300 && addr <= 0x04004400)
+    if ((addr & 0xFFFFFF00) == 0x04004300)
     {
-        DSi_DSP::Write16(addr, val);
-        return;
+        if (!(SCFG_EXT[0] & (1<<18))) return;
+        return DSi_DSP::Write16(addr, val);
     }
 
     return NDS::ARM9IOWrite16(addr, val);
@@ -2609,6 +2621,12 @@ void ARM9IOWrite32(u32 addr, u32 val)
         return DSi_CamModule::Write32(addr, val);
     }
 
+    if ((addr & 0xFFFFFF00) == 0x04004300)
+    {
+        if (!(SCFG_EXT[0] & (1<<18))) return;
+        return DSi_DSP::Write32(addr, val);
+    }
+
     return NDS::ARM9IOWrite32(addr, val);
 }
 
diff --git a/src/DSi_DSP.cpp b/src/DSi_DSP.cpp
index 0525366..711166c 100644
--- a/src/DSi_DSP.cpp
+++ b/src/DSi_DSP.cpp
@@ -390,9 +390,6 @@ u16 PDataDMAReadMMIO()
 
 u8 Read8(u32 addr)
 {
-    if (!(DSi::SCFG_EXT[0] & (1<<18)))
-        return 0;
-
     if (!DSPCatchUp()) return 0;
 
     addr &= 0x3F; // mirroring wheee
@@ -419,9 +416,6 @@ u8 Read8(u32 addr)
 }
 u16 Read16(u32 addr)
 {
-    if (!(DSi::SCFG_EXT[0] & (1<<18)))
-        return 0;
-
     if (!DSPCatchUp()) return 0;
 
     addr &= 0x3E; // mirroring wheee
@@ -463,8 +457,6 @@ u16 Read16(u32 addr)
 }
 u32 Read32(u32 addr)
 {
-    if (!(DSi::SCFG_EXT[0] & (1<<18))) return 0;
-
     addr &= 0x3C;
     return Read16(addr); // *shrug* (doesn't do anything unintended due to the
                          // 4byte spacing between regs while they're all 16bit)
@@ -472,8 +464,6 @@ u32 Read32(u32 addr)
 
 void Write8(u32 addr, u8 val)
 {
-    if (!(DSi::SCFG_EXT[0] & (1<<18))) return;
-
     if (!DSPCatchUp()) return;
 
     addr &= 0x3F;
@@ -494,8 +484,6 @@ void Write8(u32 addr, u8 val)
 }
 void Write16(u32 addr, u16 val)
 {
-    if (!(DSi::SCFG_EXT[0] & (1<<18))) return;
-
     if (!DSPCatchUp()) return;
 
     addr &= 0x3E;
@@ -547,8 +535,6 @@ void Write16(u32 addr, u16 val)
 
 void Write32(u32 addr, u32 val)
 {
-    if (!(DSi::SCFG_EXT[0] & (1<<18))) return;
-
     addr &= 0x3C;
     Write16(addr, val & 0xFFFF);
 }
-- 
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