From 0e421ccebd3ebabfbbabcae96acc262b76198ad2 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Thu, 13 Jun 2019 14:41:54 +0200 Subject: add all sorts of shit --- src/NDS.cpp | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/NDS.cpp b/src/NDS.cpp index ea34103..f00665e 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -31,6 +31,8 @@ #include "Wifi.h" #include "Platform.h" +#include "DSi.h" + namespace NDS { @@ -83,8 +85,8 @@ u32 SchedListMask; u32 CPUStop; -u8 ARM9BIOS[0x1000]; -u8 ARM7BIOS[0x4000]; +u8 ARM9BIOS[0x10000]; +u8 ARM7BIOS[0x10000]; u8 MainRAM[MAIN_RAM_SIZE]; @@ -387,6 +389,9 @@ void Reset() LastSysClockCycles = 0; + memset(ARM9BIOS, 0, 0x10000); + memset(ARM7BIOS, 0, 0x10000); + f = Platform::OpenLocalFile("bios9.bin", "rb"); if (!f) { @@ -421,6 +426,8 @@ void Reset() fclose(f); } + DSi::LoadNAND(); + // TODO for later: configure this when emulating a DSi ARM9ClockShift = 1; @@ -1566,9 +1573,9 @@ void debug(u32 param) u8 ARM9Read8(u32 addr) { - if ((addr & 0xFFFFF000) == 0xFFFF0000) + if ((addr & 0xFFFF0000) == 0xFFFF0000) { - return *(u8*)&ARM9BIOS[addr & 0xFFF]; + return *(u8*)&ARM9BIOS[addr & 0xFFFF]; } switch (addr & 0xFF000000) @@ -1627,9 +1634,9 @@ u8 ARM9Read8(u32 addr) u16 ARM9Read16(u32 addr) { - if ((addr & 0xFFFFF000) == 0xFFFF0000) + if ((addr & 0xFFFF0000) == 0xFFFF0000) { - return *(u16*)&ARM9BIOS[addr & 0xFFF]; + return *(u16*)&ARM9BIOS[addr & 0xFFFF]; } switch (addr & 0xFF000000) @@ -1688,9 +1695,9 @@ u16 ARM9Read16(u32 addr) u32 ARM9Read32(u32 addr) { - if ((addr & 0xFFFFF000) == 0xFFFF0000) + if ((addr & 0xFFFF0000) == 0xFFFF0000) { - return *(u32*)&ARM9BIOS[addr & 0xFFF]; + return *(u32*)&ARM9BIOS[addr & 0xFFFF]; } switch (addr & 0xFF000000) @@ -1896,9 +1903,10 @@ bool ARM9GetMemRegion(u32 addr, bool write, MemRegion* region) u8 ARM7Read8(u32 addr) { - if (addr < 0x00004000) + if (addr < 0x00010000) { - if (ARM7->R[15] >= 0x4000) + // TODO: check the boundary? is it 4000 or higher on regular DS? + if (ARM7->R[15] >= 0x00010000) return 0xFF; if (addr < ARM7BIOSProt && ARM7->R[15] >= ARM7BIOSProt) return 0xFF; @@ -1952,9 +1960,9 @@ u8 ARM7Read8(u32 addr) u16 ARM7Read16(u32 addr) { - if (addr < 0x00004000) + if (addr < 0x00010000) { - if (ARM7->R[15] >= 0x4000) + if (ARM7->R[15] >= 0x00010000) return 0xFFFF; if (addr < ARM7BIOSProt && ARM7->R[15] >= ARM7BIOSProt) return 0xFFFF; @@ -2015,9 +2023,9 @@ u16 ARM7Read16(u32 addr) u32 ARM7Read32(u32 addr) { - if (addr < 0x00004000) + if (addr < 0x00010000) { - if (ARM7->R[15] >= 0x4000) + if (ARM7->R[15] >= 0x00010000) return 0xFFFFFFFF; if (addr < ARM7BIOSProt && ARM7->R[15] >= ARM7BIOSProt) return 0xFFFFFFFF; -- cgit v1.2.3 From 83d23939db58a3d59d97e26c7dc3cfd9ea7927d9 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Sat, 15 Jun 2019 13:09:11 +0200 Subject: melonDSi: skeleton in place --- src/ARM.h | 31 +++-- src/CP15.cpp | 31 +++-- src/DSi.cpp | 393 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- src/DSi.h | 33 +++++ src/NDS.cpp | 65 +++++----- src/sha1/sha1.c | 17 +-- src/sha1/sha1.h | 10 +- 7 files changed, 518 insertions(+), 62 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/ARM.h b/src/ARM.h index d13d535..6b6e330 100644 --- a/src/ARM.h +++ b/src/ARM.h @@ -23,6 +23,7 @@ #include "types.h" #include "NDS.h" +#include "DSi.h" #define ROR(x, n) (((x) >> (n)) | ((x) << (32-(n)))) @@ -271,17 +272,20 @@ public: u16 CodeRead16(u32 addr) { - return NDS::ARM7Read16(addr); + //return NDS::ARM7Read16(addr); + return DSi::ARM7Read16(addr); } u32 CodeRead32(u32 addr) { - return NDS::ARM7Read32(addr); + //return NDS::ARM7Read32(addr); + return DSi::ARM7Read32(addr); } void DataRead8(u32 addr, u32* val) { - *val = NDS::ARM7Read8(addr); + *val = DSi::ARM7Read8(addr); + //*val = NDS::ARM7Read8(addr); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][0]; } @@ -290,7 +294,8 @@ public: { addr &= ~1; - *val = NDS::ARM7Read16(addr); + *val = DSi::ARM7Read16(addr); + //*val = NDS::ARM7Read16(addr); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][0]; } @@ -299,7 +304,8 @@ public: { addr &= ~3; - *val = NDS::ARM7Read32(addr); + *val = DSi::ARM7Read32(addr); + //*val = NDS::ARM7Read32(addr); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][2]; } @@ -308,13 +314,15 @@ public: { addr &= ~3; - *val = NDS::ARM7Read32(addr); + *val = DSi::ARM7Read32(addr); + //*val = NDS::ARM7Read32(addr); DataCycles += NDS::ARM7MemTimings[DataRegion][3]; } void DataWrite8(u32 addr, u8 val) { - NDS::ARM7Write8(addr, val); + DSi::ARM7Write8(addr, val); + //NDS::ARM7Write8(addr, val); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][0]; } @@ -323,7 +331,8 @@ public: { addr &= ~1; - NDS::ARM7Write16(addr, val); + DSi::ARM7Write16(addr, val); + //NDS::ARM7Write16(addr, val); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][0]; } @@ -332,7 +341,8 @@ public: { addr &= ~3; - NDS::ARM7Write32(addr, val); + DSi::ARM7Write32(addr, val); + //NDS::ARM7Write32(addr, val); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][2]; } @@ -341,7 +351,8 @@ public: { addr &= ~3; - NDS::ARM7Write32(addr, val); + DSi::ARM7Write32(addr, val); + //NDS::ARM7Write32(addr, val); DataCycles += NDS::ARM7MemTimings[DataRegion][3]; } diff --git a/src/CP15.cpp b/src/CP15.cpp index a4db5f3..4654a2a 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -19,6 +19,7 @@ #include #include #include "NDS.h" +#include "DSi.h" #include "ARM.h" @@ -680,7 +681,8 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch) if (CodeMem.Mem) return *(u32*)&CodeMem.Mem[addr & CodeMem.Mask]; - return NDS::ARM9Read32(addr); + //return NDS::ARM9Read32(addr); + return DSi::ARM9Read32(addr); } @@ -699,7 +701,8 @@ void ARMv5::DataRead8(u32 addr, u32* val) return; } - *val = NDS::ARM9Read8(addr); + *val = DSi::ARM9Read8(addr); + //*val = NDS::ARM9Read8(addr); DataCycles = MemTimings[addr >> 12][1]; } @@ -720,7 +723,8 @@ void ARMv5::DataRead16(u32 addr, u32* val) return; } - *val = NDS::ARM9Read16(addr); + *val = DSi::ARM9Read16(addr); + //*val = NDS::ARM9Read16(addr); DataCycles = MemTimings[addr >> 12][1]; } @@ -741,7 +745,8 @@ void ARMv5::DataRead32(u32 addr, u32* val) return; } - *val = NDS::ARM9Read32(addr); + *val = DSi::ARM9Read32(addr); + //*val = NDS::ARM9Read32(addr); DataCycles = MemTimings[addr >> 12][2]; } @@ -762,7 +767,8 @@ void ARMv5::DataRead32S(u32 addr, u32* val) return; } - *val = NDS::ARM9Read32(addr); + *val = DSi::ARM9Read32(addr); + //*val = NDS::ARM9Read32(addr); DataCycles += MemTimings[addr >> 12][3]; } @@ -781,7 +787,8 @@ void ARMv5::DataWrite8(u32 addr, u8 val) return; } - NDS::ARM9Write8(addr, val); + DSi::ARM9Write8(addr, val); + //NDS::ARM9Write8(addr, val); DataCycles = MemTimings[addr >> 12][1]; } @@ -802,7 +809,8 @@ void ARMv5::DataWrite16(u32 addr, u16 val) return; } - NDS::ARM9Write16(addr, val); + DSi::ARM9Write16(addr, val); + //NDS::ARM9Write16(addr, val); DataCycles = MemTimings[addr >> 12][1]; } @@ -823,7 +831,8 @@ void ARMv5::DataWrite32(u32 addr, u32 val) return; } - NDS::ARM9Write32(addr, val); + DSi::ARM9Write32(addr, val); + //NDS::ARM9Write32(addr, val); DataCycles = MemTimings[addr >> 12][2]; } @@ -844,7 +853,8 @@ void ARMv5::DataWrite32S(u32 addr, u32 val) return; } - NDS::ARM9Write32(addr, val); + DSi::ARM9Write32(addr, val); + //NDS::ARM9Write32(addr, val); DataCycles += MemTimings[addr >> 12][3]; } @@ -857,6 +867,7 @@ void ARMv5::GetCodeMemRegion(u32 addr, NDS::MemRegion* region) return; }*/ - NDS::ARM9GetMemRegion(addr, false, &CodeMem); + DSi::ARM9GetMemRegion(addr, false, &CodeMem); + //NDS::ARM9GetMemRegion(addr, false, &CodeMem); } diff --git a/src/DSi.cpp b/src/DSi.cpp index 376e6a0..8026e49 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -16,18 +16,409 @@ with melonDS. If not, see http://www.gnu.org/licenses/. */ +#include "NDS.h" #include "DSi.h" #include "tiny-AES-c/aes.hpp" #include "sha1/sha1.h" +#include "Platform.h" + namespace DSi { +// + + +bool LoadBIOS() +{ + FILE* f; + u32 i; + + f = Platform::OpenLocalFile("bios9i.bin", "rb"); + if (!f) + { + printf("ARM9i BIOS not found\n"); + + for (i = 0; i < 16; i++) + ((u32*)NDS::ARM9BIOS)[i] = 0xE7FFDEFF; + } + else + { + fseek(f, 0, SEEK_SET); + fread(NDS::ARM9BIOS, 0x10000, 1, f); + + printf("ARM9i BIOS loaded\n"); + fclose(f); + } + + f = Platform::OpenLocalFile("bios7i.bin", "rb"); + if (!f) + { + printf("ARM7i BIOS not found\n"); + + for (i = 0; i < 16; i++) + ((u32*)NDS::ARM7BIOS)[i] = 0xE7FFDEFF; + } + else + { + // TODO: check if the first 32 bytes are crapoed + + fseek(f, 0, SEEK_SET); + fread(NDS::ARM7BIOS, 0x10000, 1, f); + + printf("ARM7i BIOS loaded\n"); + fclose(f); + } + + // herp + *(u32*)&NDS::ARM9BIOS[0] = 0xEAFFFFFE; + *(u32*)&NDS::ARM7BIOS[0] = 0xEAFFFFFE; + + return true; +} + bool LoadNAND() { - // + printf("Loading DSi NAND\n"); + + FILE* f = Platform::OpenLocalFile("nand.bin", "rb"); + if (f) + { + u32 bootparams[8]; + fseek(f, 0x220, SEEK_SET); + fread(bootparams, 4, 8, f); + + printf("ARM9: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n", + bootparams[0], bootparams[1], bootparams[2], bootparams[3]); + printf("ARM7: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n", + bootparams[4], bootparams[5], bootparams[6], bootparams[7]); + +#define printhex(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); printf("\n"); } +#define printhex_rev(str, size) { for (int z = (size)-1; z >= 0; z--) printf("%02X", (str)[z]); printf("\n"); } + + u8 emmc_cid[16]; + u8 consoleid[8]; + fseek(f, 0xF000010, SEEK_SET); + fread(emmc_cid, 1, 16, f); + fread(consoleid, 1, 8, f); + + printf("eMMC CID: "); printhex(emmc_cid, 16); + printf("Console ID: "); printhex_rev(consoleid, 8); + + fclose(f); + } return true; } + +u8 ARM9Read8(u32 addr) +{ + switch (addr & 0xFF000000) + { + case 0x04000000: + return ARM9IORead8(addr); + } + + return NDS::ARM9Read8(addr); +} + +u16 ARM9Read16(u32 addr) +{ + switch (addr & 0xFF000000) + { + case 0x04000000: + return ARM9IORead16(addr); + } + + return NDS::ARM9Read16(addr); +} + +u32 ARM9Read32(u32 addr) +{ + switch (addr & 0xFF000000) + { + case 0x04000000: + return ARM9IORead32(addr); + } + + return NDS::ARM9Read32(addr); +} + +void ARM9Write8(u32 addr, u8 val) +{ + switch (addr & 0xFF000000) + { + case 0x04000000: + ARM9IOWrite8(addr, val); + return; + } + + return NDS::ARM9Write8(addr, val); +} + +void ARM9Write16(u32 addr, u16 val) +{ + switch (addr & 0xFF000000) + { + case 0x04000000: + ARM9IOWrite16(addr, val); + return; + } + + return NDS::ARM9Write16(addr, val); +} + +void ARM9Write32(u32 addr, u32 val) +{ + switch (addr & 0xFF000000) + { + case 0x04000000: + ARM9IOWrite32(addr, val); + return; + } + + return NDS::ARM9Write32(addr, val); +} + +bool ARM9GetMemRegion(u32 addr, bool write, NDS::MemRegion* region) +{ + switch (addr & 0xFF000000) + { + case 0x02000000: + region->Mem = NDS::MainRAM; + region->Mask = MAIN_RAM_SIZE-1; + return true; + } + + if ((addr & 0xFFFF0000) == 0xFFFF0000 && !write) + { + region->Mem = NDS::ARM9BIOS; + region->Mask = 0xFFFF; + return true; + } + + region->Mem = NULL; + return false; +} + + + +u8 ARM7Read8(u32 addr) +{ + switch (addr & 0xFF800000) + { + case 0x04000000: + return ARM7IORead8(addr); + } + + return NDS::ARM7Read8(addr); +} + +u16 ARM7Read16(u32 addr) +{ + switch (addr & 0xFF800000) + { + case 0x04000000: + return ARM7IORead16(addr); + } + + return NDS::ARM7Read16(addr); +} + +u32 ARM7Read32(u32 addr) +{ + switch (addr & 0xFF800000) + { + case 0x04000000: + return ARM7IORead32(addr); + } + + return NDS::ARM7Read32(addr); +} + +void ARM7Write8(u32 addr, u8 val) +{ + switch (addr & 0xFF800000) + { + case 0x04000000: + ARM7IOWrite8(addr, val); + return; + } + + return NDS::ARM7Write8(addr, val); +} + +void ARM7Write16(u32 addr, u16 val) +{ + switch (addr & 0xFF800000) + { + case 0x04000000: + ARM7IOWrite16(addr, val); + return; + } + + return NDS::ARM7Write16(addr, val); +} + +void ARM7Write32(u32 addr, u32 val) +{ + switch (addr & 0xFF800000) + { + case 0x04000000: + ARM7IOWrite32(addr, val); + return; + } + + return NDS::ARM7Write32(addr, val); +} + +bool ARM7GetMemRegion(u32 addr, bool write, NDS::MemRegion* region) +{ + switch (addr & 0xFF800000) + { + case 0x02000000: + case 0x02800000: + region->Mem = NDS::MainRAM; + region->Mask = MAIN_RAM_SIZE-1; + return true; + } + + // BIOS. ARM7 PC has to be within range. + /*if (addr < 0x00010000 && !write) + { + if (NDS::ARM7->R[15] < 0x00010000 && (addr >= NDS::ARM7BIOSProt || NDS::ARM7->R[15] < NDS::ARM7BIOSProt)) + { + region->Mem = NDS::ARM7BIOS; + region->Mask = 0xFFFF; + return true; + } + }*/ + + region->Mem = NULL; + return false; +} + + + + +#define CASE_READ8_16BIT(addr, val) \ + case (addr): return (val) & 0xFF; \ + case (addr+1): return (val) >> 8; + +#define CASE_READ8_32BIT(addr, val) \ + case (addr): return (val) & 0xFF; \ + case (addr+1): return ((val) >> 8) & 0xFF; \ + case (addr+2): return ((val) >> 16) & 0xFF; \ + case (addr+3): return (val) >> 24; + +u8 ARM9IORead8(u32 addr) +{ + switch (addr) + { + } + + return NDS::ARM9IORead8(addr); +} + +u16 ARM9IORead16(u32 addr) +{ + switch (addr) + { + } + + return NDS::ARM9IORead16(addr); +} + +u32 ARM9IORead32(u32 addr) +{ + switch (addr) + { + } + + return NDS::ARM9IORead32(addr); +} + +void ARM9IOWrite8(u32 addr, u8 val) +{ + switch (addr) + { + } + + return NDS::ARM9IOWrite8(addr, val); +} + +void ARM9IOWrite16(u32 addr, u16 val) +{ + switch (addr) + { + } + + return NDS::ARM9IOWrite16(addr, val); +} + +void ARM9IOWrite32(u32 addr, u32 val) +{ + switch (addr) + { + } + + return NDS::ARM9IOWrite32(addr, val); +} + + +u8 ARM7IORead8(u32 addr) +{ + switch (addr) + { + } + + return NDS::ARM7IORead8(addr); +} + +u16 ARM7IORead16(u32 addr) +{ + switch (addr) + { + } + + return NDS::ARM7IORead16(addr); +} + +u32 ARM7IORead32(u32 addr) +{ + switch (addr) + { + } + + return NDS::ARM7IORead32(addr); +} + +void ARM7IOWrite8(u32 addr, u8 val) +{ + switch (addr) + { + } + + return NDS::ARM7IOWrite8(addr, val); +} + +void ARM7IOWrite16(u32 addr, u16 val) +{ + switch (addr) + { + } + + return NDS::ARM7IOWrite16(addr, val); +} + +void ARM7IOWrite32(u32 addr, u32 val) +{ + switch (addr) + { + } + + return NDS::ARM7IOWrite32(addr, val); +} + } diff --git a/src/DSi.h b/src/DSi.h index 2c71ad9..2a3ee21 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -24,8 +24,41 @@ namespace DSi { +bool LoadBIOS(); bool LoadNAND(); +u8 ARM9Read8(u32 addr); +u16 ARM9Read16(u32 addr); +u32 ARM9Read32(u32 addr); +void ARM9Write8(u32 addr, u8 val); +void ARM9Write16(u32 addr, u16 val); +void ARM9Write32(u32 addr, u32 val); + +bool ARM9GetMemRegion(u32 addr, bool write, NDS::MemRegion* region); + +u8 ARM7Read8(u32 addr); +u16 ARM7Read16(u32 addr); +u32 ARM7Read32(u32 addr); +void ARM7Write8(u32 addr, u8 val); +void ARM7Write16(u32 addr, u16 val); +void ARM7Write32(u32 addr, u32 val); + +bool ARM7GetMemRegion(u32 addr, bool write, NDS::MemRegion* region); + +u8 ARM9IORead8(u32 addr); +u16 ARM9IORead16(u32 addr); +u32 ARM9IORead32(u32 addr); +void ARM9IOWrite8(u32 addr, u8 val); +void ARM9IOWrite16(u32 addr, u16 val); +void ARM9IOWrite32(u32 addr, u32 val); + +u8 ARM7IORead8(u32 addr); +u16 ARM7IORead16(u32 addr); +u32 ARM7IORead32(u32 addr); +void ARM7IOWrite8(u32 addr, u8 val); +void ARM7IOWrite16(u32 addr, u16 val); +void ARM7IOWrite32(u32 addr, u32 val); + } #endif // DSI_H diff --git a/src/NDS.cpp b/src/NDS.cpp index f00665e..5481f6f 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -392,44 +392,51 @@ void Reset() memset(ARM9BIOS, 0, 0x10000); memset(ARM7BIOS, 0, 0x10000); - f = Platform::OpenLocalFile("bios9.bin", "rb"); - if (!f) + if (true) { - printf("ARM9 BIOS not found\n"); + DSi::LoadBIOS(); + DSi::LoadNAND(); - for (i = 0; i < 16; i++) - ((u32*)ARM9BIOS)[i] = 0xE7FFDEFF; + ARM9ClockShift = 2; } else { - fseek(f, 0, SEEK_SET); - fread(ARM9BIOS, 0x1000, 1, f); + f = Platform::OpenLocalFile("bios9.bin", "rb"); + if (!f) + { + printf("ARM9 BIOS not found\n"); - printf("ARM9 BIOS loaded\n"); - fclose(f); - } + for (i = 0; i < 16; i++) + ((u32*)ARM9BIOS)[i] = 0xE7FFDEFF; + } + else + { + fseek(f, 0, SEEK_SET); + fread(ARM9BIOS, 0x1000, 1, f); - f = Platform::OpenLocalFile("bios7.bin", "rb"); - if (!f) - { - printf("ARM7 BIOS not found\n"); + printf("ARM9 BIOS loaded\n"); + fclose(f); + } - for (i = 0; i < 16; i++) - ((u32*)ARM7BIOS)[i] = 0xE7FFDEFF; - } - else - { - fseek(f, 0, SEEK_SET); - fread(ARM7BIOS, 0x4000, 1, f); + f = Platform::OpenLocalFile("bios7.bin", "rb"); + if (!f) + { + printf("ARM7 BIOS not found\n"); - printf("ARM7 BIOS loaded\n"); - fclose(f); - } + for (i = 0; i < 16; i++) + ((u32*)ARM7BIOS)[i] = 0xE7FFDEFF; + } + else + { + fseek(f, 0, SEEK_SET); + fread(ARM7BIOS, 0x4000, 1, f); - DSi::LoadNAND(); + printf("ARM7 BIOS loaded\n"); + fclose(f); + } - // TODO for later: configure this when emulating a DSi - ARM9ClockShift = 1; + ARM9ClockShift = 1; + } ARM9Timestamp = 0; ARM9Target = 0; ARM7Timestamp = 0; ARM7Target = 0; @@ -443,8 +450,8 @@ void Reset() MapSharedWRAM(0); - ExMemCnt[0] = 0; - ExMemCnt[1] = 0; + ExMemCnt[0] = 0x4000; + ExMemCnt[1] = 0x4000; memset(ROMSeed0, 0, 2*8); memset(ROMSeed1, 0, 2*8); SetGBASlotTimings(); diff --git a/src/sha1/sha1.c b/src/sha1/sha1.c index 2c50433..3729550 100644 --- a/src/sha1/sha1.c +++ b/src/sha1/sha1.c @@ -42,7 +42,8 @@ A million repetitions of "a" #if defined(vax) || defined(ns32000) || defined(sun386) || defined(__i386__) || \ defined(MIPSEL) || defined(_MIPSEL) || defined(BIT_ZERO_ON_RIGHT) || \ - defined(__alpha__) || defined(__alpha) + defined(__alpha__) || defined(__alpha) || \ + defined(__WIN32__) #define BYTE_ORDER LITTLE_ENDIAN #endif @@ -103,12 +104,12 @@ A million repetitions of "a" /* Hash a single 512-bit block. This is the core of the algorithm. */ -void SHA1Transform(u_int32_t state[5], const unsigned char buffer[64]) +void SHA1Transform(uint32_t state[5], const unsigned char buffer[64]) { -u_int32_t a, b, c, d, e; +uint32_t a, b, c, d, e; typedef union { unsigned char c[64]; - u_int32_t l[16]; + uint32_t l[16]; } CHAR64LONG16; #ifdef SHA1HANDSOFF CHAR64LONG16 block[1]; /* use array to appear as a pointer */ @@ -178,10 +179,10 @@ void SHA1Init(SHA1_CTX* context) /* Run your data through this. */ -void SHA1Update(SHA1_CTX* context, const unsigned char* data, u_int32_t len) +void SHA1Update(SHA1_CTX* context, const unsigned char* data, uint32_t len) { -u_int32_t i; -u_int32_t j; +uint32_t i; +uint32_t j; j = context->count[0]; if ((context->count[0] += len << 3) < j) @@ -219,7 +220,7 @@ unsigned char c; for (i = 0; i < 2; i++) { - u_int32_t t = context->count[i]; + uint32_t t = context->count[i]; int j; for (j = 0; j < 4; t >>= 8, j++) diff --git a/src/sha1/sha1.h b/src/sha1/sha1.h index 9d6f129..56ffa56 100644 --- a/src/sha1/sha1.h +++ b/src/sha1/sha1.h @@ -5,13 +5,15 @@ By Steve Reid 100% Public Domain */ +#include + typedef struct { - u_int32_t state[5]; - u_int32_t count[2]; + uint32_t state[5]; + uint32_t count[2]; unsigned char buffer[64]; } SHA1_CTX; -void SHA1Transform(u_int32_t state[5], const unsigned char buffer[64]); +void SHA1Transform(uint32_t state[5], const unsigned char buffer[64]); void SHA1Init(SHA1_CTX* context); -void SHA1Update(SHA1_CTX* context, const unsigned char* data, u_int32_t len); +void SHA1Update(SHA1_CTX* context, const unsigned char* data, uint32_t len); void SHA1Final(unsigned char digest[20], SHA1_CTX* context); -- cgit v1.2.3 From 7aa5131ec719f6dc4577a660ce94d793aa4a8617 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Sat, 15 Jun 2019 14:05:31 +0200 Subject: run teh binary. BAHAHAHAHAHAHAHAAHHHH it doesn't do much for now tho --- src/DSi.cpp | 284 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/DSi.h | 2 + src/NDS.cpp | 2 + 3 files changed, 288 insertions(+) (limited to 'src/NDS.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index 920981d..22741aa 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -20,14 +20,26 @@ #include #include "NDS.h" #include "DSi.h" +#include "ARM.h" #include "tiny-AES-c/aes.hpp" #include "sha1/sha1.h" #include "Platform.h" +namespace NDS +{ + +extern ARMv5* ARM9; +extern ARMv4* ARM7; + +} + + namespace DSi { +u32 BootAddr[2]; + u32 MBK[2][9]; u8 NWRAM_A[0x40000]; @@ -43,6 +55,12 @@ u32 NWRAMEnd[2][3]; u32 NWRAMMask[2][3]; +void Reset() +{ + NDS::ARM9->JumpTo(BootAddr[0]); + NDS::ARM7->JumpTo(BootAddr[1]); +} + bool LoadBIOS() { FILE* f; @@ -158,6 +176,56 @@ bool LoadNAND() // TODO: MBK9 protect thing + // load binaries + // TODO: optionally support loading from actual NAND? + // currently decrypted binaries have to be provided + // they can be decrypted with twltool + + FILE* bin; + + bin = Platform::OpenLocalFile("boot2_9.bin", "rb"); + if (bin) + { + u32 dstaddr = bootparams[2]; + for (u32 i = 0; i < bootparams[1]; i += 4) + { + u32 _tmp; + fread(&_tmp, 4, 1, bin); + ARM9Write32(dstaddr, _tmp); + dstaddr += 4; + } + + fclose(bin); + } + else + { + printf("ARM9 boot2 not found\n"); + } + + bin = Platform::OpenLocalFile("boot2_7.bin", "rb"); + if (bin) + { + u32 dstaddr = bootparams[6]; + for (u32 i = 0; i < bootparams[5]; i += 4) + { + u32 _tmp; + fread(&_tmp, 4, 1, bin); + ARM7Write32(dstaddr, _tmp); + dstaddr += 4; + } + + fclose(bin); + } + else + { + printf("ARM7 boot2 not found\n"); + } + + // repoint CPUs to the boot2 binaries + + BootAddr[0] = bootparams[2]; + BootAddr[1] = bootparams[6]; + #define printhex(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); printf("\n"); } #define printhex_rev(str, size) { for (int z = (size)-1; z >= 0; z--) printf("%02X", (str)[z]); printf("\n"); } @@ -316,6 +384,24 @@ u8 ARM9Read8(u32 addr) { switch (addr & 0xFF000000) { + case 0x03000000: + if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0]) + { + u8* ptr = NWRAMMap_A[0][(addr >> 16) & NWRAMMask[0][0]]; + return ptr ? *(u8*)&ptr[addr & 0xFFFF] : 0; + } + if (addr >= NWRAMStart[0][1] && addr < NWRAMEnd[0][1]) + { + u8* ptr = NWRAMMap_B[0][(addr >> 15) & NWRAMMask[0][1]]; + return ptr ? *(u8*)&ptr[addr & 0x7FFF] : 0; + } + if (addr >= NWRAMStart[0][2] && addr < NWRAMEnd[0][2]) + { + u8* ptr = NWRAMMap_C[0][(addr >> 15) & NWRAMMask[0][2]]; + return ptr ? *(u8*)&ptr[addr & 0x7FFF] : 0; + } + return NDS::ARM9Read8(addr); + case 0x04000000: return ARM9IORead8(addr); } @@ -327,6 +413,24 @@ u16 ARM9Read16(u32 addr) { switch (addr & 0xFF000000) { + case 0x03000000: + if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0]) + { + u8* ptr = NWRAMMap_A[0][(addr >> 16) & NWRAMMask[0][0]]; + return ptr ? *(u16*)&ptr[addr & 0xFFFF] : 0; + } + if (addr >= NWRAMStart[0][1] && addr < NWRAMEnd[0][1]) + { + u8* ptr = NWRAMMap_B[0][(addr >> 15) & NWRAMMask[0][1]]; + return ptr ? *(u16*)&ptr[addr & 0x7FFF] : 0; + } + if (addr >= NWRAMStart[0][2] && addr < NWRAMEnd[0][2]) + { + u8* ptr = NWRAMMap_C[0][(addr >> 15) & NWRAMMask[0][2]]; + return ptr ? *(u16*)&ptr[addr & 0x7FFF] : 0; + } + return NDS::ARM9Read16(addr); + case 0x04000000: return ARM9IORead16(addr); } @@ -338,6 +442,24 @@ u32 ARM9Read32(u32 addr) { switch (addr & 0xFF000000) { + case 0x03000000: + if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0]) + { + u8* ptr = NWRAMMap_A[0][(addr >> 16) & NWRAMMask[0][0]]; + return ptr ? *(u32*)&ptr[addr & 0xFFFF] : 0; + } + if (addr >= NWRAMStart[0][1] && addr < NWRAMEnd[0][1]) + { + u8* ptr = NWRAMMap_B[0][(addr >> 15) & NWRAMMask[0][1]]; + return ptr ? *(u32*)&ptr[addr & 0x7FFF] : 0; + } + if (addr >= NWRAMStart[0][2] && addr < NWRAMEnd[0][2]) + { + u8* ptr = NWRAMMap_C[0][(addr >> 15) & NWRAMMask[0][2]]; + return ptr ? *(u32*)&ptr[addr & 0x7FFF] : 0; + } + return NDS::ARM9Read32(addr); + case 0x04000000: return ARM9IORead32(addr); } @@ -349,6 +471,24 @@ void ARM9Write8(u32 addr, u8 val) { switch (addr & 0xFF000000) { + case 0x03000000: + if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0]) + { + u8* ptr = NWRAMMap_A[0][(addr >> 16) & NWRAMMask[0][0]]; + if (ptr) *(u8*)&ptr[addr & 0xFFFF] = val; + } + if (addr >= NWRAMStart[0][1] && addr < NWRAMEnd[0][1]) + { + u8* ptr = NWRAMMap_B[0][(addr >> 15) & NWRAMMask[0][1]]; + if (ptr) *(u8*)&ptr[addr & 0x7FFF] = val; + } + if (addr >= NWRAMStart[0][2] && addr < NWRAMEnd[0][2]) + { + u8* ptr = NWRAMMap_C[0][(addr >> 15) & NWRAMMask[0][2]]; + if (ptr) *(u8*)&ptr[addr & 0x7FFF] = val; + } + return NDS::ARM9Write8(addr, val); + case 0x04000000: ARM9IOWrite8(addr, val); return; @@ -361,6 +501,24 @@ void ARM9Write16(u32 addr, u16 val) { switch (addr & 0xFF000000) { + case 0x03000000: + if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0]) + { + u8* ptr = NWRAMMap_A[0][(addr >> 16) & NWRAMMask[0][0]]; + if (ptr) *(u16*)&ptr[addr & 0xFFFF] = val; + } + if (addr >= NWRAMStart[0][1] && addr < NWRAMEnd[0][1]) + { + u8* ptr = NWRAMMap_B[0][(addr >> 15) & NWRAMMask[0][1]]; + if (ptr) *(u16*)&ptr[addr & 0x7FFF] = val; + } + if (addr >= NWRAMStart[0][2] && addr < NWRAMEnd[0][2]) + { + u8* ptr = NWRAMMap_C[0][(addr >> 15) & NWRAMMask[0][2]]; + if (ptr) *(u16*)&ptr[addr & 0x7FFF] = val; + } + return NDS::ARM9Write16(addr, val); + case 0x04000000: ARM9IOWrite16(addr, val); return; @@ -373,6 +531,24 @@ void ARM9Write32(u32 addr, u32 val) { switch (addr & 0xFF000000) { + case 0x03000000: + if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0]) + { + u8* ptr = NWRAMMap_A[0][(addr >> 16) & NWRAMMask[0][0]]; + if (ptr) *(u32*)&ptr[addr & 0xFFFF] = val; + } + if (addr >= NWRAMStart[0][1] && addr < NWRAMEnd[0][1]) + { + u8* ptr = NWRAMMap_B[0][(addr >> 15) & NWRAMMask[0][1]]; + if (ptr) *(u32*)&ptr[addr & 0x7FFF] = val; + } + if (addr >= NWRAMStart[0][2] && addr < NWRAMEnd[0][2]) + { + u8* ptr = NWRAMMap_C[0][(addr >> 15) & NWRAMMask[0][2]]; + if (ptr) *(u32*)&ptr[addr & 0x7FFF] = val; + } + return NDS::ARM9Write32(addr, val); + case 0x04000000: ARM9IOWrite32(addr, val); return; @@ -408,6 +584,24 @@ u8 ARM7Read8(u32 addr) { switch (addr & 0xFF800000) { + case 0x03000000: + if (addr >= NWRAMStart[1][0] && addr < NWRAMEnd[1][0]) + { + u8* ptr = NWRAMMap_A[1][(addr >> 16) & NWRAMMask[1][0]]; + return ptr ? *(u8*)&ptr[addr & 0xFFFF] : 0; + } + if (addr >= NWRAMStart[1][1] && addr < NWRAMEnd[1][1]) + { + u8* ptr = NWRAMMap_B[1][(addr >> 15) & NWRAMMask[1][1]]; + return ptr ? *(u8*)&ptr[addr & 0x7FFF] : 0; + } + if (addr >= NWRAMStart[1][2] && addr < NWRAMEnd[1][2]) + { + u8* ptr = NWRAMMap_C[1][(addr >> 15) & NWRAMMask[1][2]]; + return ptr ? *(u8*)&ptr[addr & 0x7FFF] : 0; + } + return NDS::ARM7Read8(addr); + case 0x04000000: return ARM7IORead8(addr); } @@ -419,6 +613,24 @@ u16 ARM7Read16(u32 addr) { switch (addr & 0xFF800000) { + case 0x03000000: + if (addr >= NWRAMStart[1][0] && addr < NWRAMEnd[1][0]) + { + u8* ptr = NWRAMMap_A[1][(addr >> 16) & NWRAMMask[1][0]]; + return ptr ? *(u16*)&ptr[addr & 0xFFFF] : 0; + } + if (addr >= NWRAMStart[1][1] && addr < NWRAMEnd[1][1]) + { + u8* ptr = NWRAMMap_B[1][(addr >> 15) & NWRAMMask[1][1]]; + return ptr ? *(u16*)&ptr[addr & 0x7FFF] : 0; + } + if (addr >= NWRAMStart[1][2] && addr < NWRAMEnd[1][2]) + { + u8* ptr = NWRAMMap_C[1][(addr >> 15) & NWRAMMask[1][2]]; + return ptr ? *(u16*)&ptr[addr & 0x7FFF] : 0; + } + return NDS::ARM7Read16(addr); + case 0x04000000: return ARM7IORead16(addr); } @@ -430,6 +642,24 @@ u32 ARM7Read32(u32 addr) { switch (addr & 0xFF800000) { + case 0x03000000: + if (addr >= NWRAMStart[1][0] && addr < NWRAMEnd[1][0]) + { + u8* ptr = NWRAMMap_A[1][(addr >> 16) & NWRAMMask[1][0]]; + return ptr ? *(u32*)&ptr[addr & 0xFFFF] : 0; + } + if (addr >= NWRAMStart[1][1] && addr < NWRAMEnd[1][1]) + { + u8* ptr = NWRAMMap_B[1][(addr >> 15) & NWRAMMask[1][1]]; + return ptr ? *(u32*)&ptr[addr & 0x7FFF] : 0; + } + if (addr >= NWRAMStart[1][2] && addr < NWRAMEnd[1][2]) + { + u8* ptr = NWRAMMap_C[1][(addr >> 15) & NWRAMMask[1][2]]; + return ptr ? *(u32*)&ptr[addr & 0x7FFF] : 0; + } + return NDS::ARM7Read32(addr); + case 0x04000000: return ARM7IORead32(addr); } @@ -441,6 +671,24 @@ void ARM7Write8(u32 addr, u8 val) { switch (addr & 0xFF800000) { + case 0x03000000: + if (addr >= NWRAMStart[1][0] && addr < NWRAMEnd[1][0]) + { + u8* ptr = NWRAMMap_A[1][(addr >> 16) & NWRAMMask[1][0]]; + if (ptr) *(u8*)&ptr[addr & 0xFFFF] = val; + } + if (addr >= NWRAMStart[1][1] && addr < NWRAMEnd[1][1]) + { + u8* ptr = NWRAMMap_B[1][(addr >> 15) & NWRAMMask[1][1]]; + if (ptr) *(u8*)&ptr[addr & 0x7FFF] = val; + } + if (addr >= NWRAMStart[1][2] && addr < NWRAMEnd[1][2]) + { + u8* ptr = NWRAMMap_C[1][(addr >> 15) & NWRAMMask[1][2]]; + if (ptr) *(u8*)&ptr[addr & 0x7FFF] = val; + } + return NDS::ARM7Write8(addr, val); + case 0x04000000: ARM7IOWrite8(addr, val); return; @@ -453,6 +701,24 @@ void ARM7Write16(u32 addr, u16 val) { switch (addr & 0xFF800000) { + case 0x03000000: + if (addr >= NWRAMStart[1][0] && addr < NWRAMEnd[1][0]) + { + u8* ptr = NWRAMMap_A[1][(addr >> 16) & NWRAMMask[1][0]]; + if (ptr) *(u16*)&ptr[addr & 0xFFFF] = val; + } + if (addr >= NWRAMStart[1][1] && addr < NWRAMEnd[1][1]) + { + u8* ptr = NWRAMMap_B[1][(addr >> 15) & NWRAMMask[1][1]]; + if (ptr) *(u16*)&ptr[addr & 0x7FFF] = val; + } + if (addr >= NWRAMStart[1][2] && addr < NWRAMEnd[1][2]) + { + u8* ptr = NWRAMMap_C[1][(addr >> 15) & NWRAMMask[1][2]]; + if (ptr) *(u16*)&ptr[addr & 0x7FFF] = val; + } + return NDS::ARM7Write16(addr, val); + case 0x04000000: ARM7IOWrite16(addr, val); return; @@ -465,6 +731,24 @@ void ARM7Write32(u32 addr, u32 val) { switch (addr & 0xFF800000) { + case 0x03000000: + if (addr >= NWRAMStart[1][0] && addr < NWRAMEnd[1][0]) + { + u8* ptr = NWRAMMap_A[1][(addr >> 16) & NWRAMMask[1][0]]; + if (ptr) *(u32*)&ptr[addr & 0xFFFF] = val; + } + if (addr >= NWRAMStart[1][1] && addr < NWRAMEnd[1][1]) + { + u8* ptr = NWRAMMap_B[1][(addr >> 15) & NWRAMMask[1][1]]; + if (ptr) *(u32*)&ptr[addr & 0x7FFF] = val; + } + if (addr >= NWRAMStart[1][2] && addr < NWRAMEnd[1][2]) + { + u8* ptr = NWRAMMap_C[1][(addr >> 15) & NWRAMMask[1][2]]; + if (ptr) *(u32*)&ptr[addr & 0x7FFF] = val; + } + return NDS::ARM7Write32(addr, val); + case 0x04000000: ARM7IOWrite32(addr, val); return; diff --git a/src/DSi.h b/src/DSi.h index 040c39b..b1b4abf 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -24,6 +24,8 @@ namespace DSi { +void Reset(); + bool LoadBIOS(); bool LoadNAND(); diff --git a/src/NDS.cpp b/src/NDS.cpp index 5481f6f..c285910 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -510,6 +510,8 @@ void Reset() SPI::Reset(); RTC::Reset(); Wifi::Reset(); + + DSi::Reset(); } void Stop() -- cgit v1.2.3 From 566a8df6cd5af057a77cf8bed091e1b7a18bfecd Mon Sep 17 00:00:00 2001 From: Arisotura Date: Sun, 16 Jun 2019 15:05:18 +0200 Subject: add IE2/IF2 --- src/DSi.cpp | 10 ++++++++++ src/NDS.cpp | 16 ++++++++++++++++ src/NDS.h | 41 ++++++++++++++++++++++++++++++++++++++--- 3 files changed, 64 insertions(+), 3 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index ae1bed2..206c253 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -897,6 +897,9 @@ u16 ARM7IORead16(u32 addr) { switch (addr) { + case 0x04000218: return NDS::IE2; + case 0x0400021C: return NDS::IF2; + case 0x04004004: return 0x0187; case 0x04004006: return 0; // JTAG register } @@ -908,6 +911,9 @@ u32 ARM7IORead32(u32 addr) { switch (addr) { + case 0x04000218: return NDS::IE2; + case 0x0400021C: return NDS::IF2; + case 0x04004008: return 0x80000000; // HAX } @@ -929,6 +935,8 @@ void ARM7IOWrite16(u32 addr, u16 val) { switch (addr) { + case 0x04000218: NDS::IE2 = (val & 0x7FF7); NDS::UpdateIRQ(1); return; + case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return; } return NDS::ARM7IOWrite16(addr, val); @@ -938,6 +946,8 @@ void ARM7IOWrite32(u32 addr, u32 val) { switch (addr) { + case 0x04000218: NDS::IE2 = (val & 0x7FF7); NDS::UpdateIRQ(1); return; + case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return; } return NDS::ARM7IOWrite32(addr, val); diff --git a/src/NDS.cpp b/src/NDS.cpp index c285910..5ca55f3 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -107,6 +107,7 @@ u8 ROMSeed1[2*8]; // IO shit u32 IME[2]; u32 IE[2], IF[2]; +u32 IE2, IF2; u8 PostFlag9; u8 PostFlag7; @@ -462,6 +463,8 @@ void Reset() IME[1] = 0; IE[1] = 0; IF[1] = 0; + IE2 = 0; + IF2 = 0; PostFlag9 = 0x00; PostFlag7 = 0x00; @@ -1067,6 +1070,7 @@ void UpdateIRQ(u32 cpu) if (IME[cpu] & 0x1) { arm->IRQ = IE[cpu] & IF[cpu]; + if (cpu) arm->IRQ |= (IE2 & IF2); } else { @@ -1086,6 +1090,18 @@ void ClearIRQ(u32 cpu, u32 irq) UpdateIRQ(cpu); } +void SetIRQ2(u32 irq) +{ + IF2 |= (1 << irq); + UpdateIRQ(1); +} + +void ClearIRQ2(u32 irq) +{ + IF2 &= ~(1 << irq); + UpdateIRQ(1); +} + bool HaltInterrupted(u32 cpu) { if (cpu == 0) diff --git a/src/NDS.h b/src/NDS.h index e8bb44d..e6cd2ee 100644 --- a/src/NDS.h +++ b/src/NDS.h @@ -74,12 +74,42 @@ enum IRQ_IPCSync, IRQ_IPCSendDone, IRQ_IPCRecv, - IRQ_CartSendDone, - IRQ_CartIREQMC, + IRQ_CartSendDone, // TODO: less misleading name + IRQ_CartIREQMC, // IRQ triggered by game cart (example: Pokémon Typing Adventure, BT controller) IRQ_GXFIFO, IRQ_LidOpen, IRQ_SPI, - IRQ_Wifi + IRQ_Wifi, + + // DSi IRQs + IRQ_DSi_DSP = 24, + IRQ_DSi_Camera, + IRQ_DSi_Unk26, + IRQ_DSi_Unk27, + IRQ_DSi_NDMA0, + IRQ_DSi_NDMA1, + IRQ_DSi_NDMA2, + IRQ_DSi_NDMA3, +}; + +enum +{ + // DSi ARM7-side IE2/IF2 + IRQ2_DSi_GPIO18_0 = 0, + IRQ2_DSi_GPIO18_1, + IRQ2_DSi_GPIO18_2, + IRQ2_DSi_Unused35, + IRQ2_DSi_GPIO33_0, + IRQ2_DSi_Headphone, + IRQ2_DSi_PowerButton, + IRQ2_DSi_GPIO33_3, // "sound enable input" + IRQ2_DSi_SDMMC, + IRQ2_DSi_SD_Data1, + IRQ2_DSi_SDIO, + IRQ2_DSi_SDIO_Data1, + IRQ2_DSi_AES, + IRQ2_DSi_I2C, + IRQ2_DSi_MicExt }; typedef struct @@ -109,6 +139,8 @@ extern u32 ARM9ClockShift; extern u32 IME[2]; extern u32 IE[2]; extern u32 IF[2]; +extern u32 IE2; +extern u32 IF2; extern Timer Timers[8]; extern u16 PowerControl9; @@ -162,8 +194,11 @@ void Halt(); void MapSharedWRAM(u8 val); +void UpdateIRQ(u32 cpu); void SetIRQ(u32 cpu, u32 irq); void ClearIRQ(u32 cpu, u32 irq); +void SetIRQ2(u32 irq); +void ClearIRQ2(u32 irq); bool HaltInterrupted(u32 cpu); void StopCPU(u32 cpu, u32 mask); void ResumeCPU(u32 cpu, u32 mask); -- cgit v1.2.3 From d4dd97638d1615f51bcadd256d390a895519d565 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Sun, 16 Jun 2019 17:01:49 +0200 Subject: lay base for SD shit --- melonDS.cbp | 2 ++ src/DSi.cpp | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/DSi.h | 2 ++ src/DSi_SD.cpp | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/DSi_SD.h | 41 +++++++++++++++++++++++++++++++++ src/NDS.cpp | 4 ++++ src/version.h | 2 +- 7 files changed, 189 insertions(+), 1 deletion(-) create mode 100644 src/DSi_SD.cpp create mode 100644 src/DSi_SD.h (limited to 'src/NDS.cpp') diff --git a/melonDS.cbp b/melonDS.cbp index bbe07dd..e75e02c 100644 --- a/melonDS.cbp +++ b/melonDS.cbp @@ -106,6 +106,8 @@ + + diff --git a/src/DSi.cpp b/src/DSi.cpp index 206c253..e30e3e1 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -26,6 +26,7 @@ #include "Platform.h" #include "DSi_I2C.h" +#include "DSi_SD.h" namespace NDS @@ -56,6 +57,27 @@ u32 NWRAMStart[2][3]; u32 NWRAMEnd[2][3]; u32 NWRAMMask[2][3]; +DSi_SD* SDMMC; +DSi_SD* SDIO; + + +bool Init() +{ + if (!DSi_I2C::Init()) return false; + + SDMMC = new DSi_SD(0); + SDIO = new DSi_SD(1); + + return true; +} + +void DeInit() +{ + DSi_I2C::DeInit(); + + delete SDMMC; + delete SDIO; +} void Reset() { @@ -67,6 +89,9 @@ void Reset() NDS::ARM7->JumpTo(BootAddr[1]); DSi_I2C::Reset(); + + SDMMC->Reset(); + SDIO->Reset(); } bool LoadBIOS() @@ -904,6 +929,15 @@ u16 ARM7IORead16(u32 addr) case 0x04004006: return 0; // JTAG register } + if (addr >= 0x04004800 && addr < 0x04004A00) + { + return SDMMC->Read(addr); + } + if (addr >= 0x04004A00 && addr < 0x04004C00) + { + return SDIO->Read(addr); + } + return NDS::ARM7IORead16(addr); } @@ -917,6 +951,15 @@ u32 ARM7IORead32(u32 addr) case 0x04004008: return 0x80000000; // HAX } + if (addr >= 0x04004800 && addr < 0x04004A00) + { + return SDMMC->Read(addr) | (SDMMC->Read(addr+2) << 16); + } + if (addr >= 0x04004A00 && addr < 0x04004C00) + { + return SDIO->Read(addr) | (SDIO->Read(addr+2) << 16); + } + return NDS::ARM7IORead32(addr); } @@ -939,6 +982,17 @@ void ARM7IOWrite16(u32 addr, u16 val) case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return; } + if (addr >= 0x04004800 && addr < 0x04004A00) + { + SDMMC->Write(addr, val); + return; + } + if (addr >= 0x04004A00 && addr < 0x04004C00) + { + SDIO->Write(addr, val); + return; + } + return NDS::ARM7IOWrite16(addr, val); } @@ -950,6 +1004,19 @@ void ARM7IOWrite32(u32 addr, u32 val) case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return; } + if (addr >= 0x04004800 && addr < 0x04004A00) + { + SDMMC->Write(addr, val & 0xFFFF); + SDMMC->Write(addr+2, val >> 16); + return; + } + if (addr >= 0x04004A00 && addr < 0x04004C00) + { + SDIO->Write(addr, val & 0xFFFF); + SDIO->Write(addr+2, val >> 16); + return; + } + return NDS::ARM7IOWrite32(addr, val); } diff --git a/src/DSi.h b/src/DSi.h index 02f84da..6d45a10 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -24,6 +24,8 @@ namespace DSi { +bool Init(); +void DeInit(); void Reset(); bool LoadBIOS(); diff --git a/src/DSi_SD.cpp b/src/DSi_SD.cpp new file mode 100644 index 0000000..58b733c --- /dev/null +++ b/src/DSi_SD.cpp @@ -0,0 +1,72 @@ +/* + Copyright 2016-2019 Arisotura + + This file is part of melonDS. + + melonDS is free software: you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation, either version 3 of the License, or (at your option) + any later version. + + melonDS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with melonDS. If not, see http://www.gnu.org/licenses/. +*/ + +#include +#include +#include "DSi.h" +#include "DSi_SD.h" + + +DSi_SD::DSi_SD(u32 num) +{ + Num = num; +} + +DSi_SD::~DSi_SD() +{ + // +} + +void DSi_SD::Reset() +{ + if (Num == 0) + { + PortSelect = 0x0200; // CHECKME + } + else + { + PortSelect = 0x0100; // CHECKME + } +} + +void DSi_SD::DoSavestate(Savestate* file) +{ + // TODO! +} + + +u16 DSi_SD::Read(u32 addr) +{ + switch (addr & 0x1FF) + { + case 0x002: return PortSelect & 0x030F; + } + + printf("unknown %s read %08X\n", Num?"SDIO":"SD/MMC", addr); + return 0; +} + +void DSi_SD::Write(u32 addr, u16 val) +{ + switch (addr & 0x1FF) + { + case 0x002: PortSelect = val; return; + } + + printf("unknown %s write %08X %04X\n", Num?"SDIO":"SD/MMC", addr, val); +} diff --git a/src/DSi_SD.h b/src/DSi_SD.h new file mode 100644 index 0000000..ce3eb84 --- /dev/null +++ b/src/DSi_SD.h @@ -0,0 +1,41 @@ +/* + Copyright 2016-2019 Arisotura + + This file is part of melonDS. + + melonDS is free software: you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation, either version 3 of the License, or (at your option) + any later version. + + melonDS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with melonDS. If not, see http://www.gnu.org/licenses/. +*/ + +#ifndef DSI_SD_H +#define DSI_SD_H + +class DSi_SD +{ +public: + DSi_SD(u32 num); + ~DSi_SD(); + + void Reset(); + + void DoSavestate(Savestate* file); + + u16 Read(u32 addr); + void Write(u32 addr, u16 val); + +private: + u32 Num; + + u16 PortSelect; +}; + +#endif // DSI_SD_H diff --git a/src/NDS.cpp b/src/NDS.cpp index 5ca55f3..414f87c 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -178,6 +178,8 @@ bool Init() if (!RTC::Init()) return false; if (!Wifi::Init()) return false; + if (!DSi::Init()) return false; + return true; } @@ -198,6 +200,8 @@ void DeInit() SPI::DeInit(); RTC::DeInit(); Wifi::DeInit(); + + DSi::DeInit(); } diff --git a/src/version.h b/src/version.h index cc15c89..bb97c3c 100644 --- a/src/version.h +++ b/src/version.h @@ -19,7 +19,7 @@ #ifndef VERSION_H #define VERSION_H -#define MELONDS_VERSION "0.8.1" +#define MELONDS_VERSION "0.8.1-DSi" #define MELONDS_URL "http://melonds.kuribo64.net/" -- cgit v1.2.3 From d6bbc6f0f1ede57f0805137617ba670a49f7506f Mon Sep 17 00:00:00 2001 From: Arisotura Date: Tue, 18 Jun 2019 22:54:07 +0200 Subject: tremble upon the NDMA implementation that doesn't do much beyond getting stuck --- src/DMA.cpp | 6 -- src/DSi.cpp | 171 +++++++++++++++++++++++++++++++ src/DSi.h | 4 + src/DSi_NDMA.cpp | 301 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/DSi_NDMA.h | 74 +++++++++++++- src/NDS.cpp | 4 + src/NDS.h | 5 +- 7 files changed, 556 insertions(+), 9 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/DMA.cpp b/src/DMA.cpp index 2814264..0826d7a 100644 --- a/src/DMA.cpp +++ b/src/DMA.cpp @@ -20,15 +20,9 @@ #include "NDS.h" #include "DSi.h" #include "DMA.h" -#include "NDSCart.h" #include "GPU.h" -// NOTES ON DMA SHIT -// -// * could use optimized code paths for common types of DMA transfers. for example, VRAM -// have to profile it to see if it's actually worth doing - // DMA TIMINGS // diff --git a/src/DSi.cpp b/src/DSi.cpp index abd3bd6..0c9c26c 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -25,6 +25,7 @@ #include "sha1/sha1.h" #include "Platform.h" +#include "DSi_NDMA.h" #include "DSi_I2C.h" #include "DSi_SD.h" @@ -57,6 +58,9 @@ u32 NWRAMStart[2][3]; u32 NWRAMEnd[2][3]; u32 NWRAMMask[2][3]; +u32 NDMACnt[2]; +DSi_NDMA* NDMAs[8]; + DSi_SDHost* SDMMC; DSi_SDHost* SDIO; @@ -68,6 +72,15 @@ bool Init() { if (!DSi_I2C::Init()) return false; + NDMAs[0] = new DSi_NDMA(0, 0); + NDMAs[1] = new DSi_NDMA(0, 1); + NDMAs[2] = new DSi_NDMA(0, 2); + NDMAs[3] = new DSi_NDMA(0, 3); + NDMAs[4] = new DSi_NDMA(1, 0); + NDMAs[5] = new DSi_NDMA(1, 1); + NDMAs[6] = new DSi_NDMA(1, 2); + NDMAs[7] = new DSi_NDMA(1, 3); + SDMMC = new DSi_SDHost(0); SDIO = new DSi_SDHost(1); @@ -78,6 +91,8 @@ void DeInit() { DSi_I2C::DeInit(); + for (int i = 0; i < 8; i++) delete NDMAs[i]; + delete SDMMC; delete SDIO; } @@ -91,6 +106,9 @@ void Reset() NDS::ARM9->JumpTo(BootAddr[0]); NDS::ARM7->JumpTo(BootAddr[1]); + NDMACnt[0] = 0; NDMACnt[1] = 0; + for (int i = 0; i < 8; i++) NDMAs[i]->Reset(); + DSi_I2C::Reset(); SDMMC->Reset(); @@ -279,6 +297,40 @@ bool LoadNAND() } +void RunNDMAs(u32 cpu) +{ + // TODO: round-robin mode (requires DMA channels to have a subblock delay set) + + if (cpu == 0) + { + if (NDS::ARM9Timestamp >= NDS::ARM9Target) return; + + // + } + else + { + if (NDS::ARM7Timestamp >= NDS::ARM7Target) return; + + // + } +} + +void StallNDMAs() +{ + // TODO +} + +bool NDMAsRunning(u32 cpu) +{ + cpu <<= 2; + if (NDMAs[cpu+0]->IsRunning()) return true; + if (NDMAs[cpu+1]->IsRunning()) return true; + if (NDMAs[cpu+2]->IsRunning()) return true; + if (NDMAs[cpu+3]->IsRunning()) return true; + return false; +} + + // new WRAM mapping // TODO: find out what happens upon overlapping slots!! @@ -872,6 +924,36 @@ u32 ARM9IORead32(u32 addr) switch (addr) { case 0x04004010: return 1; // todo + + case 0x04004100: return NDMACnt[0]; + case 0x04004104: return NDMAs[0]->SrcAddr; + case 0x04004108: return NDMAs[0]->DstAddr; + case 0x0400410C: return NDMAs[0]->TotalLength; + case 0x04004110: return NDMAs[0]->BlockLength; + case 0x04004114: return NDMAs[0]->SubblockTimer; + case 0x04004118: return NDMAs[0]->FillData; + case 0x0400411C: return NDMAs[0]->Cnt; + case 0x04004120: return NDMAs[1]->SrcAddr; + case 0x04004124: return NDMAs[1]->DstAddr; + case 0x04004128: return NDMAs[1]->TotalLength; + case 0x0400412C: return NDMAs[1]->BlockLength; + case 0x04004130: return NDMAs[1]->SubblockTimer; + case 0x04004134: return NDMAs[1]->FillData; + case 0x04004138: return NDMAs[1]->Cnt; + case 0x0400413C: return NDMAs[2]->SrcAddr; + case 0x04004140: return NDMAs[2]->DstAddr; + case 0x04004144: return NDMAs[2]->TotalLength; + case 0x04004148: return NDMAs[2]->BlockLength; + case 0x0400414C: return NDMAs[2]->SubblockTimer; + case 0x04004150: return NDMAs[2]->FillData; + case 0x04004154: return NDMAs[2]->Cnt; + case 0x04004158: return NDMAs[3]->SrcAddr; + case 0x0400415C: return NDMAs[3]->DstAddr; + case 0x04004160: return NDMAs[3]->TotalLength; + case 0x04004164: return NDMAs[3]->BlockLength; + case 0x04004168: return NDMAs[3]->SubblockTimer; + case 0x0400416C: return NDMAs[3]->FillData; + case 0x04004170: return NDMAs[3]->Cnt; } return NDS::ARM9IORead32(addr); @@ -899,6 +981,35 @@ void ARM9IOWrite32(u32 addr, u32 val) { switch (addr) { + case 0x04004100: NDMACnt[0] = val & 0x800F0000; return; + case 0x04004104: NDMAs[0]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004108: NDMAs[0]->DstAddr = val & 0xFFFFFFFC; return; + case 0x0400410C: NDMAs[0]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004110: NDMAs[0]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004114: NDMAs[0]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004118: NDMAs[0]->FillData = val; return; + case 0x0400411C: NDMAs[0]->WriteCnt(val); return; + case 0x04004120: NDMAs[1]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004124: NDMAs[1]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004128: NDMAs[1]->TotalLength = val & 0x0FFFFFFF; return; + case 0x0400412C: NDMAs[1]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004130: NDMAs[1]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004134: NDMAs[1]->FillData = val; return; + case 0x04004138: NDMAs[1]->WriteCnt(val); return; + case 0x0400413C: NDMAs[2]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004140: NDMAs[2]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004144: NDMAs[2]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004148: NDMAs[2]->BlockLength = val & 0x00FFFFFF; return; + case 0x0400414C: NDMAs[2]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004150: NDMAs[2]->FillData = val; return; + case 0x04004154: NDMAs[2]->WriteCnt(val); return; + case 0x04004158: NDMAs[3]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x0400415C: NDMAs[3]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004160: NDMAs[3]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004164: NDMAs[3]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004168: NDMAs[3]->SubblockTimer = val & 0x0003FFFF; return; + case 0x0400416C: NDMAs[3]->FillData = val; return; + case 0x04004170: NDMAs[3]->WriteCnt(val); return; } return NDS::ARM9IOWrite32(addr, val); @@ -950,6 +1061,36 @@ u32 ARM7IORead32(u32 addr) case 0x0400021C: return NDS::IF2; case 0x04004008: return 0x80000000; // HAX + + case 0x04004100: return NDMACnt[1]; + case 0x04004104: return NDMAs[4]->SrcAddr; + case 0x04004108: return NDMAs[4]->DstAddr; + case 0x0400410C: return NDMAs[4]->TotalLength; + case 0x04004110: return NDMAs[4]->BlockLength; + case 0x04004114: return NDMAs[4]->SubblockTimer; + case 0x04004118: return NDMAs[4]->FillData; + case 0x0400411C: return NDMAs[4]->Cnt; + case 0x04004120: return NDMAs[5]->SrcAddr; + case 0x04004124: return NDMAs[5]->DstAddr; + case 0x04004128: return NDMAs[5]->TotalLength; + case 0x0400412C: return NDMAs[5]->BlockLength; + case 0x04004130: return NDMAs[5]->SubblockTimer; + case 0x04004134: return NDMAs[5]->FillData; + case 0x04004138: return NDMAs[5]->Cnt; + case 0x0400413C: return NDMAs[6]->SrcAddr; + case 0x04004140: return NDMAs[6]->DstAddr; + case 0x04004144: return NDMAs[6]->TotalLength; + case 0x04004148: return NDMAs[6]->BlockLength; + case 0x0400414C: return NDMAs[6]->SubblockTimer; + case 0x04004150: return NDMAs[6]->FillData; + case 0x04004154: return NDMAs[6]->Cnt; + case 0x04004158: return NDMAs[7]->SrcAddr; + case 0x0400415C: return NDMAs[7]->DstAddr; + case 0x04004160: return NDMAs[7]->TotalLength; + case 0x04004164: return NDMAs[7]->BlockLength; + case 0x04004168: return NDMAs[7]->SubblockTimer; + case 0x0400416C: return NDMAs[7]->FillData; + case 0x04004170: return NDMAs[7]->Cnt; } if (addr >= 0x04004800 && addr < 0x04004A00) @@ -1003,6 +1144,36 @@ void ARM7IOWrite32(u32 addr, u32 val) { case 0x04000218: NDS::IE2 = (val & 0x7FF7); NDS::UpdateIRQ(1); return; case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return; + + case 0x04004100: NDMACnt[1] = val & 0x800F0000; return; + case 0x04004104: NDMAs[4]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004108: NDMAs[4]->DstAddr = val & 0xFFFFFFFC; return; + case 0x0400410C: NDMAs[4]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004110: NDMAs[4]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004114: NDMAs[4]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004118: NDMAs[4]->FillData = val; return; + case 0x0400411C: NDMAs[4]->WriteCnt(val); return; + case 0x04004120: NDMAs[5]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004124: NDMAs[5]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004128: NDMAs[5]->TotalLength = val & 0x0FFFFFFF; return; + case 0x0400412C: NDMAs[5]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004130: NDMAs[5]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004134: NDMAs[5]->FillData = val; return; + case 0x04004138: NDMAs[5]->WriteCnt(val); return; + case 0x0400413C: NDMAs[6]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004140: NDMAs[6]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004144: NDMAs[6]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004148: NDMAs[6]->BlockLength = val & 0x00FFFFFF; return; + case 0x0400414C: NDMAs[6]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004150: NDMAs[6]->FillData = val; return; + case 0x04004154: NDMAs[6]->WriteCnt(val); return; + case 0x04004158: NDMAs[7]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x0400415C: NDMAs[7]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004160: NDMAs[7]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004164: NDMAs[7]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004168: NDMAs[7]->SubblockTimer = val & 0x0003FFFF; return; + case 0x0400416C: NDMAs[7]->FillData = val; return; + case 0x04004170: NDMAs[7]->WriteCnt(val); return; } if (addr >= 0x04004800 && addr < 0x04004A00) diff --git a/src/DSi.h b/src/DSi.h index efd533a..32253a7 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -38,6 +38,10 @@ void Reset(); bool LoadBIOS(); bool LoadNAND(); +void RunNDMAs(u32 cpu); +void StallNDMAs(); +bool NDMAsRunning(u32 cpu); + void MapNWRAM_A(u32 num, u8 val); void MapNWRAM_B(u32 num, u8 val); void MapNWRAM_C(u32 num, u8 val); diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index 6a524dd..a8055eb 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -15,3 +15,304 @@ You should have received a copy of the GNU General Public License along with melonDS. If not, see http://www.gnu.org/licenses/. */ + +#include +#include "NDS.h" +#include "DSi.h" +#include "DSi_NDMA.h" +#include "GPU.h" + + + +DSi_NDMA::DSi_NDMA(u32 cpu, u32 num) +{ + CPU = cpu; + Num = num; + + Reset(); +} + +DSi_NDMA::~DSi_NDMA() +{ +} + +void DSi_NDMA::Reset() +{ + SrcAddr = 0; + DstAddr = 0; + TotalLength = 0; + BlockLength = 0; + SubblockTimer = 0; + FillData = 0; + Cnt = 0; + + StartMode = 0; + CurSrcAddr = 0; + CurDstAddr = 0; + SubblockLength = 0; + RemCount = 0; + IterCount = 0; + TotalRemCount = 0; + SrcAddrInc = 0; + DstAddrInc = 0; + + Running = false; + InProgress = false; +} + +void DSi_NDMA::DoSavestate(Savestate* file) +{ + // TODO! +} + +void DSi_NDMA::WriteCnt(u32 val) +{ + u32 oldcnt = Cnt; + Cnt = val; + + if ((!(oldcnt & 0x80000000)) && (val & 0x80000000)) // checkme + { + CurSrcAddr = SrcAddr; + CurDstAddr = DstAddr; + TotalRemCount = TotalLength; + + switch ((Cnt >> 10) & 0x3) + { + case 0: DstAddrInc = 1; break; + case 1: DstAddrInc = -1; break; + case 2: DstAddrInc = 0; break; + case 3: DstAddrInc = 1; printf("BAD NDMA DST INC MODE 3\n"); break; + } + + switch ((Cnt >> 13) & 0x3) + { + case 0: SrcAddrInc = 1; break; + case 1: SrcAddrInc = -1; break; + case 2: SrcAddrInc = 0; break; + case 3: SrcAddrInc = 0; break; // fill mode + } + + StartMode = (Cnt >> 24) & 0x1F; + if (StartMode > 0x10) StartMode = 0x10; + if (CPU == 1) StartMode |= 0x20; + + if ((StartMode & 0x1F) == 0x10) + Start(); + + if (StartMode != 0x10 && StartMode != 0x30) + printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X\n", CPU?7:9, Num, StartMode, SrcAddr, DstAddr); + } +} + +void DSi_NDMA::Start() +{ + if (Running) return; + + if (!InProgress) + { + RemCount = BlockLength; + if (!RemCount) + RemCount = 0x1000000; + } + + // TODO: how does GXFIFO DMA work with all the block shito? + IterCount = RemCount; + + if (IterCount > TotalRemCount) + IterCount = TotalRemCount; + + if (Cnt & (1<<12)) CurDstAddr = DstAddr; + if (Cnt & (1<<15)) CurSrcAddr = SrcAddr; + + printf("ARM%d NDMA%d %08X %02X %08X->%08X %d bytes\n", CPU?7:9, Num, Cnt, StartMode, CurSrcAddr, CurDstAddr, RemCount*4); + + //IsGXFIFODMA = (CPU == 0 && (CurSrcAddr>>24) == 0x02 && CurDstAddr == 0x04000400 && DstAddrInc == 0); + + // TODO eventually: not stop if we're running code in ITCM + + if (SubblockTimer & 0xFFFF) + printf("TODO! NDMA SUBBLOCK TIMER: %08X\n", SubblockTimer); + + if (NDS::DMAsRunning(CPU)) + Running = 1; + else + Running = 2; + + InProgress = true; + NDS::StopCPU(CPU, 1<<(Num+4)); +} + +void DSi_NDMA::Run() +{ + if (!Running) return; + if (CPU == 0) return Run9(); + else return Run7(); +} + +void DSi_NDMA::Run9() +{ + if (NDS::ARM9Timestamp >= NDS::ARM9Target) return; + + Executing = true; + + // add NS penalty for first accesses in burst + bool burststart = (Running == 2); + Running = 1; + + s32 unitcycles; + //s32 lastcycles = cycles; + + bool dofill = ((Cnt >> 13) & 0x3) == 3; + + if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02) + { + unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2]; + } + else + { + unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][3] + NDS::ARM9MemTimings[CurDstAddr >> 14][3]; + if ((CurSrcAddr >> 24) == (CurDstAddr >> 24)) + unitcycles++; + else if ((CurSrcAddr >> 24) == 0x02) + unitcycles--; + + /*if (burststart) + { + cycles -= 2; + cycles -= (NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2]); + cycles += unitcycles; + }*/ + } + + while (IterCount > 0 && !Stall) + { + NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift); + + if (dofill) + DSi::ARM9Write32(CurDstAddr, FillData); + else + DSi::ARM9Write32(CurDstAddr, DSi::ARM9Read32(CurSrcAddr)); + + CurSrcAddr += SrcAddrInc<<2; + CurDstAddr += DstAddrInc<<2; + IterCount--; + RemCount--; + TotalRemCount--; + + if (NDS::ARM9Timestamp >= NDS::ARM9Target) break; + } + + Executing = false; + Stall = false; + + if (RemCount) + { + if (IterCount == 0) + { + Running = 0; + NDS::ResumeCPU(0, 1<<(Num+4)); + + //if (StartMode == 0x07) + // GPU3D::CheckFIFODMA(); + } + + return; + } + + if ((StartMode & 0x1F) == 0x10) // CHECKME + Cnt &= ~(1<<31); + else if (!(Cnt & (1<<29))) + { + if (TotalRemCount == 0) + Cnt &= ~(1<<31); + } + + if (Cnt & (1<<30)) + NDS::SetIRQ(0, NDS::IRQ_DSi_NDMA0 + Num); + + Running = 0; + InProgress = false; + NDS::ResumeCPU(0, 1<<(Num+4)); +} + +void DSi_NDMA::Run7() +{ + if (NDS::ARM7Timestamp >= NDS::ARM7Target) return; + + Executing = true; + + // add NS penalty for first accesses in burst + bool burststart = (Running == 2); + Running = 1; + + s32 unitcycles; + //s32 lastcycles = cycles; + + bool dofill = ((Cnt >> 13) & 0x3) == 3; + + if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02) + { + unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2]; + } + else + { + unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][3] + NDS::ARM7MemTimings[CurDstAddr >> 15][3]; + if ((CurSrcAddr >> 23) == (CurDstAddr >> 23)) + unitcycles++; + else if ((CurSrcAddr >> 24) == 0x02) + unitcycles--; + + /*if (burststart) + { + cycles -= 2; + cycles -= (NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2]); + cycles += unitcycles; + }*/ + } + + while (IterCount > 0 && !Stall) + { + NDS::ARM7Timestamp += unitcycles; + + if (dofill) + DSi::ARM7Write32(CurDstAddr, FillData); + else + DSi::ARM7Write32(CurDstAddr, DSi::ARM7Read32(CurSrcAddr)); + + CurSrcAddr += SrcAddrInc<<2; + CurDstAddr += DstAddrInc<<2; + IterCount--; + RemCount--; + + if (NDS::ARM7Timestamp >= NDS::ARM7Target) break; + } + + Executing = false; + Stall = false; + + if (RemCount) + { + if (IterCount == 0) + { + Running = 0; + NDS::ResumeCPU(1, 1<<(Num+4)); + } + + return; + } + + if ((StartMode & 0x1F) == 0x10) // CHECKME + Cnt &= ~(1<<31); + else if (!(Cnt & (1<<29))) + { + if (TotalRemCount == 0) + Cnt &= ~(1<<31); + } + + if (Cnt & (1<<30)) + NDS::SetIRQ(1, NDS::IRQ_DSi_NDMA0 + Num); + + Running = 0; + InProgress = false; + NDS::ResumeCPU(1, 1<<(Num+4)); +} diff --git a/src/DSi_NDMA.h b/src/DSi_NDMA.h index 6661652..d7b7483 100644 --- a/src/DSi_NDMA.h +++ b/src/DSi_NDMA.h @@ -19,6 +19,78 @@ #ifndef DSI_NDMA_H #define DSI_NDMA_H -// +#include "types.h" + +class DSi_NDMA +{ +public: + DSi_NDMA(u32 cpu, u32 num); + ~DSi_NDMA(); + + void Reset(); + + void DoSavestate(Savestate* file); + + void WriteCnt(u32 val); + void Start(); + + void Run(); + + void Run9(); + void Run7(); + + bool IsInMode(u32 mode) + { + return ((mode == StartMode) && (Cnt & 0x80000000)); + } + + bool IsRunning() { return Running!=0; } + + void StartIfNeeded(u32 mode) + { + if ((mode == StartMode) && (Cnt & 0x80000000)) + Start(); + } + + void StopIfNeeded(u32 mode) + { + if (mode == StartMode) + Cnt &= ~0x80000000; + } + + void StallIfRunning() + { + if (Executing) Stall = true; + } + + u32 SrcAddr; + u32 DstAddr; + u32 TotalLength; // total length, when transferring multiple blocks + u32 BlockLength; // length of one transfer + u32 SubblockTimer; // optional delay between subblocks (only in round-robin mode) + u32 FillData; + u32 Cnt; + +private: + u32 CPU, Num; + + u32 StartMode; + u32 CurSrcAddr; + u32 CurDstAddr; + u32 SubblockLength; // length transferred per run when delay is used + u32 RemCount; + u32 IterCount; + u32 TotalRemCount; + u32 SrcAddrInc; + u32 DstAddrInc; + + u32 Running; + bool InProgress; + + bool Executing; + bool Stall; + + bool IsGXFIFODMA; +}; #endif // DSI_NDMA_H diff --git a/src/NDS.cpp b/src/NDS.cpp index 414f87c..e20f62f 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -827,6 +827,7 @@ u32 RunFrame() if (!(CPUStop & 0x80000000)) DMAs[1]->Run(); if (!(CPUStop & 0x80000000)) DMAs[2]->Run(); if (!(CPUStop & 0x80000000)) DMAs[3]->Run(); + DSi::RunNDMAs(0); } else { @@ -849,6 +850,7 @@ u32 RunFrame() DMAs[5]->Run(); DMAs[6]->Run(); DMAs[7]->Run(); + DSi::RunNDMAs(1); } else { @@ -1153,6 +1155,7 @@ void GXFIFOStall() DMAs[1]->StallIfRunning(); DMAs[2]->StallIfRunning(); DMAs[3]->StallIfRunning(); + DSi::StallNDMAs(); } } @@ -1367,6 +1370,7 @@ bool DMAsRunning(u32 cpu) if (DMAs[cpu+1]->IsRunning()) return true; if (DMAs[cpu+2]->IsRunning()) return true; if (DMAs[cpu+3]->IsRunning()) return true; + if (DSi::NDMAsRunning(cpu>>2)) return true; return false; } diff --git a/src/NDS.h b/src/NDS.h index f87ffed..850e829 100644 --- a/src/NDS.h +++ b/src/NDS.h @@ -101,7 +101,7 @@ enum IRQ2_DSi_GPIO18_0 = 0, IRQ2_DSi_GPIO18_1, IRQ2_DSi_GPIO18_2, - IRQ2_DSi_Unused35, + IRQ2_DSi_Unused3, IRQ2_DSi_GPIO33_0, IRQ2_DSi_Headphone, IRQ2_DSi_PowerButton, @@ -138,7 +138,6 @@ extern u64 ARM9Timestamp, ARM9Target; extern u64 ARM7Timestamp, ARM7Target; extern u32 ARM9ClockShift; -// hax extern u32 IME[2]; extern u32 IE[2]; extern u32 IF[2]; @@ -146,6 +145,8 @@ extern u32 IE2; extern u32 IF2; extern Timer Timers[8]; +extern u32 CPUStop; + extern u16 PowerControl9; extern u16 ExMemCnt[2]; -- cgit v1.2.3 From 81dde71ebac19cf9a68dd7a2a41561cbcbfacc68 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Wed, 19 Jun 2019 14:24:49 +0200 Subject: add AES, fix a bunch of bugs we're getting an error screen! wee --- src/ARM.cpp | 37 ------- src/DSi.cpp | 55 ++++++++++ src/DSi.h | 3 + src/DSi_AES.cpp | 303 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/DSi_AES.h | 26 ++++- src/DSi_NDMA.cpp | 21 ++-- src/DSi_SD.cpp | 21 ++-- src/NDS.cpp | 6 +- 8 files changed, 416 insertions(+), 56 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/ARM.cpp b/src/ARM.cpp index 60dec9a..b7fe3c7 100644 --- a/src/ARM.cpp +++ b/src/ARM.cpp @@ -239,36 +239,6 @@ void ARMv4::JumpTo(u32 addr, bool restorecpsr) else addr &= ~0x1; } - /*if (addr==0x037D4668) printf("MYSTERY START\n"); - if (addr==0x037CA71C) printf("MYSTERY END\n"); - if (addr==0x037CCD68) printf("atomic_store %08X %08X, %08X\n", R[0], R[1], R[15]); - if (addr==0x037CDD00) printf("zog %08X\n", R[15]);*/ - /*if (addr==0x037CDC00) printf("sendcmd %08X %08X\n", R[0], R[15]); - if (addr==0x037CA700) printf("prepare CID, %08X\n", R[15]); - if(addr==0x037D4498) printf("READ SHITTY FIFO. %08X\n", R[15]); - if (addr==0x037CCD68) printf("atomic_store %08X %08X, %08X\n", R[0], R[1], R[15]); - if (addr>=0x037CEE00 && addr<=0x037CEE30) printf("shitty loop: %08X->%08X\n", R[15], addr); - if (R[15]==0x037CCD8C) printf("BERG!!! %08X\n", addr); - if (addr==0x037CD600) printf("XFER IRQ HANDLER\n"); - if (R[15]==0x037CD62C) printf("TERRIBLE HANDLER: %08X\n", addr); - if (addr==0x037CCE24) printf("SD IRQ HANDLER\n"); - if (addr==0x037CCD94) printf("atomic_load %08X %08X, %08X\n", R[0], R[1], R[15]); - if (addr==0x037CEB7C) printf("CHECK CSR RESULT. %08X %08X %08X, %08X\n", R[0], R[1], R[2], R[15]); - if (R[15]==0x037CEC6C) printf("RETURN FROM CSR CHECK: %08X %08X\n", R[0], R[3]+0x38); - if (addr==0x037CB2AC) printf("ZOG!\n"); - if (addr==0x037CB2A0) printf("GONP %08X %08X, %08X\n", R[1]+0x28, R[3]+0x34, R[15]); - if (addr==0x037CCFC0) printf("SDMMC TIMEOUT. %08X\n", R[15]); - if (addr==0x037D68A8) printf("BARKBARKBARK. %08X\n", R[15]); - if (addr==0x037CCF04) printf("BAKAAA\n"); - if (addr==0x037D6988) printf("MORPMORPMORPMORPMORPMORPMORPMORPMORP %08X\n", R[15]); - if (addr==0x37D6904) printf("TIMEOUT FARTORED! %08X, %08X %08X, %08X\n", R[4], R[3], R[12], R[15]); - // TIMEOUT FARTORED! 037E89B8, 00000000 00200BFB, 037D68FC - if (addr==0x037CD660) printf("BRAAAAAAAAAAAP %08X\n", R[15]); - if (addr==0x037CD798) printf("BRAAPP SHATORED. %08X, %08X %08X\n", R[0], R[1], R[2]); - if (addr==0x037CCD34) printf("atomic_and %08X %08X, %08X\n", R[0], R[1], R[15]);*/ - // atomic_and 0400481C 0000FFE7, 037CD850 - - u32 oldregion = R[15] >> 23; u32 newregion = addr >> 23; @@ -607,13 +577,6 @@ void ARMv4::Execute() } else AddCycles_C(); - - /*if (R[15]==0x037CEE18) printf("SHITTY POINTER = %08X\n", R[0]+0x34); - if (R[15]==0x037CEE1C) printf("SHITTY FLAG = %08X\n", R[0]); - if (R[15]==0x037D68F0) printf("TIMESTAMP THING = %08X:%08X, CUR=%08X:%08X, ptr=%08X\n", - R[3], R[12], R[1], R[0], R[4]); - //if (R[15]==0x037CB29C) printf("GLORG!!! %08X\n", R[3]+0x34); 037E8A8C - if (R[15]==0x037CD730) printf("COUNT OF SHITO. %08X %08X\n", R[0], R[2]);*/ } // TODO optimize this shit!!! diff --git a/src/DSi.cpp b/src/DSi.cpp index fc590e1..fd58872 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -28,6 +28,7 @@ #include "DSi_NDMA.h" #include "DSi_I2C.h" #include "DSi_SD.h" +#include "DSi_AES.h" namespace NDS @@ -71,6 +72,7 @@ u8 eMMC_CID[16]; bool Init() { if (!DSi_I2C::Init()) return false; + if (!DSi_AES::Init()) return false; NDMAs[0] = new DSi_NDMA(0, 0); NDMAs[1] = new DSi_NDMA(0, 1); @@ -90,6 +92,7 @@ bool Init() void DeInit() { DSi_I2C::DeInit(); + DSi_AES::DeInit(); for (int i = 0; i < 8; i++) delete NDMAs[i]; @@ -110,6 +113,7 @@ void Reset() for (int i = 0; i < 8; i++) NDMAs[i]->Reset(); DSi_I2C::Reset(); + DSi_AES::Reset(); SDMMC->Reset(); SDIO->Reset(); @@ -336,6 +340,24 @@ bool NDMAsRunning(u32 cpu) return false; } +void CheckNDMAs(u32 cpu, u32 mode) +{ + cpu <<= 2; + NDMAs[cpu+0]->StartIfNeeded(mode); + NDMAs[cpu+1]->StartIfNeeded(mode); + NDMAs[cpu+2]->StartIfNeeded(mode); + NDMAs[cpu+3]->StartIfNeeded(mode); +} + +void StopNDMAs(u32 cpu, u32 mode) +{ + cpu <<= 2; + NDMAs[cpu+0]->StopIfNeeded(mode); + NDMAs[cpu+1]->StopIfNeeded(mode); + NDMAs[cpu+2]->StopIfNeeded(mode); + NDMAs[cpu+3]->StopIfNeeded(mode); +} + // new WRAM mapping // TODO: find out what happens upon overlapping slots!! @@ -1097,6 +1119,9 @@ u32 ARM7IORead32(u32 addr) case 0x04004168: return NDMAs[7]->SubblockTimer; case 0x0400416C: return NDMAs[7]->FillData; case 0x04004170: return NDMAs[7]->Cnt; + + case 0x04004400: return DSi_AES::ReadCnt(); + case 0x0400440C: return DSi_AES::ReadOutputFIFO(); } if (addr >= 0x04004800 && addr < 0x04004A00) @@ -1182,6 +1207,36 @@ void ARM7IOWrite32(u32 addr, u32 val) case 0x04004168: NDMAs[7]->SubblockTimer = val & 0x0003FFFF; return; case 0x0400416C: NDMAs[7]->FillData = val; return; case 0x04004170: NDMAs[7]->WriteCnt(val); return; + + case 0x04004400: DSi_AES::WriteCnt(val); return; + case 0x04004404: DSi_AES::WriteBlkCnt(val); return; + case 0x04004408: DSi_AES::WriteInputFIFO(val); return; + } + + if (addr >= 0x04004420 && addr < 0x04004430) + { + addr -= 0x04004420; + DSi_AES::WriteIV(addr, val, 0xFFFFFFFF); + return; + } + if (addr >= 0x04004430 && addr < 0x04004440) + { + addr -= 0x04004430; + DSi_AES::WriteMAC(addr, val, 0xFFFFFFFF); + return; + } + if (addr >= 0x04004440 && addr < 0x04004500) + { + addr -= 0x04004440; + int n = 0; + while (addr > 0x30) { addr -= 0x30; n++; } + + switch (addr >> 4) + { + case 0: DSi_AES::WriteKeyNormal(n, addr&0xF, val, 0xFFFFFFFF); return; + case 1: DSi_AES::WriteKeyX(n, addr&0xF, val, 0xFFFFFFFF); return; + case 2: DSi_AES::WriteKeyY(n, addr&0xF, val, 0xFFFFFFFF); return; + } } if (addr >= 0x04004800 && addr < 0x04004A00) diff --git a/src/DSi.h b/src/DSi.h index 32253a7..642a56a 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -26,6 +26,7 @@ namespace DSi { extern u8 eMMC_CID[16]; +extern u64 ConsoleID; extern DSi_SDHost* SDMMC; extern DSi_SDHost* SDIO; @@ -41,6 +42,8 @@ bool LoadNAND(); void RunNDMAs(u32 cpu); void StallNDMAs(); bool NDMAsRunning(u32 cpu); +void CheckNDMAs(u32 cpu, u32 mode); +void StopNDMAs(u32 cpu, u32 mode); void MapNWRAM_A(u32 num, u8 val); void MapNWRAM_B(u32 num, u8 val); diff --git a/src/DSi_AES.cpp b/src/DSi_AES.cpp index 6a524dd..8271e3e 100644 --- a/src/DSi_AES.cpp +++ b/src/DSi_AES.cpp @@ -15,3 +15,306 @@ You should have received a copy of the GNU General Public License along with melonDS. If not, see http://www.gnu.org/licenses/. */ + +#include +#include +#include "DSi.h" +#include "DSi_AES.h" +#include "FIFO.h" +#include "tiny-AES-c/aes.hpp" + + +namespace DSi_AES +{ + +u32 Cnt; + +u32 BlkCnt; +u32 RemBlocks; + +u32 InputDMASize, OutputDMASize; +u32 AESMode; + +FIFO* InputFIFO; +FIFO* OutputFIFO; + +u8 IV[16]; + +u8 KeyNormal[4][16]; +u8 KeyX[4][16]; +u8 KeyY[4][16]; + +u8 CurKey[16]; + +AES_ctx Ctx; + + +void Swap16(u8* dst, u8* src) +{ + for (int i = 0; i < 16; i++) + dst[i] = src[15-i]; +} + +void ROL16(u8* val, u32 n) +{ + u32 n_coarse = n >> 3; + u32 n_fine = n & 7; + u8 tmp[16]; + + for (u32 i = 0; i < 16; i++) + { + tmp[i] = val[(i - n_coarse) & 0xF]; + } + + for (u32 i = 0; i < 16; i++) + { + val[i] = (tmp[i] << n_fine) | (tmp[(i - 1) & 0xF] >> (8-n_fine)); + } +} + +#define _printhex(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); printf("\n"); } + + +bool Init() +{ + InputFIFO = new FIFO(16); + OutputFIFO = new FIFO(16); + + const u8 zero[16] = {0}; + AES_init_ctx_iv(&Ctx, zero, zero); + + return true; +} + +void DeInit() +{ + delete InputFIFO; + delete OutputFIFO; +} + +void Reset() +{ + Cnt = 0; + + BlkCnt = 0; + RemBlocks = 0; + + InputDMASize = 0; + OutputDMASize = 0; + AESMode = 0; + + InputFIFO->Clear(); + OutputFIFO->Clear(); + + memset(KeyNormal, 0, sizeof(KeyNormal)); + memset(KeyX, 0, sizeof(KeyX)); + memset(KeyY, 0, sizeof(KeyY)); + + memset(CurKey, 0, sizeof(CurKey)); + + // initialize keys, as per GBAtek + + // slot 3: console-unique eMMC crypto + *(u32*)&KeyX[3][0] = (u32)DSi::ConsoleID; + *(u32*)&KeyX[3][4] = (u32)DSi::ConsoleID ^ 0x24EE6906; + *(u32*)&KeyX[3][8] = (u32)(DSi::ConsoleID >> 32) ^ 0xE65B601D; + *(u32*)&KeyX[3][12] = (u32)(DSi::ConsoleID >> 32); + *(u32*)&KeyY[3][0] = 0x0AB9DC76; + *(u32*)&KeyY[3][4] = 0xBD4DC4D3; + *(u32*)&KeyY[3][8] = 0x202DDD1D; +} + + +void ProcessBlock_CTR() +{ + u8 data[16]; + u8 data_rev[16]; + + *(u32*)&data[0] = InputFIFO->Read(); + *(u32*)&data[4] = InputFIFO->Read(); + *(u32*)&data[8] = InputFIFO->Read(); + *(u32*)&data[12] = InputFIFO->Read(); + + //printf("AES-CTR: INPUT: "); _printhex(data, 16); + + Swap16(data_rev, data); + AES_CTR_xcrypt_buffer(&Ctx, data_rev, 16); + Swap16(data, data_rev); + + //printf("AES-CTR: OUTPUT: "); _printhex(data, 16); + + OutputFIFO->Write(*(u32*)&data[0]); + OutputFIFO->Write(*(u32*)&data[4]); + OutputFIFO->Write(*(u32*)&data[8]); + OutputFIFO->Write(*(u32*)&data[12]); +} + + +u32 ReadCnt() +{ + u32 ret = Cnt; + + ret |= InputFIFO->Level(); + ret |= (OutputFIFO->Level() << 5); + + return ret; +} + +void WriteCnt(u32 val) +{ + u32 oldcnt = Cnt; + Cnt = val & 0xFC1FF000; + + if (val & (1<<10)) InputFIFO->Clear(); + if (val & (1<<11)) OutputFIFO->Clear(); + + u32 dmasize[4] = {4, 8, 12, 16}; + InputDMASize = dmasize[3 - ((val >> 12) & 0x3)]; + OutputDMASize = dmasize[(val >> 14) & 0x3]; + + AESMode = (val >> 28) & 0x3; + if (AESMode < 2) printf("AES-CCM TODO\n"); + + if (val & (1<<24)) + { + u32 slot = (val >> 26) & 0x3; + memcpy(CurKey, KeyNormal[slot], 16); + + //printf("AES: key(%d): ", slot); _printhex(CurKey, 16); + + u8 tmp[16]; + Swap16(tmp, CurKey); + AES_init_ctx(&Ctx, tmp); + } + + if (!(oldcnt & (1<<31)) && (val & (1<<31))) + { + // transfer start (checkme) + RemBlocks = BlkCnt >> 16; + } + + printf("AES CNT: %08X / mode=%d inDMA=%d outDMA=%d blocks=%d\n", + val, AESMode, InputDMASize, OutputDMASize, RemBlocks); +} + +void WriteBlkCnt(u32 val) +{ + BlkCnt = val; +} + +u32 ReadOutputFIFO() +{ + return OutputFIFO->Read(); +} + +void WriteInputFIFO(u32 val) +{ + // TODO: add some delay to processing + + InputFIFO->Write(val); + + if (!(Cnt & (1<<31))) return; + + while (InputFIFO->Level() >= 4 && RemBlocks > 0) + { + switch (AESMode) + { + case 2: + case 3: ProcessBlock_CTR(); break; + default: + // dorp + OutputFIFO->Write(InputFIFO->Read()); + OutputFIFO->Write(InputFIFO->Read()); + OutputFIFO->Write(InputFIFO->Read()); + OutputFIFO->Write(InputFIFO->Read()); + } + + RemBlocks--; + } + + if (OutputFIFO->Level() >= OutputDMASize) + { + // trigger DMA + DSi::CheckNDMAs(1, 0x2B); + } + // TODO: DMA the other way around + + if (RemBlocks == 0) + { + Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ2(NDS::IRQ2_DSi_AES); + } +} + + +void WriteIV(u32 offset, u32 val, u32 mask) +{ + u32 old = *(u32*)&IV[offset]; + + *(u32*)&IV[offset] = (old & ~mask) | (val & mask); + + //printf("AES: IV: "); _printhex(IV, 16); + + u8 tmp[16]; + Swap16(tmp, IV); + AES_ctx_set_iv(&Ctx, tmp); +} + +void WriteMAC(u32 offset, u32 val, u32 mask) +{ + // +} + +void DeriveNormalKey(u32 slot) +{ + const u8 key_const[16] = {0xFF, 0xFE, 0xFB, 0x4E, 0x29, 0x59, 0x02, 0x58, 0x2A, 0x68, 0x0F, 0x5F, 0x1A, 0x4F, 0x3E, 0x79}; + u8 tmp[16]; + + //printf("keyX: "); _printhex(KeyX[slot], 16); + //printf("keyY: "); _printhex(KeyY[slot], 16); + + for (int i = 0; i < 16; i++) + tmp[i] = KeyX[slot][i] ^ KeyY[slot][i]; + + u32 carry = 0; + for (int i = 0; i < 16; i++) + { + u32 res = tmp[i] + key_const[15-i] + carry; + tmp[i] = res & 0xFF; + carry = res >> 8; + } + + ROL16(tmp, 42); + + //printf("derive normalkey %d\n", slot); _printhex(tmp, 16); + + memcpy(KeyNormal[slot], tmp, 16); +} + +void WriteKeyNormal(u32 slot, u32 offset, u32 val, u32 mask) +{ + u32 old = *(u32*)&KeyNormal[slot][offset]; + + *(u32*)&KeyNormal[slot][offset] = (old & ~mask) | (val & mask); +} + +void WriteKeyX(u32 slot, u32 offset, u32 val, u32 mask) +{ + u32 old = *(u32*)&KeyX[slot][offset]; + + *(u32*)&KeyX[slot][offset] = (old & ~mask) | (val & mask); +} + +void WriteKeyY(u32 slot, u32 offset, u32 val, u32 mask) +{ + u32 old = *(u32*)&KeyY[slot][offset]; + + *(u32*)&KeyY[slot][offset] = (old & ~mask) | (val & mask); + + if (offset >= 0xC) + { + DeriveNormalKey(slot); + } +} + +} diff --git a/src/DSi_AES.h b/src/DSi_AES.h index 028523a..7c388f5 100644 --- a/src/DSi_AES.h +++ b/src/DSi_AES.h @@ -19,6 +19,30 @@ #ifndef DSI_AES_H #define DSI_AES_H -// +#include "types.h" + +namespace DSi_AES +{ + +extern u32 Cnt; + +bool Init(); +void DeInit(); +void Reset(); + +u32 ReadCnt(); +void WriteCnt(u32 val); +void WriteBlkCnt(u32 val); + +u32 ReadOutputFIFO(); +void WriteInputFIFO(u32 val); + +void WriteIV(u32 offset, u32 val, u32 mask); +void WriteMAC(u32 offset, u32 val, u32 mask); +void WriteKeyNormal(u32 slot, u32 offset, u32 val, u32 mask); +void WriteKeyX(u32 slot, u32 offset, u32 val, u32 mask); +void WriteKeyY(u32 slot, u32 offset, u32 val, u32 mask); + +} #endif // DSI_AES_H diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index 7c0b2a1..aed78af 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -99,7 +99,8 @@ void DSi_NDMA::WriteCnt(u32 val) if ((StartMode & 0x1F) == 0x10) Start(); - if (StartMode != 0x10 && StartMode != 0x30) + if (StartMode != 0x10 && StartMode != 0x30 && + StartMode != 0x2B) printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X\n", CPU?7:9, Num, StartMode, SrcAddr, DstAddr); } } @@ -223,16 +224,19 @@ void DSi_NDMA::Run9() } if ((StartMode & 0x1F) == 0x10) // CHECKME + { Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ(0, NDS::IRQ_DSi_NDMA0 + Num); + } else if (!(Cnt & (1<<29))) { if (TotalRemCount == 0) + { Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ(0, NDS::IRQ_DSi_NDMA0 + Num); + } } - if (Cnt & (1<<30)) - NDS::SetIRQ(0, NDS::IRQ_DSi_NDMA0 + Num); - Running = 0; InProgress = false; NDS::ResumeCPU(0, 1<<(Num+4)); @@ -305,16 +309,19 @@ void DSi_NDMA::Run7() } if ((StartMode & 0x1F) == 0x10) // CHECKME + { Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ(1, NDS::IRQ_DSi_NDMA0 + Num); + } else if (!(Cnt & (1<<29))) { if (TotalRemCount == 0) + { Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ(1, NDS::IRQ_DSi_NDMA0 + Num); + } } - if (Cnt & (1<<30)) - NDS::SetIRQ(1, NDS::IRQ_DSi_NDMA0 + Num); - Running = 0; InProgress = false; NDS::ResumeCPU(1, 1<<(Num+4)); diff --git a/src/DSi_SD.cpp b/src/DSi_SD.cpp index 42b515c..bb3c4a4 100644 --- a/src/DSi_SD.cpp +++ b/src/DSi_SD.cpp @@ -473,10 +473,10 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param) case 2: case 10: // get CID - Host->SendResponse(*(u32*)&CID[0], false); - Host->SendResponse(*(u32*)&CID[1], false); - Host->SendResponse(*(u32*)&CID[2], false); - Host->SendResponse(*(u32*)&CID[3], true); + Host->SendResponse(*(u32*)&CID[12], false); + Host->SendResponse(*(u32*)&CID[8], false); + Host->SendResponse(*(u32*)&CID[4], false); + Host->SendResponse(*(u32*)&CID[0], true); //if (cmd == 2) SetState(0x02); return; @@ -502,13 +502,18 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param) return; case 9: // get CSD - Host->SendResponse(*(u32*)&CSD[0], false); - Host->SendResponse(*(u32*)&CSD[1], false); - Host->SendResponse(*(u32*)&CSD[2], false); - Host->SendResponse(*(u32*)&CSD[3], true); + Host->SendResponse(*(u32*)&CSD[12], false); + Host->SendResponse(*(u32*)&CSD[8], false); + Host->SendResponse(*(u32*)&CSD[4], false); + Host->SendResponse(*(u32*)&CSD[0], true); return; case 12: // stop operation + // TODO + Host->SendResponse(CSR, true); + return; + + case 13: // get status Host->SendResponse(CSR, true); return; diff --git a/src/NDS.cpp b/src/NDS.cpp index e20f62f..7513d57 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -1582,12 +1582,12 @@ void debug(u32 param) printf("ARM7 PC=%08X LR=%08X %08X\n", ARM7->R[15], ARM7->R[14], ARM7->R_IRQ[1]); printf("ARM9 IME=%08X IE=%08X IF=%08X\n", IME[0], IE[0], IF[0]); - printf("ARM7 IME=%08X IE=%08X IF=%08X\n", IME[1], IE[1], IF[1]); + printf("ARM7 IME=%08X IE=%08X IF=%08X IE2=%04X IF2=%04X\n", IME[1], IE[1], IF[1], IE2, IF2); //for (int i = 0; i < 9; i++) // printf("VRAM %c: %02X\n", 'A'+i, GPU::VRAMCNT[i]); - FILE* + /*FILE* shit = fopen("debug/card.bin", "wb"); for (u32 i = 0x02000000; i < 0x02400000; i+=4) { @@ -1599,7 +1599,7 @@ void debug(u32 param) u32 val = ARM7Read32(i); fwrite(&val, 4, 1, shit); } - fclose(shit); + fclose(shit);*/ } -- cgit v1.2.3 From 000aa1f327c0fcfa627953fcb732884aec6867b1 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Thu, 20 Jun 2019 02:31:46 +0200 Subject: add LCD init flag in DISPSTAT --- src/DSi.cpp | 7 +++++-- src/GPU.cpp | 2 +- src/NDS.cpp | 15 +++++++++++++++ 3 files changed, 21 insertions(+), 3 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index c8d4c7d..ee9d21c 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -21,8 +21,7 @@ #include "NDS.h" #include "DSi.h" #include "ARM.h" -#include "tiny-AES-c/aes.hpp" -#include "sha1/sha1.h" +#include "GPU.h" #include "Platform.h" #include "DSi_NDMA.h" @@ -121,6 +120,10 @@ void Reset() SDMMC->Reset(); SDIO->Reset(); + + // LCD init flag + GPU::DispStat[0] |= (1<<6); + GPU::DispStat[1] |= (1<<6); } bool LoadBIOS() diff --git a/src/GPU.cpp b/src/GPU.cpp index dcd79b4..0eb321c 100644 --- a/src/GPU.cpp +++ b/src/GPU.cpp @@ -20,7 +20,7 @@ #include #include "NDS.h" #include "GPU.h" -u64 vbltime; + namespace GPU { diff --git a/src/NDS.cpp b/src/NDS.cpp index 7513d57..6622373 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -1600,6 +1600,21 @@ void debug(u32 param) fwrite(&val, 4, 1, shit); } fclose(shit);*/ + FILE* + shit = fopen("debug/dump9.bin", "wb"); + for (u32 i = 0x02000000; i < 0x04000000; i+=4) + { + u32 val = DSi::ARM9Read32(i); + fwrite(&val, 4, 1, shit); + } + fclose(shit); + shit = fopen("debug/dump7.bin", "wb"); + for (u32 i = 0x02000000; i < 0x04000000; i+=4) + { + u32 val = DSi::ARM7Read32(i); + fwrite(&val, 4, 1, shit); + } + fclose(shit); } -- cgit v1.2.3 From d943a51b9658e1898f49b6773f85778ae7348400 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Thu, 20 Jun 2019 03:19:51 +0200 Subject: ayyy getting there! --- src/DSi.cpp | 2 +- src/DSi_I2C.cpp | 9 ++++----- src/DSi_NDMA.cpp | 4 ++-- src/DSi_SD.cpp | 5 ++++- src/NDS.cpp | 4 ++-- 5 files changed, 13 insertions(+), 11 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index ee9d21c..0e35d53 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -1239,7 +1239,7 @@ u8 ARM7IORead8(u32 addr) CASE_READ8_32BIT(0x04004060, MBK[1][8]) case 0x04004500: return DSi_I2C::ReadData(); - case 0x04004501: printf("read I2C CNT %02X\n", DSi_I2C::Cnt); return DSi_I2C::Cnt; + case 0x04004501: return DSi_I2C::Cnt; case 0x04004D00: return ConsoleID & 0xFF; case 0x04004D01: return (ConsoleID >> 8) & 0xFF; diff --git a/src/DSi_I2C.cpp b/src/DSi_I2C.cpp index 8b01b0e..845dd9d 100644 --- a/src/DSi_I2C.cpp +++ b/src/DSi_I2C.cpp @@ -152,7 +152,7 @@ void Reset() void WriteCnt(u8 val) { - printf("I2C: write CNT %02X\n", val); + //printf("I2C: write CNT %02X\n", val); // TODO: check ACK flag // TODO: transfer delay @@ -174,7 +174,7 @@ void WriteCnt(u8 val) default: Data = 0; break; } - printf("I2C read, device=%02X, cnt=%02X, data=%02X, last=%d\n", Device, val, Data, islast); + //printf("I2C read, device=%02X, cnt=%02X, data=%02X, last=%d\n", Device, val, Data, islast); } else { @@ -184,7 +184,7 @@ void WriteCnt(u8 val) if (val & (1<<1)) { Device = Data & 0xFE; - printf("I2C: %s start, device=%02X\n", (Data&0x01)?"read":"write", Device); + //printf("I2C: %s start, device=%02X\n", (Data&0x01)?"read":"write", Device); switch (Device) { @@ -193,7 +193,7 @@ void WriteCnt(u8 val) } else { - printf("I2C write, device=%02X, cnt=%02X, data=%02X, last=%d\n", Device, val, Data, islast); + //printf("I2C write, device=%02X, cnt=%02X, data=%02X, last=%d\n", Device, val, Data, islast); switch (Device) { @@ -212,7 +212,6 @@ void WriteCnt(u8 val) u8 ReadData() { - printf("I2C: read the data: %02X\n", Data); return Data; } diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index a62904a..37eb687 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -135,8 +135,8 @@ void DSi_NDMA::Start() // TODO eventually: not stop if we're running code in ITCM - if (SubblockTimer & 0xFFFF) - printf("TODO! NDMA SUBBLOCK TIMER: %08X\n", SubblockTimer); + //if (SubblockTimer & 0xFFFF) + // printf("TODO! NDMA SUBBLOCK TIMER: %08X\n", SubblockTimer); if (NDS::DMAsRunning(CPU)) Running = 1; diff --git a/src/DSi_SD.cpp b/src/DSi_SD.cpp index fbb2e14..3764a3c 100644 --- a/src/DSi_SD.cpp +++ b/src/DSi_SD.cpp @@ -218,6 +218,8 @@ u16 DSi_SDHost::Read(u32 addr) case 0x026: return BlockLen16; case 0x028: return SDOption; + case 0x02C: return 0; // TODO + case 0x030: // FIFO16 { // TODO: decrement BlockLen???? @@ -275,7 +277,7 @@ u16 DSi_SDHost::Read(u32 addr) case 0x108: return BlockCount32; } - printf("unknown %s read %08X\n", SD_DESC, addr); + printf("unknown %s read %08X @ %08X\n", SD_DESC, addr, NDS::GetPC(1)); return 0; } @@ -356,6 +358,7 @@ void DSi_SDHost::Write(u32 addr, u16 val) break; } } + else printf("%s: SENDING CMD %04X TO NULL DEVICE\n", SD_DESC, val); } return; diff --git a/src/NDS.cpp b/src/NDS.cpp index 6622373..61cf547 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -1600,7 +1600,7 @@ void debug(u32 param) fwrite(&val, 4, 1, shit); } fclose(shit);*/ - FILE* + /*FILE* shit = fopen("debug/dump9.bin", "wb"); for (u32 i = 0x02000000; i < 0x04000000; i+=4) { @@ -1614,7 +1614,7 @@ void debug(u32 param) u32 val = DSi::ARM7Read32(i); fwrite(&val, 4, 1, shit); } - fclose(shit); + fclose(shit);*/ } -- cgit v1.2.3 From a6a9f74acc2fe1c0645dae7b06816d7fc6a67f81 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Sun, 4 Aug 2019 11:44:36 +0200 Subject: lay base for DSi-mode TSC --- melonDS.cbp | 2 + src/DSi_SPI_TSC.cpp | 113 +++++++++++++++++++++++++++++++++++++++++++++++++ src/DSi_SPI_TSC.h | 40 +++++++++++++++++ src/NDS.cpp | 32 ++++++++------ src/NDS.h | 2 - src/SPI.cpp | 14 ++++-- src/libui_sdl/main.cpp | 2 - 7 files changed, 186 insertions(+), 19 deletions(-) create mode 100644 src/DSi_SPI_TSC.cpp create mode 100644 src/DSi_SPI_TSC.h (limited to 'src/NDS.cpp') diff --git a/melonDS.cbp b/melonDS.cbp index 2fd6ed0..cc5357b 100644 --- a/melonDS.cbp +++ b/melonDS.cbp @@ -114,6 +114,8 @@ + + diff --git a/src/DSi_SPI_TSC.cpp b/src/DSi_SPI_TSC.cpp new file mode 100644 index 0000000..253cef8 --- /dev/null +++ b/src/DSi_SPI_TSC.cpp @@ -0,0 +1,113 @@ +/* + Copyright 2016-2019 Arisotura + + This file is part of melonDS. + + melonDS is free software: you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation, either version 3 of the License, or (at your option) + any later version. + + melonDS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with melonDS. If not, see http://www.gnu.org/licenses/. +*/ + +#include +#include +#include "DSi.h" +#include "DSi_SPI_TSC.h" + + +namespace DSi_SPI_TSC +{ + +u32 DataPos; +u8 Index; +u8 Mode; +u8 Data; + +u16 TouchX, TouchY; + + +bool Init() +{ + return true; +} + +void DeInit() +{ +} + +void Reset() +{ + DataPos = 0; + + Mode = 0; + Index = 0; + Data = 0; +} + +void DoSavestate(Savestate* file) +{ + /*file->Section("SPTi"); + + file->Var32(&DataPos); + file->Var8(&ControlByte); + file->Var8(&Data); + + file->Var16(&ConvResult);*/ + // TODO!! +} + +void SetTouchCoords(u16 x, u16 y) +{ + TouchX = x; + TouchY = y; + + if (y == 0xFFF) return; + + TouchX <<= 4; + TouchY <<= 4; +} + +void MicInputFrame(s16* data, int samples) +{ + // TODO: forward to DS-mode TSC if needed +} + +u8 Read() +{ + return Data; +} + +void Write(u8 val, u32 hold) +{ +#define READWRITE(var) { if (Index & 0x01) Data = var; else var = val; } +printf("TSC: %02X %d\n", val, hold?1:0); + if (DataPos == 0) + { + Index = val; + } + else + { + if ((Index & 0xFE) == 0) + { + READWRITE(Mode); + } + else + { + printf("DSi_SPI_TSC: unknown IO, mode=%02X, index=%02X (%02X %s)\n", Mode, Index, Index>>1, (Index&1)?"read":"write"); + } + + Index += (1<<1); // increment index + } + + if (hold) DataPos++; + else DataPos = 0; +} + +} diff --git a/src/DSi_SPI_TSC.h b/src/DSi_SPI_TSC.h new file mode 100644 index 0000000..f3ffc32 --- /dev/null +++ b/src/DSi_SPI_TSC.h @@ -0,0 +1,40 @@ +/* + Copyright 2016-2019 Arisotura + + This file is part of melonDS. + + melonDS is free software: you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation, either version 3 of the License, or (at your option) + any later version. + + melonDS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with melonDS. If not, see http://www.gnu.org/licenses/. +*/ + +#ifndef DSI_SPI_TSC +#define DSI_SPI_TSC + +namespace DSi_SPI_TSC +{ + +extern u32 DataPos; + +bool Init(); +void DeInit(); +void Reset(); +void DoSavestate(Savestate* file); + +void SetTouchCoords(u16 x, u16 y); +void MicInputFrame(s16* data, int samples); + +u8 Read(); +void Write(u8 val, u32 hold); + +} + +#endif // DSI_SPI_TSC diff --git a/src/NDS.cpp b/src/NDS.cpp index 61cf547..da7f9f9 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -32,6 +32,7 @@ #include "Platform.h" #include "DSi.h" +#include "DSi_SPI_TSC.h" namespace NDS @@ -519,6 +520,7 @@ void Reset() Wifi::Reset(); DSi::Reset(); + KeyInput &= ~(1 << (16+6)); // TODO } void Stop() @@ -932,24 +934,30 @@ void CancelEvent(u32 id) } -void PressKey(u32 key) -{ - KeyInput &= ~(1 << key); -} - -void ReleaseKey(u32 key) -{ - KeyInput |= (1 << key); -} - void TouchScreen(u16 x, u16 y) { - SPI_TSC::SetTouchCoords(x, y); + if (true) // TODO!! + { + DSi_SPI_TSC::SetTouchCoords(x, y); + } + else + { + SPI_TSC::SetTouchCoords(x, y); + KeyInput &= ~(1 << (16+6)); + } } void ReleaseScreen() { - SPI_TSC::SetTouchCoords(0x000, 0xFFF); + if (true) // TODO!! + { + DSi_SPI_TSC::SetTouchCoords(0x000, 0xFFF); + } + else + { + SPI_TSC::SetTouchCoords(0x000, 0xFFF); + KeyInput |= (1 << (16+6)); + } } diff --git a/src/NDS.h b/src/NDS.h index fd94a01..d391cf7 100644 --- a/src/NDS.h +++ b/src/NDS.h @@ -180,8 +180,6 @@ void RelocateSave(const char* path, bool write); u32 RunFrame(); -void PressKey(u32 key); -void ReleaseKey(u32 key); void TouchScreen(u16 x, u16 y); void ReleaseScreen(); diff --git a/src/SPI.cpp b/src/SPI.cpp index 783e638..e21ad0c 100644 --- a/src/SPI.cpp +++ b/src/SPI.cpp @@ -22,6 +22,7 @@ #include "Config.h" #include "NDS.h" #include "SPI.h" +#include "DSi_SPI_TSC.h" #include "Platform.h" @@ -590,6 +591,7 @@ bool Init() if (!SPI_Firmware::Init()) return false; if (!SPI_Powerman::Init()) return false; if (!SPI_TSC::Init()) return false; + if (!DSi_SPI_TSC::Init()) return false; return true; } @@ -599,6 +601,7 @@ void DeInit() SPI_Firmware::DeInit(); SPI_Powerman::DeInit(); SPI_TSC::DeInit(); + DSi_SPI_TSC::DeInit(); } void Reset() @@ -608,6 +611,7 @@ void Reset() SPI_Firmware::Reset(); SPI_Powerman::Reset(); SPI_TSC::Reset(); + DSi_SPI_TSC::Reset(); } void DoSavestate(Savestate* file) @@ -620,6 +624,7 @@ void DoSavestate(Savestate* file) SPI_Firmware::DoSavestate(file); SPI_Powerman::DoSavestate(file); SPI_TSC::DoSavestate(file); + DSi_SPI_TSC::DoSavestate(file); } @@ -633,7 +638,8 @@ void WriteCnt(u16 val) { case 0x0000: SPI_Powerman::Hold = 0; break; case 0x0100: SPI_Firmware::Hold = 0; break; - case 0x0200: SPI_TSC::DataPos = 0; break; + //case 0x0200: SPI_TSC::DataPos = 0; break; + case 0x0200: DSi_SPI_TSC::DataPos = 0; break; } } @@ -659,7 +665,8 @@ u8 ReadData() { case 0x0000: return SPI_Powerman::Read(); case 0x0100: return SPI_Firmware::Read(); - case 0x0200: return SPI_TSC::Read(); + //case 0x0200: return SPI_TSC::Read(); + case 0x0200: return DSi_SPI_TSC::Read(); default: return 0; } } @@ -675,7 +682,8 @@ void WriteData(u8 val) { case 0x0000: SPI_Powerman::Write(val, Cnt&(1<<11)); break; case 0x0100: SPI_Firmware::Write(val, Cnt&(1<<11)); break; - case 0x0200: SPI_TSC::Write(val, Cnt&(1<<11)); break; + //case 0x0200: SPI_TSC::Write(val, Cnt&(1<<11)); break; + case 0x0200: DSi_SPI_TSC::Write(val, Cnt&(1<<11)); break; default: printf("SPI to unknown device %04X %02X\n", Cnt, val); break; } diff --git a/src/libui_sdl/main.cpp b/src/libui_sdl/main.cpp index 86949eb..34e838c 100644 --- a/src/libui_sdl/main.cpp +++ b/src/libui_sdl/main.cpp @@ -1088,7 +1088,6 @@ void OnAreaMouseEvent(uiAreaHandler* handler, uiArea* area, uiAreaMouseEvent* ev if (Touching && (evt->Up == 1)) { Touching = false; - NDS::ReleaseKey(16+6); NDS::ReleaseScreen(); } else if (!Touching && (evt->Down == 1) && @@ -1096,7 +1095,6 @@ void OnAreaMouseEvent(uiAreaHandler* handler, uiArea* area, uiAreaMouseEvent* ev (x < (BottomScreenRect.X+BottomScreenRect.Width)) && (y < (BottomScreenRect.Y+BottomScreenRect.Height))) { Touching = true; - NDS::PressKey(16+6); } if (Touching) -- cgit v1.2.3 From a9f36929e05e40abc9e91567443199b07530638f Mon Sep 17 00:00:00 2001 From: Arisotura Date: Sun, 4 Aug 2019 14:34:33 +0200 Subject: TSC: add backwards-compatibility --- src/DSi_SPI_TSC.cpp | 98 ++++++++++++++++++++++++++++++++++++++--------------- src/NDS.cpp | 4 +-- src/NDS.h | 2 ++ src/SPI.h | 3 ++ 4 files changed, 77 insertions(+), 30 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/DSi_SPI_TSC.cpp b/src/DSi_SPI_TSC.cpp index 2ec9858..507005b 100644 --- a/src/DSi_SPI_TSC.cpp +++ b/src/DSi_SPI_TSC.cpp @@ -19,6 +19,7 @@ #include #include #include "DSi.h" +#include "SPI.h" #include "DSi_SPI_TSC.h" @@ -27,10 +28,11 @@ namespace DSi_SPI_TSC u32 DataPos; u8 Index; -u8 Mode; +u8 Bank; u8 Data; -u8 Mode3Regs[0x80]; +u8 Bank3Regs[0x80]; +u8 TSCMode; u16 TouchX, TouchY; @@ -48,21 +50,23 @@ void Reset() { DataPos = 0; - Mode = 0; + Bank = 0; Index = 0; Data = 0; - memset(Mode3Regs, 0, 0x80); - Mode3Regs[0x02] = 0x18; - Mode3Regs[0x03] = 0x87; - Mode3Regs[0x04] = 0x22; - Mode3Regs[0x05] = 0x04; - Mode3Regs[0x06] = 0x20; - Mode3Regs[0x09] = 0x40; - Mode3Regs[0x0E] = 0xAD; - Mode3Regs[0x0F] = 0xA0; - Mode3Regs[0x10] = 0x88; - Mode3Regs[0x11] = 0x81; + memset(Bank3Regs, 0, 0x80); + Bank3Regs[0x02] = 0x18; + Bank3Regs[0x03] = 0x87; + Bank3Regs[0x04] = 0x22; + Bank3Regs[0x05] = 0x04; + Bank3Regs[0x06] = 0x20; + Bank3Regs[0x09] = 0x40; + Bank3Regs[0x0E] = 0xAD; + Bank3Regs[0x0F] = 0xA0; + Bank3Regs[0x10] = 0x88; + Bank3Regs[0x11] = 0x81; + + TSCMode = 0x01; // DSi mode } void DoSavestate(Savestate* file) @@ -79,10 +83,17 @@ void DoSavestate(Savestate* file) void SetTouchCoords(u16 x, u16 y) { + if (TSCMode == 0x00) + { + if (y == 0xFFF) NDS::KeyInput |= (1 << (16+6)); + else NDS::KeyInput &= ~(1 << (16+6)); + return SPI_TSC::SetTouchCoords(x, y); + } + TouchX = x; TouchY = y; -printf("touching: %d/%d\n", x, y); - u8 oldpress = Mode3Regs[0x0E] & 0x01; + + u8 oldpress = Bank3Regs[0x0E] & 0x01; if (y == 0xFFF) { @@ -92,8 +103,9 @@ printf("touching: %d/%d\n", x, y); TouchX = 0x7000; TouchY = 0x7000; - Mode3Regs[0x09] = 0x40; - Mode3Regs[0x0E] |= 0x01; + Bank3Regs[0x09] = 0x40; + //Bank3Regs[0x09] &= ~0x80; + Bank3Regs[0x0E] |= 0x01; } else { @@ -102,11 +114,12 @@ printf("touching: %d/%d\n", x, y); TouchX <<= 4; TouchY <<= 4; - Mode3Regs[0x09] = 0x80; - Mode3Regs[0x0E] &= ~0x01; + Bank3Regs[0x09] = 0x80; + //Bank3Regs[0x09] |= 0x80; + Bank3Regs[0x0E] &= ~0x01; } - if (oldpress ^ (Mode3Regs[0x0E] & 0x01)) + if (oldpress ^ (Bank3Regs[0x0E] & 0x01)) { TouchX |= 0x8000; TouchY |= 0x8000; @@ -115,16 +128,23 @@ printf("touching: %d/%d\n", x, y); void MicInputFrame(s16* data, int samples) { - // TODO: forward to DS-mode TSC if needed + if (TSCMode == 0x00) return SPI_TSC::MicInputFrame(data, samples); + + // otherwise we don't handle mic input + // TODO: handle it where it needs to be } u8 Read() { + if (TSCMode == 0x00) return SPI_TSC::Read(); + return Data; } void Write(u8 val, u32 hold) { + if (TSCMode == 0x00) return SPI_TSC::Write(val, hold); + #define READWRITE(var) { if (Index & 0x01) Data = var; else var = val; } if (DataPos == 0) @@ -137,18 +157,18 @@ void Write(u8 val, u32 hold) if (id == 0) { - READWRITE(Mode); + READWRITE(Bank); } - else if (Mode == 0x03) + else if (Bank == 0x03) { - if (Index & 0x01) Data = Mode3Regs[id]; + if (Index & 0x01) Data = Bank3Regs[id]; else { if (id == 0x0D || id == 0x0E) - Mode3Regs[id] = (Mode3Regs[id] & 0x03) | (val & 0xFC); + Bank3Regs[id] = (Bank3Regs[id] & 0x03) | (val & 0xFC); } } - else if ((Mode == 0xFC) && (Index & 0x01)) + else if ((Bank == 0xFC) && (Index & 0x01)) { if (id < 0x0B) { @@ -174,9 +194,31 @@ void Write(u8 val, u32 hold) Data = 0; } } + else if (Bank == 0xFF) + { + if (id == 0x05) + { + // TSC mode register + // 01: normal (DSi) mode + // 00: compatibility (DS) mode + + if (Index & 0x01) Data = TSCMode; + else + { + TSCMode = val; + if (TSCMode == 0x00) + { + printf("DSi_SPI_TSC: DS-compatibility mode\n"); + DataPos = 0; + NDS::KeyInput |= (1 << (16+6)); + return; + } + } + } + } else { - printf("DSi_SPI_TSC: unknown IO, mode=%02X, index=%02X (%02X %s)\n", Mode, Index, Index>>1, (Index&1)?"read":"write"); + printf("DSi_SPI_TSC: unknown IO, bank=%02X, index=%02X (%02X %s)\n", Bank, Index, Index>>1, (Index&1)?"read":"write"); } Index += (1<<1); // increment index diff --git a/src/NDS.cpp b/src/NDS.cpp index da7f9f9..42b5d9f 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -580,7 +580,7 @@ bool DoSavestate_Scheduler(Savestate* file) } if (funcid == -1) { - printf("savestate: VERY BAD!!!!! FUNCTION POINTER FOR EVENT %d NOT IN HACKY LIST. CANNOT SAVE. SMACK STAPLEBUTTER.\n", i); + printf("savestate: VERY BAD!!!!! FUNCTION POINTER FOR EVENT %d NOT IN HACKY LIST. CANNOT SAVE. SMACK ARISOTURA.\n", i); return false; } } @@ -694,7 +694,7 @@ bool DoSavestate(Savestate* file) for (int i = 0; i < 8; i++) DMAs[i]->DoSavestate(file); - file->Var8(&WRAMCnt); + file->Var8(&WRAMCnt); // FIXME!!!!! if (!file->Saving) { diff --git a/src/NDS.h b/src/NDS.h index d391cf7..309b16a 100644 --- a/src/NDS.h +++ b/src/NDS.h @@ -163,6 +163,8 @@ extern u8 ARM7BIOS[0x10000]; extern u8 MainRAM[MAIN_RAM_SIZE]; +extern u32 KeyInput; + bool Init(); void DeInit(); void Reset(); diff --git a/src/SPI.h b/src/SPI.h index 44de876..73fd57e 100644 --- a/src/SPI.h +++ b/src/SPI.h @@ -39,6 +39,9 @@ namespace SPI_TSC void SetTouchCoords(u16 x, u16 y); void MicInputFrame(s16* data, int samples); +u8 Read(); +void Write(u8 val, u32 hold); + } namespace SPI -- cgit v1.2.3 From 4d3d8433cbfc7916a344c18c491da401f6e32bfb Mon Sep 17 00:00:00 2001 From: Arisotura Date: Mon, 5 Aug 2019 19:52:03 +0200 Subject: * add old DS BIOSes and 04004000 BIOS-switch fixes audio issues when running DS games * attempt adding other fun shit like dynamic RAM size, but that mostly went nowhere for now --- src/DSi.cpp | 191 ++++++++++++++++++++++++++++++++++++++++++++++++++---------- src/DSi.h | 3 + src/NDS.cpp | 154 ++++++++++++++++++++++++++---------------------- src/NDS.h | 11 ++-- 4 files changed, 251 insertions(+), 108 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index 771f67b..9f07fa1 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -45,11 +45,15 @@ namespace DSi u32 BootAddr[2]; +u16 SCFG_BIOS; u16 SCFG_Clock9; u16 SCFG_Clock7; u32 SCFG_EXT[2]; u32 SCFG_MC; +u8 ARM9iBIOS[0x10000]; +u8 ARM7iBIOS[0x10000]; + u32 MBK[2][9]; u8 NWRAM_A[0x40000]; @@ -131,6 +135,7 @@ void Reset() SDMMC->Reset(); SDIO->Reset(); + SCFG_BIOS = 0x0101; // TODO: should be zero when booting from BIOS SCFG_Clock9 = 0x0187; // CHECKME SCFG_Clock7 = 0x0187; SCFG_EXT[0] = 0x8307F100; @@ -160,18 +165,21 @@ bool LoadBIOS() FILE* f; u32 i; + memset(ARM9iBIOS, 0, 0x10000); + memset(ARM7iBIOS, 0, 0x10000); + f = Platform::OpenLocalFile("bios9i.bin", "rb"); if (!f) { printf("ARM9i BIOS not found\n"); for (i = 0; i < 16; i++) - ((u32*)NDS::ARM9BIOS)[i] = 0xE7FFDEFF; + ((u32*)ARM9iBIOS)[i] = 0xE7FFDEFF; } else { fseek(f, 0, SEEK_SET); - fread(NDS::ARM9BIOS, 0x10000, 1, f); + fread(ARM9iBIOS, 0x10000, 1, f); printf("ARM9i BIOS loaded\n"); fclose(f); @@ -183,22 +191,25 @@ bool LoadBIOS() printf("ARM7i BIOS not found\n"); for (i = 0; i < 16; i++) - ((u32*)NDS::ARM7BIOS)[i] = 0xE7FFDEFF; + ((u32*)ARM7iBIOS)[i] = 0xE7FFDEFF; } else { // TODO: check if the first 32 bytes are crapoed fseek(f, 0, SEEK_SET); - fread(NDS::ARM7BIOS, 0x10000, 1, f); + fread(ARM7iBIOS, 0x10000, 1, f); printf("ARM7i BIOS loaded\n"); fclose(f); } // herp - *(u32*)&NDS::ARM9BIOS[0] = 0xEAFFFFFE; - *(u32*)&NDS::ARM7BIOS[0] = 0xEAFFFFFE; + *(u32*)&ARM9iBIOS[0] = 0xEAFFFFFE; + *(u32*)&ARM7iBIOS[0] = 0xEAFFFFFE; + + // TODO!!!! + // hax the upper 32K out of the goddamn DSi return true; } @@ -582,6 +593,22 @@ void MapNWRAMRange(u32 cpu, u32 num, u32 val) } +void Set_SCFG_Clock9(u16 val) +{ + SCFG_Clock9 = val & 0x0187; + return; + + NDS::ARM9Timestamp >>= NDS::ARM9ClockShift; + + printf("CLOCK9=%04X\n", val); + SCFG_Clock9 = val & 0x0187; + + if (SCFG_Clock9 & (1<<0)) NDS::ARM9ClockShift = 2; + else NDS::ARM9ClockShift = 1; + NDS::ARM9Timestamp <<= NDS::ARM9ClockShift; + NDS::ARM9->UpdateRegionTimings(0x00000000, 0xFFFFFFFF); +} + void Set_SCFG_MC(u32 val) { u32 oldslotstatus = SCFG_MC & 0xC; @@ -600,6 +627,14 @@ void Set_SCFG_MC(u32 val) u8 ARM9Read8(u32 addr) { + if ((addr >= 0xFFFF0000) && (!(SCFG_BIOS & (1<<1)))) + { + if ((addr >= 0xFFFF8000) && (SCFG_BIOS & (1<<0))) + return 0xFF; + + return *(u8*)&ARM9iBIOS[addr & 0xFFFF]; + } + switch (addr & 0xFF000000) { case 0x03000000: @@ -629,6 +664,14 @@ u8 ARM9Read8(u32 addr) u16 ARM9Read16(u32 addr) { + if ((addr >= 0xFFFF0000) && (!(SCFG_BIOS & (1<<1)))) + { + if ((addr >= 0xFFFF8000) && (SCFG_BIOS & (1<<0))) + return 0xFFFF; + + return *(u16*)&ARM9iBIOS[addr & 0xFFFF]; + } + switch (addr & 0xFF000000) { case 0x03000000: @@ -658,6 +701,14 @@ u16 ARM9Read16(u32 addr) u32 ARM9Read32(u32 addr) { + if ((addr >= 0xFFFF0000) && (!(SCFG_BIOS & (1<<1)))) + { + if ((addr >= 0xFFFF8000) && (SCFG_BIOS & (1<<0))) + return 0xFFFFFFFF; + + return *(u32*)&ARM9iBIOS[addr & 0xFFFF]; + } + switch (addr & 0xFF000000) { case 0x03000000: @@ -790,14 +841,28 @@ bool ARM9GetMemRegion(u32 addr, bool write, NDS::MemRegion* region) { case 0x02000000: region->Mem = NDS::MainRAM; - region->Mask = MAIN_RAM_SIZE-1; + region->Mask = NDS::MainRAMMask; return true; } if ((addr & 0xFFFF0000) == 0xFFFF0000 && !write) { - region->Mem = NDS::ARM9BIOS; - region->Mask = 0xFFFF; + if (SCFG_BIOS & (1<<1)) + { + if (addr >= 0xFFFF1000) + { + region->Mem = NULL; + return false; + } + + region->Mem = NDS::ARM9BIOS; + region->Mask = 0xFFF; + } + else + { + region->Mem = ARM9iBIOS; + region->Mask = 0xFFFF; + } return true; } @@ -809,6 +874,18 @@ bool ARM9GetMemRegion(u32 addr, bool write, NDS::MemRegion* region) u8 ARM7Read8(u32 addr) { + if ((addr < 0x00010000) && (!(SCFG_BIOS & (1<<9)))) + { + if ((addr >= 0x00008000) && (SCFG_BIOS & (1<<8))) + return 0xFF; + if (NDS::ARM7->R[15] >= 0x00010000) + return 0xFF; + if (addr < NDS::ARM7BIOSProt && NDS::ARM7->R[15] >= NDS::ARM7BIOSProt) + return 0xFF; + + return *(u8*)&ARM7iBIOS[addr]; + } + switch (addr & 0xFF800000) { case 0x03000000: @@ -838,6 +915,18 @@ u8 ARM7Read8(u32 addr) u16 ARM7Read16(u32 addr) { + if ((addr < 0x00010000) && (!(SCFG_BIOS & (1<<9)))) + { + if ((addr >= 0x00008000) && (SCFG_BIOS & (1<<8))) + return 0xFFFF; + if (NDS::ARM7->R[15] >= 0x00010000) + return 0xFFFF; + if (addr < NDS::ARM7BIOSProt && NDS::ARM7->R[15] >= NDS::ARM7BIOSProt) + return 0xFFFF; + + return *(u16*)&ARM7iBIOS[addr]; + } + switch (addr & 0xFF800000) { case 0x03000000: @@ -867,6 +956,18 @@ u16 ARM7Read16(u32 addr) u32 ARM7Read32(u32 addr) { + if ((addr < 0x00010000) && (!(SCFG_BIOS & (1<<9)))) + { + if ((addr >= 0x00008000) && (SCFG_BIOS & (1<<8))) + return 0xFFFFFFFF; + if (NDS::ARM7->R[15] >= 0x00010000) + return 0xFFFFFFFF; + if (addr < NDS::ARM7BIOSProt && NDS::ARM7->R[15] >= NDS::ARM7BIOSProt) + return 0xFFFFFFFF; + + return *(u32*)&ARM7iBIOS[addr]; + } + switch (addr & 0xFF800000) { case 0x03000000: @@ -1000,7 +1101,7 @@ bool ARM7GetMemRegion(u32 addr, bool write, NDS::MemRegion* region) case 0x02000000: case 0x02800000: region->Mem = NDS::MainRAM; - region->Mask = MAIN_RAM_SIZE-1; + region->Mask = NDS::MainRAMMask; return true; } @@ -1040,7 +1141,7 @@ u8 ARM9IORead8(u32 addr) { switch (addr) { - case 0x04004000: return 1; + case 0x04004000: return SCFG_BIOS & 0xFF; CASE_READ8_32BIT(0x04004040, MBK[0][0]) CASE_READ8_32BIT(0x04004044, MBK[0][1]) @@ -1060,6 +1161,7 @@ u16 ARM9IORead16(u32 addr) { switch (addr) { + case 0x04004000: return SCFG_BIOS & 0xFF; case 0x04004004: return SCFG_Clock9; case 0x04004010: return SCFG_MC & 0xFFFF; @@ -1081,6 +1183,7 @@ u32 ARM9IORead32(u32 addr) { switch (addr) { + case 0x04004000: return SCFG_BIOS & 0xFF; case 0x04004008: return SCFG_EXT[0]; case 0x04004010: return SCFG_MC & 0xFFFF; @@ -1172,9 +1275,7 @@ void ARM9IOWrite16(u32 addr, u16 val) switch (addr) { case 0x04004004: - // TODO: actually change clock! - printf("CLOCK9=%04X\n", val); - SCFG_Clock9 = val & 0x0187; + Set_SCFG_Clock9(val); return; case 0x04004040: @@ -1232,6 +1333,20 @@ void ARM9IOWrite32(u32 addr, u32 val) SCFG_EXT[1] &= ~0x0000F080; SCFG_EXT[1] |= (val & 0x0000F080); printf("SCFG_EXT = %08X / %08X (val9 %08X)\n", SCFG_EXT[0], SCFG_EXT[1], val); + /*switch ((SCFG_EXT[0] >> 14) & 0x3) + { + case 0: + case 1: + NDS::MainRAMMask = 0x3FFFFF; + printf("RAM: 4MB\n"); + break; + case 2: + case 3: // TODO: debug console w/ 32MB? + NDS::MainRAMMask = 0xFFFFFF; + printf("RAM: 16MB\n"); + break; + }*/ + printf("from %08X, ARM7 %08X, %08X\n", NDS::GetPC(0), NDS::GetPC(1), NDS::ARM7->R[1]); return; case 0x04004040: @@ -1307,8 +1422,8 @@ u8 ARM7IORead8(u32 addr) { switch (addr) { - case 0x04004000: return 0x01; - case 0x04004001: return 0x01; + case 0x04004000: return SCFG_BIOS & 0xFF; + case 0x04004001: return SCFG_BIOS >> 8; CASE_READ8_32BIT(0x04004040, MBK[1][0]) CASE_READ8_32BIT(0x04004044, MBK[1][1]) @@ -1323,14 +1438,14 @@ u8 ARM7IORead8(u32 addr) case 0x04004500: return DSi_I2C::ReadData(); case 0x04004501: return DSi_I2C::Cnt; - case 0x04004D00: return ConsoleID & 0xFF; - case 0x04004D01: return (ConsoleID >> 8) & 0xFF; - case 0x04004D02: return (ConsoleID >> 16) & 0xFF; - case 0x04004D03: return (ConsoleID >> 24) & 0xFF; - case 0x04004D04: return (ConsoleID >> 32) & 0xFF; - case 0x04004D05: return (ConsoleID >> 40) & 0xFF; - case 0x04004D06: return (ConsoleID >> 48) & 0xFF; - case 0x04004D07: return ConsoleID >> 56; + case 0x04004D00: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID & 0xFF; + case 0x04004D01: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 8) & 0xFF; + case 0x04004D02: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 16) & 0xFF; + case 0x04004D03: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 24) & 0xFF; + case 0x04004D04: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 32) & 0xFF; + case 0x04004D05: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 40) & 0xFF; + case 0x04004D06: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 48) & 0xFF; + case 0x04004D07: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID >> 56; case 0x04004D08: return 0; } @@ -1344,6 +1459,7 @@ u16 ARM7IORead16(u32 addr) case 0x04000218: return NDS::IE2; case 0x0400021C: return NDS::IF2; + case 0x04004000: return SCFG_BIOS; case 0x04004004: return SCFG_Clock7; case 0x04004006: return 0; // JTAG register case 0x04004010: return SCFG_MC & 0xFFFF; @@ -1358,10 +1474,10 @@ u16 ARM7IORead16(u32 addr) CASE_READ16_32BIT(0x0400405C, MBK[1][7]) CASE_READ16_32BIT(0x04004060, MBK[1][8]) - case 0x04004D00: return ConsoleID & 0xFFFF; - case 0x04004D02: return (ConsoleID >> 16) & 0xFFFF; - case 0x04004D04: return (ConsoleID >> 32) & 0xFFFF; - case 0x04004D06: return ConsoleID >> 48; + case 0x04004D00: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID & 0xFFFF; + case 0x04004D02: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 16) & 0xFFFF; + case 0x04004D04: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 32) & 0xFFFF; + case 0x04004D06: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID >> 48; case 0x04004D08: return 0; } @@ -1384,6 +1500,7 @@ u32 ARM7IORead32(u32 addr) case 0x04000218: return NDS::IE2; case 0x0400021C: return NDS::IF2; + case 0x04004000: return SCFG_BIOS; case 0x04004008: return SCFG_EXT[1]; case 0x04004010: return SCFG_MC; @@ -1430,8 +1547,8 @@ u32 ARM7IORead32(u32 addr) case 0x04004400: return DSi_AES::ReadCnt(); case 0x0400440C: return DSi_AES::ReadOutputFIFO(); - case 0x04004D00: return ConsoleID & 0xFFFFFFFF; - case 0x04004D04: return ConsoleID >> 32; + case 0x04004D00: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID & 0xFFFFFFFF; + case 0x04004D04: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID >> 32; case 0x04004D08: return 0; } @@ -1453,6 +1570,13 @@ void ARM7IOWrite8(u32 addr, u8 val) { switch (addr) { + case 0x04004000: + SCFG_BIOS |= (val & 0x03); + return; + case 0x04004001: + SCFG_BIOS |= ((val & 0x07) << 8); + return; + case 0x04004500: DSi_I2C::WriteData(val); return; case 0x04004501: DSi_I2C::WriteCnt(val); return; } @@ -1467,10 +1591,12 @@ void ARM7IOWrite16(u32 addr, u16 val) case 0x04000218: NDS::IE2 = (val & 0x7FF7); NDS::UpdateIRQ(1); return; case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return; + case 0x04004000: + SCFG_BIOS |= (val & 0x0703); + return; case 0x04004004: SCFG_Clock7 = val & 0x0187; return; - case 0x04004010: Set_SCFG_MC((SCFG_MC & 0xFFFF0000) | val); return; @@ -1497,6 +1623,9 @@ void ARM7IOWrite32(u32 addr, u32 val) case 0x04000218: NDS::IE2 = (val & 0x7FF7); NDS::UpdateIRQ(1); return; case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return; + case 0x04004000: + SCFG_BIOS |= (val & 0x0703); + return; case 0x04004008: SCFG_EXT[0] &= ~0x03000000; SCFG_EXT[0] |= (val & 0x03000000); diff --git a/src/DSi.h b/src/DSi.h index b29cdb5..bd37550 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -25,6 +25,9 @@ namespace DSi { +extern u8 ARM9iBIOS[0x10000]; +extern u8 ARM7iBIOS[0x10000]; + extern u8 eMMC_CID[16]; extern u64 ConsoleID; diff --git a/src/NDS.cpp b/src/NDS.cpp index 42b5d9f..95265cf 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -86,10 +86,11 @@ u32 SchedListMask; u32 CPUStop; -u8 ARM9BIOS[0x10000]; -u8 ARM7BIOS[0x10000]; +u8 ARM9BIOS[0x1000]; +u8 ARM7BIOS[0x4000]; -u8 MainRAM[MAIN_RAM_SIZE]; +u8 MainRAM[0x1000000]; +u32 MainRAMMask; u8 SharedWRAM[0x8000]; u8 WRAMCnt; @@ -235,7 +236,11 @@ void SetARM9RegionTimings(u32 addrstart, u32 addrend, int buswidth, int nonseq, ARM9MemTimings[i][3] = S32; } - ARM9->UpdateRegionTimings(addrstart<<14, addrend<<14); + addrstart <<= 14; + addrend <<= 14; + if (!addrend) addrend = 0xFFFFFFFF; + + ARM9->UpdateRegionTimings(addrstart, addrend); } void SetARM7RegionTimings(u32 addrstart, u32 addrend, int buswidth, int nonseq, int seq) @@ -395,53 +400,58 @@ void Reset() LastSysClockCycles = 0; - memset(ARM9BIOS, 0, 0x10000); - memset(ARM7BIOS, 0, 0x10000); + memset(ARM9BIOS, 0, 0x1000); + memset(ARM7BIOS, 0, 0x4000); - if (true) + // DS BIOSes are always loaded, even in DSi mode + // we need them for DS-compatible mode + + f = Platform::OpenLocalFile("bios9.bin", "rb"); + if (!f) { - DSi::LoadBIOS(); - DSi::LoadNAND(); + printf("ARM9 BIOS not found\n"); - ARM9ClockShift = 2; + for (i = 0; i < 16; i++) + ((u32*)ARM9BIOS)[i] = 0xE7FFDEFF; } else { - f = Platform::OpenLocalFile("bios9.bin", "rb"); - if (!f) - { - printf("ARM9 BIOS not found\n"); + fseek(f, 0, SEEK_SET); + fread(ARM9BIOS, 0x1000, 1, f); - for (i = 0; i < 16; i++) - ((u32*)ARM9BIOS)[i] = 0xE7FFDEFF; - } - else - { - fseek(f, 0, SEEK_SET); - fread(ARM9BIOS, 0x1000, 1, f); + printf("ARM9 BIOS loaded\n"); + fclose(f); + } - printf("ARM9 BIOS loaded\n"); - fclose(f); - } + f = Platform::OpenLocalFile("bios7.bin", "rb"); + if (!f) + { + printf("ARM7 BIOS not found\n"); - f = Platform::OpenLocalFile("bios7.bin", "rb"); - if (!f) - { - printf("ARM7 BIOS not found\n"); + for (i = 0; i < 16; i++) + ((u32*)ARM7BIOS)[i] = 0xE7FFDEFF; + } + else + { + fseek(f, 0, SEEK_SET); + fread(ARM7BIOS, 0x4000, 1, f); - for (i = 0; i < 16; i++) - ((u32*)ARM7BIOS)[i] = 0xE7FFDEFF; - } - else - { - fseek(f, 0, SEEK_SET); - fread(ARM7BIOS, 0x4000, 1, f); + printf("ARM7 BIOS loaded\n"); + fclose(f); + } - printf("ARM7 BIOS loaded\n"); - fclose(f); - } + if (true) + { + DSi::LoadBIOS(); + DSi::LoadNAND(); + ARM9ClockShift = 2; + MainRAMMask = 0xFFFFFF; + } + else + { ARM9ClockShift = 1; + MainRAMMask = 0x3FFFFF; } ARM9Timestamp = 0; ARM9Target = 0; @@ -450,7 +460,7 @@ void Reset() InitTimings(); - memset(MainRAM, 0, MAIN_RAM_SIZE); + memset(MainRAM, 0, 0x1000000); memset(SharedWRAM, 0, 0x8000); memset(ARM7WRAM, 0, 0x10000); @@ -1608,36 +1618,36 @@ void debug(u32 param) fwrite(&val, 4, 1, shit); } fclose(shit);*/ - /*FILE* - shit = fopen("debug/dump9.bin", "wb"); + FILE* + /*shit = fopen("debug/dump9.bin", "wb"); for (u32 i = 0x02000000; i < 0x04000000; i+=4) { u32 val = DSi::ARM9Read32(i); fwrite(&val, 4, 1, shit); } - fclose(shit); - shit = fopen("debug/dump7.bin", "wb"); + fclose(shit);*/ + shit = fopen("debug/dump7_2.bin", "wb"); for (u32 i = 0x02000000; i < 0x04000000; i+=4) { u32 val = DSi::ARM7Read32(i); fwrite(&val, 4, 1, shit); } - fclose(shit);*/ + fclose(shit); } u8 ARM9Read8(u32 addr) { - if ((addr & 0xFFFF0000) == 0xFFFF0000) + if ((addr & 0xFFFFF000) == 0xFFFF0000) { - return *(u8*)&ARM9BIOS[addr & 0xFFFF]; + return *(u8*)&ARM9BIOS[addr & 0xFFF]; } switch (addr & 0xFF000000) { case 0x02000000: - return *(u8*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)]; + return *(u8*)&MainRAM[addr & MainRAMMask]; case 0x03000000: if (SWRAM_ARM9) @@ -1690,15 +1700,15 @@ u8 ARM9Read8(u32 addr) u16 ARM9Read16(u32 addr) { - if ((addr & 0xFFFF0000) == 0xFFFF0000) + if ((addr & 0xFFFFF000) == 0xFFFF0000) { - return *(u16*)&ARM9BIOS[addr & 0xFFFF]; + return *(u16*)&ARM9BIOS[addr & 0xFFF]; } switch (addr & 0xFF000000) { case 0x02000000: - return *(u16*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)]; + return *(u16*)&MainRAM[addr & MainRAMMask]; case 0x03000000: if (SWRAM_ARM9) @@ -1751,15 +1761,15 @@ u16 ARM9Read16(u32 addr) u32 ARM9Read32(u32 addr) { - if ((addr & 0xFFFF0000) == 0xFFFF0000) + if ((addr & 0xFFFFF000) == 0xFFFF0000) { - return *(u32*)&ARM9BIOS[addr & 0xFFFF]; + return *(u32*)&ARM9BIOS[addr & 0xFFF]; } switch (addr & 0xFF000000) { case 0x02000000: - return *(u32*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)]; + return *(u32*)&MainRAM[addr & MainRAMMask]; case 0x03000000: if (SWRAM_ARM9) @@ -1815,7 +1825,7 @@ void ARM9Write8(u32 addr, u8 val) switch (addr & 0xFF000000) { case 0x02000000: - *(u8*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val; + *(u8*)&MainRAM[addr & MainRAMMask] = val; return; case 0x03000000: @@ -1844,7 +1854,7 @@ void ARM9Write16(u32 addr, u16 val) switch (addr & 0xFF000000) { case 0x02000000: - *(u16*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val; + *(u16*)&MainRAM[addr & MainRAMMask] = val; return; case 0x03000000: @@ -1887,7 +1897,7 @@ void ARM9Write32(u32 addr, u32 val) switch (addr & 0xFF000000) { case 0x02000000: - *(u32*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val; + *(u32*)&MainRAM[addr & MainRAMMask] = val; return ; case 0x03000000: @@ -1931,7 +1941,7 @@ bool ARM9GetMemRegion(u32 addr, bool write, MemRegion* region) { case 0x02000000: region->Mem = MainRAM; - region->Mask = MAIN_RAM_SIZE-1; + region->Mask = MainRAMMask; return true; case 0x03000000: @@ -1959,10 +1969,10 @@ bool ARM9GetMemRegion(u32 addr, bool write, MemRegion* region) u8 ARM7Read8(u32 addr) { - if (addr < 0x00010000) + if (addr < 0x00004000) { // TODO: check the boundary? is it 4000 or higher on regular DS? - if (ARM7->R[15] >= 0x00010000) + if (ARM7->R[15] >= 0x00004000) return 0xFF; if (addr < ARM7BIOSProt && ARM7->R[15] >= ARM7BIOSProt) return 0xFF; @@ -1974,7 +1984,7 @@ u8 ARM7Read8(u32 addr) { case 0x02000000: case 0x02800000: - return *(u8*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)]; + return *(u8*)&MainRAM[addr & MainRAMMask]; case 0x03000000: if (SWRAM_ARM7) @@ -2016,9 +2026,9 @@ u8 ARM7Read8(u32 addr) u16 ARM7Read16(u32 addr) { - if (addr < 0x00010000) + if (addr < 0x00004000) { - if (ARM7->R[15] >= 0x00010000) + if (ARM7->R[15] >= 0x00004000) return 0xFFFF; if (addr < ARM7BIOSProt && ARM7->R[15] >= ARM7BIOSProt) return 0xFFFF; @@ -2030,7 +2040,7 @@ u16 ARM7Read16(u32 addr) { case 0x02000000: case 0x02800000: - return *(u16*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)]; + return *(u16*)&MainRAM[addr & MainRAMMask]; case 0x03000000: if (SWRAM_ARM7) @@ -2079,9 +2089,9 @@ u16 ARM7Read16(u32 addr) u32 ARM7Read32(u32 addr) { - if (addr < 0x00010000) + if (addr < 0x00004000) { - if (ARM7->R[15] >= 0x00010000) + if (ARM7->R[15] >= 0x00004000) return 0xFFFFFFFF; if (addr < ARM7BIOSProt && ARM7->R[15] >= ARM7BIOSProt) return 0xFFFFFFFF; @@ -2093,7 +2103,7 @@ u32 ARM7Read32(u32 addr) { case 0x02000000: case 0x02800000: - return *(u32*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)]; + return *(u32*)&MainRAM[addr & MainRAMMask]; case 0x03000000: if (SWRAM_ARM7) @@ -2146,7 +2156,7 @@ void ARM7Write8(u32 addr, u8 val) { case 0x02000000: case 0x02800000: - *(u8*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val; + *(u8*)&MainRAM[addr & MainRAMMask] = val; return; case 0x03000000: @@ -2184,7 +2194,7 @@ void ARM7Write16(u32 addr, u16 val) { case 0x02000000: case 0x02800000: - *(u16*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val; + *(u16*)&MainRAM[addr & MainRAMMask] = val; return; case 0x03000000: @@ -2230,7 +2240,7 @@ void ARM7Write32(u32 addr, u32 val) { case 0x02000000: case 0x02800000: - *(u32*)&MainRAM[addr & (MAIN_RAM_SIZE - 1)] = val; + *(u32*)&MainRAM[addr & MainRAMMask] = val; return; case 0x03000000: @@ -2278,7 +2288,7 @@ bool ARM7GetMemRegion(u32 addr, bool write, MemRegion* region) case 0x02000000: case 0x02800000: region->Mem = MainRAM; - region->Mask = MAIN_RAM_SIZE-1; + region->Mask = MainRAMMask; return true; case 0x03000000: @@ -2555,7 +2565,7 @@ u32 ARM9IORead32(u32 addr) case 0x04000130: return (KeyInput & 0xFFFF) | (KeyCnt << 16); - case 0x04000180: return IPCSync9; + case 0x04000180: /*printf("ARM9 read IPCSYNC: %04X\n", IPCSync9);*/ return IPCSync9; case 0x040001A0: return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16); case 0x040001A4: return NDSCart::ROMCnt; @@ -2764,6 +2774,7 @@ void ARM9IOWrite16(u32 addr, u16 val) return; case 0x04000180: + printf("ARM9 IPCSYNC = %04X\n", val); IPCSync7 &= 0xFFF0; IPCSync7 |= ((val & 0x0F00) >> 8); IPCSync9 &= 0xB0FF; @@ -3348,6 +3359,7 @@ void ARM7IOWrite16(u32 addr, u16 val) case 0x04000138: RTC::Write(val, false); return; case 0x04000180: + printf("ARM7 IPCSYNC = %04X\n", val); IPCSync9 &= 0xFFF0; IPCSync9 |= ((val & 0x0F00) >> 8); IPCSync7 &= 0xB0FF; diff --git a/src/NDS.h b/src/NDS.h index 309b16a..1b572ea 100644 --- a/src/NDS.h +++ b/src/NDS.h @@ -155,13 +155,12 @@ extern u16 ExMemCnt[2]; extern u8 ROMSeed0[2*8]; extern u8 ROMSeed1[2*8]; -extern u8 ARM9BIOS[0x10000]; -extern u8 ARM7BIOS[0x10000]; +extern u8 ARM9BIOS[0x1000]; +extern u8 ARM7BIOS[0x4000]; +extern u16 ARM7BIOSProt; -//#define MAIN_RAM_SIZE 0x400000 -#define MAIN_RAM_SIZE 0x1000000 - -extern u8 MainRAM[MAIN_RAM_SIZE]; +extern u8 MainRAM[0x1000000]; +extern u32 MainRAMMask; extern u32 KeyInput; -- cgit v1.2.3 From e82364f010f6ad4e4883c241a05a4aac10cd75d6 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Sat, 19 Oct 2019 16:03:59 +0200 Subject: * some fixes to SD controller support, make it clear that there is no SD inserted, makes Flipnote work somewhat better * immediately clear AES busy flag when the block count is zero (occurs when loading DSi cart games) * implement NDMA start modes that have an old-DMA equivalent (except for GXFIFO mode) now it boots DSi carts! --- src/DSi.cpp | 16 +++++++++- src/DSi.h | 1 + src/DSi_AES.cpp | 90 +++++++++++++++++++++++++------------------------------- src/DSi_NDMA.cpp | 6 ++-- src/DSi_SD.cpp | 62 +++++++++++++++++++++++++++++++++----- src/NDS.cpp | 42 ++++++++++++++++++++++++++ src/NDSCart.cpp | 4 +-- 7 files changed, 159 insertions(+), 62 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index 9f07fa1..ef4e6da 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -411,6 +411,16 @@ void StallNDMAs() // TODO } +bool NDMAsInMode(u32 cpu, u32 mode) +{ + cpu <<= 2; + if (NDMAs[cpu+0]->IsInMode(mode)) return true; + if (NDMAs[cpu+1]->IsInMode(mode)) return true; + if (NDMAs[cpu+2]->IsInMode(mode)) return true; + if (NDMAs[cpu+3]->IsInMode(mode)) return true; + return false; +} + bool NDMAsRunning(u32 cpu) { cpu <<= 2; @@ -1156,7 +1166,7 @@ u8 ARM9IORead8(u32 addr) return NDS::ARM9IORead8(addr); } - +//u16 dicks = 0; u16 ARM9IORead16(u32 addr) { switch (addr) @@ -1174,6 +1184,8 @@ u16 ARM9IORead16(u32 addr) CASE_READ16_32BIT(0x04004058, MBK[0][6]) CASE_READ16_32BIT(0x0400405C, MBK[0][7]) CASE_READ16_32BIT(0x04004060, MBK[0][8]) + + //case 0x04004202: return dicks & 0xEF1F; } return NDS::ARM9IORead16(addr); @@ -1318,6 +1330,8 @@ void ARM9IOWrite16(u32 addr, u16 val) MapNWRAM_C(6, val & 0xFF); MapNWRAM_C(7, val >> 8); return; + + //case 0x04004202: dicks = val & 0xEF3F; return; } return NDS::ARM9IOWrite16(addr, val); diff --git a/src/DSi.h b/src/DSi.h index bd37550..5697237 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -47,6 +47,7 @@ bool LoadNAND(); void RunNDMAs(u32 cpu); void StallNDMAs(); +bool NDMAsInMode(u32 cpu, u32 mode); bool NDMAsRunning(u32 cpu); void CheckNDMAs(u32 cpu, u32 mode); void StopNDMAs(u32 cpu, u32 mode); diff --git a/src/DSi_AES.cpp b/src/DSi_AES.cpp index e49ebf5..7aae8f3 100644 --- a/src/DSi_AES.cpp +++ b/src/DSi_AES.cpp @@ -129,28 +129,8 @@ void Reset() memset(CurKey, 0, sizeof(CurKey)); memset(CurMAC, 0, sizeof(CurMAC)); - // initialize keys, as per GBAtek - -#if 0 - // slot 0: modcrypt - *(u32*)&KeyX[0][0] = 0x746E694E; - *(u32*)&KeyX[0][4] = 0x6F646E65; - - // slot 1: 'Tad'/dev.kp - *(u32*)&KeyX[1][0] = 0x4E00004A; - *(u32*)&KeyX[1][4] = 0x4A00004E; - *(u32*)&KeyX[1][8] = (u32)(DSi::ConsoleID >> 32) ^ 0xC80C4B72; - *(u32*)&KeyX[1][12] = (u32)DSi::ConsoleID; - - // slot 3: console-unique eMMC crypto - *(u32*)&KeyX[3][0] = (u32)DSi::ConsoleID; - *(u32*)&KeyX[3][4] = (u32)DSi::ConsoleID ^ 0x24EE6906; - *(u32*)&KeyX[3][8] = (u32)(DSi::ConsoleID >> 32) ^ 0xE65B601D; - *(u32*)&KeyX[3][12] = (u32)(DSi::ConsoleID >> 32); - *(u32*)&KeyY[3][0] = 0x0AB9DC76; - *(u32*)&KeyY[3][4] = 0xBD4DC4D3; - *(u32*)&KeyY[3][8] = 0x202DDD1D; -#endif + // initialize keys + FILE* f = Platform::OpenLocalFile("aeskeys.bin", "rb"); if (f) { @@ -233,12 +213,12 @@ u32 ReadCnt() ret |= InputFIFO->Level(); ret |= (OutputFIFO->Level() << 5); - +//printf("READ AES CNT: %08X, LEVELS: IN=%d OUT=%d\n", ret, InputFIFO->Level(), OutputFIFO->Level()); return ret; } void WriteCnt(u32 val) -{ +{printf("AES CNT = %08X\n", val); u32 oldcnt = Cnt; Cnt = val & 0xFC1FF000; @@ -267,41 +247,51 @@ void WriteCnt(u32 val) // transfer start (checkme) RemBlocks = BlkCnt >> 16; - u8 key[16]; - u8 iv[16]; + if (RemBlocks > 0) + { + u8 key[16]; + u8 iv[16]; - Swap16(key, CurKey); - Swap16(iv, IV); + Swap16(key, CurKey); + Swap16(iv, IV); - if (AESMode < 2) - { - if (BlkCnt & 0xFFFF) printf("AES: CCM EXTRA LEN TODO\n"); + if (AESMode < 2) + { + if (BlkCnt & 0xFFFF) printf("AES: CCM EXTRA LEN TODO\n"); - u32 maclen = (val >> 16) & 0x7; - if (maclen < 1) maclen = 1; + u32 maclen = (val >> 16) & 0x7; + if (maclen < 1) maclen = 1; - iv[0] = 0x02; - for (int i = 0; i < 12; i++) iv[1+i] = iv[4+i]; - iv[13] = 0x00; - iv[14] = 0x00; - iv[15] = 0x01; + iv[0] = 0x02; + for (int i = 0; i < 12; i++) iv[1+i] = iv[4+i]; + iv[13] = 0x00; + iv[14] = 0x00; + iv[15] = 0x01; - AES_init_ctx_iv(&Ctx, key, iv); + AES_init_ctx_iv(&Ctx, key, iv); - iv[0] |= (maclen << 3) | ((BlkCnt & 0xFFFF) ? (1<<6) : 0); - iv[13] = RemBlocks >> 12; - iv[14] = RemBlocks >> 4; - iv[15] = RemBlocks << 4; + iv[0] |= (maclen << 3) | ((BlkCnt & 0xFFFF) ? (1<<6) : 0); + iv[13] = RemBlocks >> 12; + iv[14] = RemBlocks >> 4; + iv[15] = RemBlocks << 4; - memcpy(CurMAC, iv, 16); - AES_ECB_encrypt(&Ctx, CurMAC); + memcpy(CurMAC, iv, 16); + AES_ECB_encrypt(&Ctx, CurMAC); + } + else + { + AES_init_ctx_iv(&Ctx, key, iv); + } + + DSi::CheckNDMAs(1, 0x2A); } else { - AES_init_ctx_iv(&Ctx, key, iv); - } + // no blocks to process? oh well. mark it finished + // CHECKME: does this trigger any IRQ or shit? - DSi::CheckNDMAs(1, 0x2A); + Cnt &= ~(1<<31); + } } printf("AES CNT: %08X / mode=%d key=%d inDMA=%d outDMA=%d blocks=%d\n", @@ -309,7 +299,7 @@ void WriteCnt(u32 val) } void WriteBlkCnt(u32 val) -{ +{printf("AES BLOCK CNT %08X / %d\n", val, val>>16); BlkCnt = val; } @@ -415,7 +405,7 @@ void Update() // CHECKME Cnt &= ~(1<<21); } - +printf("AES: FINISHED\n"); Cnt &= ~(1<<31); if (Cnt & (1<<30)) NDS::SetIRQ2(NDS::IRQ2_DSi_AES); DSi::StopNDMAs(1, 0x2A); diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index e7fc7ab..19c72b6 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -101,8 +101,10 @@ void DSi_NDMA::WriteCnt(u32 val) Start(); if (StartMode != 0x10 && StartMode != 0x30 && - StartMode != 0x2A && StartMode != 0x2B) - printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X\n", CPU?7:9, Num, StartMode, SrcAddr, DstAddr); + StartMode != 0x04 && StartMode != 0x06 && StartMode != 0x07 && StartMode != 0x08 && StartMode != 0x09 && + StartMode != 0x24 && StartMode != 0x26 && StartMode != 0x28 && StartMode != 0x29 && StartMode != 0x2A && StartMode != 0x2B) + printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X LEN=%d BLK=%d CNT=%08X\n", + CPU?7:9, Num, StartMode, SrcAddr, DstAddr, TotalLength, BlockLength, Cnt); } } diff --git a/src/DSi_SD.cpp b/src/DSi_SD.cpp index 796466d..a45a8ce 100644 --- a/src/DSi_SD.cpp +++ b/src/DSi_SD.cpp @@ -91,10 +91,16 @@ void DSi_SDHost::Reset() if (Num == 0) { + // TODO: eventually pull from host filesystem + /*DSi_MMCStorage* sd = new DSi_MMCStorage(this, false, "sd.bin"); + u8 sd_cid[16] = {0xBD, 0x12, 0x34, 0x56, 0x78, 0x03, 0x4D, 0x30, 0x30, 0x46, 0x50, 0x41, 0x00, 0x00, 0x15, 0x00}; + sd->SetCID(sd_cid);*/ + DSi_MMCStorage* sd = NULL; + DSi_MMCStorage* mmc = new DSi_MMCStorage(this, true, "nand.bin"); mmc->SetCID(DSi::eMMC_CID); - // TODO: port 0 (SD) + Ports[0] = sd; Ports[1] = mmc; } else @@ -196,6 +202,14 @@ void DSi_SDHost::FinishSend(u32 param) host->ClearIRQ(25); host->SetIRQ(24); //if (param & 0x2) host->SetIRQ(2); + + // TODO: this is an assumption and should eventually be confirmed + // Flipnote sets DMA blocklen to 128 words and totallen to 1024 words + // so, presumably, DMA should trigger when the FIFO is full + // 'full' being when it reaches whatever BlockLen16 is set to, or the + // other blocklen register, or when it is actually full (but that makes + // less sense) + DSi::CheckNDMAs(1, host->Num ? 0x29 : 0x28); } u32 DSi_SDHost::SendData(u8* data, u32 len) @@ -286,7 +300,7 @@ u32 DSi_SDHost::GetTransferrableLen(u32 len) u16 DSi_SDHost::Read(u32 addr) { - //if(Num)printf("SDIO READ %08X %08X\n", addr, NDS::GetPC(1)); + if(!Num)printf("SDMMC READ %08X %08X\n", addr, NDS::GetPC(1)); switch (addr & 0x1FF) { @@ -307,7 +321,24 @@ u16 DSi_SDHost::Read(u32 addr) case 0x018: return ResponseBuffer[6]; case 0x01A: return ResponseBuffer[7]; - case 0x01C: return (IRQStatus & 0x031D) | 0x0030; // TODO: adjust insert flags for SD card + case 0x01C: + { + u16 ret = (IRQStatus & 0x031D); + + if (!Num) + { + if (Ports[0]) // basic check of whether the SD card is inserted + ret |= 0x0030; + else + ret |= 0x0008; + } + else + { + // SDIO wifi is always inserted, I guess + ret |= 0x0030; + } + return ret; + } case 0x01E: return ((IRQStatus >> 16) & 0x8B7F); case 0x020: return IRQMask & 0x031D; case 0x022: return (IRQMask >> 16) & 0x8B7F; @@ -436,7 +467,7 @@ u32 DSi_SDHost::ReadFIFO32() void DSi_SDHost::Write(u32 addr, u16 val) { - //if(Num)printf("SDIO WRITE %08X %04X %08X\n", addr, val, NDS::GetPC(1)); + if(!Num)printf("SDMMC WRITE %08X %04X %08X\n", addr, val, NDS::GetPC(1)); switch (addr & 0x1FF) { @@ -464,7 +495,7 @@ void DSi_SDHost::Write(u32 addr, u16 val) } return; - case 0x002: PortSelect = val; printf("%s: PORT SELECT %04X\n", SD_DESC, val); return; + case 0x002: PortSelect = (val & 0x040F) | (PortSelect & 0x0300); printf("%s: PORT SELECT %04X (%04X)\n", SD_DESC, val, PortSelect); return; case 0x004: Param = (Param & 0xFFFF0000) | val; return; case 0x006: Param = (Param & 0x0000FFFF) | (val << 16); return; @@ -504,7 +535,7 @@ void DSi_SDHost::Write(u32 addr, u16 val) if (DataFIFO[f]->IsFull()) { // TODO - printf("!!!! %s FIFO FULL\n", SD_DESC); + printf("!!!! %s FIFO (16) FULL\n", SD_DESC); return; } @@ -582,12 +613,14 @@ void DSi_SDHost::WriteFIFO32(u32 val) { if (DataMode != 1) return; + printf("%s: WRITE FIFO32: LEVEL=%d/%d\n", SD_DESC, DataFIFO[CurFIFO]->Level(), (BlockLen16>>1)); + DSi_SDDevice* dev = Ports[PortSelect & 0x1]; u32 f = CurFIFO; if (DataFIFO[f]->IsFull()) { // TODO - printf("!!!! %s FIFO FULL\n", SD_DESC); + printf("!!!! %s FIFO (32) FULL\n", SD_DESC); return; } @@ -608,12 +641,26 @@ void DSi_SDHost::WriteFIFO32(u32 val) } +#define MMC_DESC (Internal?"NAND":"SDcard") + DSi_MMCStorage::DSi_MMCStorage(DSi_SDHost* host, bool internal, const char* path) : DSi_SDDevice(host) { Internal = internal; strncpy(FilePath, path, 1023); FilePath[1023] = '\0'; File = Platform::OpenLocalFile(path, "r+b"); + if (!File) + { + if (internal) + { + // TODO: proper failure + printf("!! MMC file %s does not exist\n", path); + } + else + { + File = Platform::OpenLocalFile(path, "w+b"); + } + } CSR = 0x00000100; // checkme @@ -674,6 +721,7 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param) { // TODO printf("CMD3 on SD card: TODO\n"); + Host->SendResponse((CSR & 0x1FFF) | ((CSR >> 6) & 0x2000) | ((CSR >> 8) & 0xC000) | (1 << 16), true); } return; diff --git a/src/NDS.cpp b/src/NDS.cpp index 95265cf..6933e95 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -1371,6 +1371,29 @@ void RunTimers(u32 cpu) +// matching NDMA modes for DSi +const u32 NDMAModes[] = +{ + // ARM9 + + 0x10, // immediate + 0x06, // VBlank + 0x07, // HBlank + 0x08, // scanline start + 0x09, // mainmem FIFO + 0x04, // DS cart slot + 0xFF, // GBA cart slot + 0x0A, // GX FIFO + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + + // ARM7 + + 0x30, // immediate + 0x26, // VBlank + 0x24, // DS cart slot + 0xFF, // wifi / GBA cart slot (TODO) +}; + bool DMAsInMode(u32 cpu, u32 mode) { cpu <<= 2; @@ -1378,6 +1401,13 @@ bool DMAsInMode(u32 cpu, u32 mode) if (DMAs[cpu+1]->IsInMode(mode)) return true; if (DMAs[cpu+2]->IsInMode(mode)) return true; if (DMAs[cpu+3]->IsInMode(mode)) return true; + + if (true) + { + cpu >>= 2; + return DSi::NDMAsInMode(cpu, NDMAModes[mode]); + } + return false; } @@ -1399,6 +1429,12 @@ void CheckDMAs(u32 cpu, u32 mode) DMAs[cpu+1]->StartIfNeeded(mode); DMAs[cpu+2]->StartIfNeeded(mode); DMAs[cpu+3]->StartIfNeeded(mode); + + if (true) + { + cpu >>= 2; + DSi::CheckNDMAs(cpu, NDMAModes[mode]); + } } void StopDMAs(u32 cpu, u32 mode) @@ -1408,6 +1444,12 @@ void StopDMAs(u32 cpu, u32 mode) DMAs[cpu+1]->StopIfNeeded(mode); DMAs[cpu+2]->StopIfNeeded(mode); DMAs[cpu+3]->StopIfNeeded(mode); + + if (true) + { + cpu >>= 2; + DSi::StopNDMAs(cpu, NDMAModes[mode]); + } } diff --git a/src/NDSCart.cpp b/src/NDSCart.cpp index 65cf8ae..b0e9837 100644 --- a/src/NDSCart.cpp +++ b/src/NDSCart.cpp @@ -1227,11 +1227,11 @@ void WriteROMCnt(u32 val) *(u32*)&cmd[4] = *(u32*)&ROMCommand[4]; } - printf("ROM COMMAND %04X %08X %02X%02X%02X%02X%02X%02X%02X%02X SIZE %04X\n", + /*printf("ROM COMMAND %04X %08X %02X%02X%02X%02X%02X%02X%02X%02X SIZE %04X\n", SPICnt, ROMCnt, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], cmd[5], cmd[6], cmd[7], - datasize); + datasize);*/ switch (cmd[0]) { -- cgit v1.2.3 From 6326ddd1726773ae21ac2408f9cc3109f112e154 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Mon, 1 Jun 2020 16:32:44 +0200 Subject: reset SD controllers during a soft-reset --- src/DSi.cpp | 3 +++ src/DSi_SD.cpp | 12 +++++------- src/NDS.cpp | 4 +--- 3 files changed, 9 insertions(+), 10 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index fb4b37a..58f39c2 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -182,6 +182,9 @@ void SoftReset() LoadNAND(); + SDMMC->Reset(); + SDIO->Reset(); + NDS::ARM9->JumpTo(BootAddr[0]); NDS::ARM7->JumpTo(BootAddr[1]); diff --git a/src/DSi_SD.cpp b/src/DSi_SD.cpp index 5231b99..8584e8b 100644 --- a/src/DSi_SD.cpp +++ b/src/DSi_SD.cpp @@ -525,12 +525,12 @@ void DSi_SDHost::Write(u32 addr, u16 val) } return; - case 0x002: PortSelect = (val & 0x040F) | (PortSelect & 0x0300); printf("%s: PORT SELECT %04X (%04X)\n", SD_DESC, val, PortSelect); return; + case 0x002: PortSelect = (val & 0x040F) | (PortSelect & 0x0300); return; case 0x004: Param = (Param & 0xFFFF0000) | val; return; case 0x006: Param = (Param & 0x0000FFFF) | (val << 16); return; case 0x008: StopAction = val & 0x0101; return; - case 0x00A: BlockCount16 = val; BlockCountInternal = val; printf("%s: BLOCK COUNT %d\n", SD_DESC, val); return; + case 0x00A: BlockCount16 = val; BlockCountInternal = val; return; case 0x01C: IRQStatus &= (val | 0xFFFF0000); return; case 0x01E: IRQStatus &= ((val << 16) | 0xFFFF); return; @@ -575,7 +575,6 @@ void DSi_SDHost::Write(u32 addr, u16 val) case 0x0D8: DataCtl = (val & 0x0022); DataMode = ((DataCtl >> 1) & 0x1) & ((Data32IRQ >> 1) & 0x1); - printf("%s: data mode %d-bit\n", SD_DESC, DataMode?32:16); return; case 0x0E0: @@ -598,7 +597,6 @@ void DSi_SDHost::Write(u32 addr, u16 val) Data32IRQ = (val & 0x1802) | (Data32IRQ & 0x0300); if (val & (1<<10)) DataFIFO32->Clear(); DataMode = ((DataCtl >> 1) & 0x1) & ((Data32IRQ >> 1) & 0x1); - printf("%s: data mode %d-bit\n", SD_DESC, DataMode?32:16); return; case 0x104: BlockLen32 = val & 0x03FF; return; case 0x108: BlockCount32 = val; return; @@ -803,7 +801,7 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param) return; case 18: // read multiple blocks - printf("READ_MULTIPLE_BLOCKS addr=%08X size=%08X\n", param, BlockSize); + //printf("READ_MULTIPLE_BLOCKS addr=%08X size=%08X\n", param, BlockSize); RWAddress = param; if (OCR & (1<<30)) { @@ -818,7 +816,7 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param) return; case 25: // write multiple blocks - printf("WRITE_MULTIPLE_BLOCKS addr=%08X size=%08X\n", param, BlockSize); + //printf("WRITE_MULTIPLE_BLOCKS addr=%08X size=%08X\n", param, BlockSize); RWAddress = param; if (OCR & (1<<30)) { @@ -846,7 +844,7 @@ void DSi_MMCStorage::SendACMD(u8 cmd, u32 param) switch (cmd) { case 6: // set bus width (TODO?) - printf("SET BUS WIDTH %08X\n", param); + //printf("SET BUS WIDTH %08X\n", param); Host->SendResponse(CSR, true); return; diff --git a/src/NDS.cpp b/src/NDS.cpp index 3936dc8..001dfe6 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -2834,7 +2834,7 @@ u32 ARM9IORead32(u32 addr) case 0x04000130: return (KeyInput & 0xFFFF) | (KeyCnt << 16); - case 0x04000180: /*printf("ARM9 read IPCSYNC: %04X\n", IPCSync9);*/ return IPCSync9; + case 0x04000180: return IPCSync9; case 0x040001A0: return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16); case 0x040001A4: return NDSCart::ROMCnt; @@ -3043,7 +3043,6 @@ void ARM9IOWrite16(u32 addr, u16 val) return; case 0x04000180: - printf("ARM9 IPCSYNC = %04X\n", val); IPCSync7 &= 0xFFF0; IPCSync7 |= ((val & 0x0F00) >> 8); IPCSync9 &= 0xB0FF; @@ -3633,7 +3632,6 @@ void ARM7IOWrite16(u32 addr, u16 val) case 0x04000138: RTC::Write(val, false); return; case 0x04000180: - printf("ARM7 IPCSYNC = %04X\n", val); IPCSync9 &= 0xFFF0; IPCSync9 |= ((val & 0x0F00) >> 8); IPCSync7 &= 0xB0FF; -- cgit v1.2.3 From 43e045357f7d74eecff61b0c8af8068b31e963b3 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Mon, 1 Jun 2020 20:36:30 +0200 Subject: make it able to switch between DS and DSi modes --- src/ARM.cpp | 46 +++++++++ src/ARM.h | 43 ++++---- src/CP15.cpp | 30 ++---- src/DMA.cpp | 29 ++++-- src/DMA.h | 5 + src/DSi.cpp | 7 +- src/NDS.cpp | 54 +++++++--- src/NDS.h | 5 + src/NDSCart.cpp | 15 ++- src/SPI.cpp | 32 ++++-- src/SPU.cpp | 16 ++- src/SPU.h | 6 ++ src/frontend/FrontendUtil.h | 9 ++ src/frontend/Util_ROM.cpp | 163 +++++++++++++++++++++++++++--- src/frontend/qt_sdl/EmuSettingsDialog.cpp | 2 +- src/frontend/qt_sdl/main.cpp | 45 +++++++-- 16 files changed, 396 insertions(+), 111 deletions(-) (limited to 'src/NDS.cpp') diff --git a/src/ARM.cpp b/src/ARM.cpp index 2d8c807..68cac59 100644 --- a/src/ARM.cpp +++ b/src/ARM.cpp @@ -18,6 +18,7 @@ #include #include "NDS.h" +#include "DSi.h" #include "ARM.h" #include "ARMInterpreter.h" #include "AREngine.h" @@ -101,10 +102,55 @@ void ARM::Reset() void ARMv5::Reset() { + if (NDS::ConsoleType == 1) + { + BusRead8 = DSi::ARM9Read8; + BusRead16 = DSi::ARM9Read16; + BusRead32 = DSi::ARM9Read32; + BusWrite8 = DSi::ARM9Write8; + BusWrite16 = DSi::ARM9Write16; + BusWrite32 = DSi::ARM9Write32; + GetMemRegion = DSi::ARM9GetMemRegion; + } + else + { + BusRead8 = NDS::ARM9Read8; + BusRead16 = NDS::ARM9Read16; + BusRead32 = NDS::ARM9Read32; + BusWrite8 = NDS::ARM9Write8; + BusWrite16 = NDS::ARM9Write16; + BusWrite32 = NDS::ARM9Write32; + GetMemRegion = NDS::ARM9GetMemRegion; + } + CP15Reset(); ARM::Reset(); } +void ARMv4::Reset() +{ + if (NDS::ConsoleType) + { + BusRead8 = DSi::ARM7Read8; + BusRead16 = DSi::ARM7Read16; + BusRead32 = DSi::ARM7Read32; + BusWrite8 = DSi::ARM7Write8; + BusWrite16 = DSi::ARM7Write16; + BusWrite32 = DSi::ARM7Write32; + } + else + { + BusRead8 = NDS::ARM7Read8; + BusRead16 = NDS::ARM7Read16; + BusRead32 = NDS::ARM7Read32; + BusWrite8 = NDS::ARM7Write8; + BusWrite16 = NDS::ARM7Write16; + BusWrite32 = NDS::ARM7Write32; + } + + ARM::Reset(); +} + void ARM::DoSavestate(Savestate* file) { diff --git a/src/ARM.h b/src/ARM.h index 95c41d4..e0832e2 100644 --- a/src/ARM.h +++ b/src/ARM.h @@ -23,7 +23,6 @@ #include "types.h" #include "NDS.h" -#include "DSi.h" #define ROR(x, n) (((x) >> (n)) | ((x) << (32-(n)))) @@ -133,6 +132,14 @@ public: NDS::MemRegion CodeMem; static u32 ConditionTable[16]; + +protected: + u8 (*BusRead8)(u32 addr); + u16 (*BusRead16)(u32 addr); + u32 (*BusRead32)(u32 addr); + void (*BusWrite8)(u32 addr, u8 val); + void (*BusWrite16)(u32 addr, u16 val); + void (*BusWrite32)(u32 addr, u32 val); }; class ARMv5 : public ARM @@ -260,6 +267,8 @@ public: s32 RegionCodeCycles; u8* CurICacheLine; + + bool (*GetMemRegion)(u32 addr, bool write, NDS::MemRegion* region); }; class ARMv4 : public ARM @@ -267,26 +276,25 @@ class ARMv4 : public ARM public: ARMv4(); + void Reset(); + void JumpTo(u32 addr, bool restorecpsr = false); void Execute(); u16 CodeRead16(u32 addr) { - //return NDS::ARM7Read16(addr); - return DSi::ARM7Read16(addr); + return BusRead16(addr); } u32 CodeRead32(u32 addr) { - //return NDS::ARM7Read32(addr); - return DSi::ARM7Read32(addr); + return BusRead32(addr); } void DataRead8(u32 addr, u32* val) { - *val = DSi::ARM7Read8(addr); - //*val = NDS::ARM7Read8(addr); + *val = BusRead8(addr); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][0]; } @@ -295,8 +303,7 @@ public: { addr &= ~1; - *val = DSi::ARM7Read16(addr); - //*val = NDS::ARM7Read16(addr); + *val = BusRead16(addr); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][0]; } @@ -305,8 +312,7 @@ public: { addr &= ~3; - *val = DSi::ARM7Read32(addr); - //*val = NDS::ARM7Read32(addr); + *val = BusRead32(addr); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][2]; } @@ -315,15 +321,13 @@ public: { addr &= ~3; - *val = DSi::ARM7Read32(addr); - //*val = NDS::ARM7Read32(addr); + *val = BusRead32(addr); DataCycles += NDS::ARM7MemTimings[DataRegion][3]; } void DataWrite8(u32 addr, u8 val) { - DSi::ARM7Write8(addr, val); - //NDS::ARM7Write8(addr, val); + BusWrite8(addr, val); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][0]; } @@ -332,8 +336,7 @@ public: { addr &= ~1; - DSi::ARM7Write16(addr, val); - //NDS::ARM7Write16(addr, val); + BusWrite16(addr, val); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][0]; } @@ -342,8 +345,7 @@ public: { addr &= ~3; - DSi::ARM7Write32(addr, val); - //NDS::ARM7Write32(addr, val); + BusWrite32(addr, val); DataRegion = addr >> 24; DataCycles = NDS::ARM7MemTimings[DataRegion][2]; } @@ -352,8 +354,7 @@ public: { addr &= ~3; - DSi::ARM7Write32(addr, val); - //NDS::ARM7Write32(addr, val); + BusWrite32(addr, val); DataCycles += NDS::ARM7MemTimings[DataRegion][3]; } diff --git a/src/CP15.cpp b/src/CP15.cpp index b61cc45..d340b9e 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -720,8 +720,7 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch) if (CodeMem.Mem) return *(u32*)&CodeMem.Mem[addr & CodeMem.Mask]; - //return NDS::ARM9Read32(addr); - return DSi::ARM9Read32(addr); + return BusRead32(addr); } @@ -740,8 +739,7 @@ void ARMv5::DataRead8(u32 addr, u32* val) return; } - *val = DSi::ARM9Read8(addr); - //*val = NDS::ARM9Read8(addr); + *val = BusRead8(addr); DataCycles = MemTimings[addr >> 12][1]; } @@ -762,8 +760,7 @@ void ARMv5::DataRead16(u32 addr, u32* val) return; } - *val = DSi::ARM9Read16(addr); - //*val = NDS::ARM9Read16(addr); + *val = BusRead16(addr); DataCycles = MemTimings[addr >> 12][1]; } @@ -784,8 +781,7 @@ void ARMv5::DataRead32(u32 addr, u32* val) return; } - *val = DSi::ARM9Read32(addr); - //*val = NDS::ARM9Read32(addr); + *val = BusRead32(addr); DataCycles = MemTimings[addr >> 12][2]; } @@ -806,8 +802,7 @@ void ARMv5::DataRead32S(u32 addr, u32* val) return; } - *val = DSi::ARM9Read32(addr); - //*val = NDS::ARM9Read32(addr); + *val = BusRead32(addr); DataCycles += MemTimings[addr >> 12][3]; } @@ -826,8 +821,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val) return; } - DSi::ARM9Write8(addr, val); - //NDS::ARM9Write8(addr, val); + BusWrite8(addr, val); DataCycles = MemTimings[addr >> 12][1]; } @@ -848,8 +842,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val) return; } - DSi::ARM9Write16(addr, val); - //NDS::ARM9Write16(addr, val); + BusWrite16(addr, val); DataCycles = MemTimings[addr >> 12][1]; } @@ -870,8 +863,7 @@ void ARMv5::DataWrite32(u32 addr, u32 val) return; } - DSi::ARM9Write32(addr, val); - //NDS::ARM9Write32(addr, val); + BusWrite32(addr, val); DataCycles = MemTimings[addr >> 12][2]; } @@ -892,8 +884,7 @@ void ARMv5::DataWrite32S(u32 addr, u32 val) return; } - DSi::ARM9Write32(addr, val); - //NDS::ARM9Write32(addr, val); + BusWrite32(addr, val); DataCycles += MemTimings[addr >> 12][3]; } @@ -906,7 +897,6 @@ void ARMv5::GetCodeMemRegion(u32 addr, NDS::MemRegion* region) return; }*/ - DSi::ARM9GetMemRegion(addr, false, &CodeMem); - //NDS::ARM9GetMemRegion(addr, false, &CodeMem); + GetMemRegion(addr, false, &CodeMem); } diff --git a/src/DMA.cpp b/src/DMA.cpp index 8e294fc..cd2df45 100644 --- a/src/DMA.cpp +++ b/src/DMA.cpp @@ -53,8 +53,6 @@ DMA::DMA(u32 cpu, u32 num) CountMask = 0x001FFFFF; else CountMask = (num==3 ? 0x0000FFFF : 0x00003FFF); - - Reset(); } DMA::~DMA() @@ -77,6 +75,21 @@ void DMA::Reset() Running = false; InProgress = false; + + if (NDS::ConsoleType == 1) + { + BusRead16 = (CPU==0) ? DSi::ARM9Read16 : DSi::ARM7Read16; + BusRead32 = (CPU==0) ? DSi::ARM9Read32 : DSi::ARM7Read32; + BusWrite16 = (CPU==0) ? DSi::ARM9Write16 : DSi::ARM7Write16; + BusWrite32 = (CPU==0) ? DSi::ARM9Write32 : DSi::ARM7Write32; + } + else + { + BusRead16 = (CPU==0) ? NDS::ARM9Read16 : NDS::ARM7Read16; + BusRead32 = (CPU==0) ? NDS::ARM9Read32 : NDS::ARM7Read32; + BusWrite16 = (CPU==0) ? NDS::ARM9Write16 : NDS::ARM7Write16; + BusWrite32 = (CPU==0) ? NDS::ARM9Write32 : NDS::ARM7Write32; + } } void DMA::DoSavestate(Savestate* file) @@ -227,8 +240,7 @@ void DMA::Run9() { NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift); - //NDS::ARM9Write16(CurDstAddr, NDS::ARM9Read16(CurSrcAddr)); - DSi::ARM9Write16(CurDstAddr, DSi::ARM9Read16(CurSrcAddr)); + BusWrite16(CurDstAddr, BusRead16(CurSrcAddr)); CurSrcAddr += SrcAddrInc<<1; CurDstAddr += DstAddrInc<<1; @@ -264,8 +276,7 @@ void DMA::Run9() { NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift); - //NDS::ARM9Write32(CurDstAddr, NDS::ARM9Read32(CurSrcAddr)); - DSi::ARM9Write32(CurDstAddr, DSi::ARM9Read32(CurSrcAddr)); + BusWrite32(CurDstAddr, BusRead32(CurSrcAddr)); CurSrcAddr += SrcAddrInc<<2; CurDstAddr += DstAddrInc<<2; @@ -341,8 +352,7 @@ void DMA::Run7() { NDS::ARM7Timestamp += unitcycles; - //NDS::ARM7Write16(CurDstAddr, NDS::ARM7Read16(CurSrcAddr)); - DSi::ARM7Write16(CurDstAddr, DSi::ARM7Read16(CurSrcAddr)); + BusWrite16(CurDstAddr, BusRead16(CurSrcAddr)); CurSrcAddr += SrcAddrInc<<1; CurDstAddr += DstAddrInc<<1; @@ -378,8 +388,7 @@ void DMA::Run7() { NDS::ARM7Timestamp += unitcycles; - //NDS::ARM7Write32(CurDstAddr, NDS::ARM7Read32(CurSrcAddr)); - DSi::ARM7Write32(CurDstAddr, DSi::ARM7Read32(CurSrcAddr)); + BusWrite32(CurDstAddr, BusRead32(CurSrcAddr)); CurSrcAddr += SrcAddrInc<<2; CurDstAddr += DstAddrInc<<2; diff --git a/src/DMA.h b/src/DMA.h index 2e7678c..0344fba 100644 --- a/src/DMA.h +++ b/src/DMA.h @@ -86,6 +86,11 @@ private: bool Stall; bool IsGXFIFODMA; + + u16 (*BusRead16)(u32 addr); + u32 (*BusRead32)(u32 addr); + void (*BusWrite16)(u32 addr, u16 val); + void (*BusWrite32)(u32 addr, u32 val); }; #endif diff --git a/src/DSi.cpp b/src/DSi.cpp index 58f39c2..520b269 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -18,6 +18,7 @@ #include #include +#include "Config.h" #include "NDS.h" #include "DSi.h" #include "ARM.h" @@ -221,7 +222,7 @@ bool LoadBIOS() memset(ARM9iBIOS, 0, 0x10000); memset(ARM7iBIOS, 0, 0x10000); - f = Platform::OpenLocalFile("bios9i.bin", "rb"); + f = Platform::OpenLocalFile(Config::DSiBIOS9Path, "rb"); if (!f) { printf("ARM9i BIOS not found\n"); @@ -238,7 +239,7 @@ bool LoadBIOS() fclose(f); } - f = Platform::OpenLocalFile("bios7i.bin", "rb"); + f = Platform::OpenLocalFile(Config::DSiBIOS7Path, "rb"); if (!f) { printf("ARM7i BIOS not found\n"); @@ -283,7 +284,7 @@ bool LoadNAND() memset(NWRAMEnd, 0, sizeof(NWRAMEnd)); memset(NWRAMMask, 0, sizeof(NWRAMMask)); - FILE* f = Platform::OpenLocalFile("nand.bin", "rb"); + FILE* f = Platform::OpenLocalFile(Config::DSiNANDPath, "rb"); if (f) { u32 bootparams[8]; diff --git a/src/NDS.cpp b/src/NDS.cpp index 001dfe6..22368ae 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -62,6 +62,8 @@ namespace NDS // // timings for GBA slot and wifi are set up at runtime +int ConsoleType; + u8 ARM9MemTimings[0x40000][4]; u8 ARM7MemTimings[0x20000][4]; @@ -296,6 +298,8 @@ void InitTimings() // TODO: +3c nonseq waitstate doesn't apply to DMA! // but of course mainRAM always gets 8c nonseq waitstate + // TODO: DSi-specific timings!! + SetARM9RegionTimings(0x00000000, 0xFFFFFFFF, 32, 1 + 3, 1); // void SetARM9RegionTimings(0xFFFF0000, 0xFFFFFFFF, 32, 1 + 3, 1); // BIOS @@ -321,6 +325,12 @@ void InitTimings() void SetupDirectBoot() { + if (ConsoleType == 1) + { + printf("!! DIRECT BOOT NOT SUPPORTED IN DSI MODE\n"); + return; + } + u32 bootparams[8]; memcpy(bootparams, &NDSCart::CartROM[0x20], 8*4); @@ -469,7 +479,7 @@ void Reset() fclose(f); } - if (true) + if (ConsoleType == 1) { DSi::LoadBIOS(); DSi::LoadNAND(); @@ -559,8 +569,11 @@ void Reset() RTC::Reset(); Wifi::Reset(); - DSi::Reset(); - KeyInput &= ~(1 << (16+6)); // TODO + if (ConsoleType == 1) + { + DSi::Reset(); + KeyInput &= ~(1 << (16+6)); + } AREngine::Reset(); } @@ -670,6 +683,11 @@ bool DoSavestate(Savestate* file) { file->Section("NDSG"); + // TODO: + // * do something for bool's (sizeof=1) + // * do something for 'loading DSi-mode savestate in DS mode' and vice-versa + // * add IE2/IF2 there + file->VarArray(MainRAM, 0x400000); file->VarArray(SharedWRAM, 0x8000); file->VarArray(ARM7WRAM, 0x10000); @@ -772,6 +790,11 @@ bool DoSavestate(Savestate* file) return true; } +void SetConsoleType(int type) +{ + ConsoleType = type; +} + bool LoadROM(const char* path, const char* sram, bool direct) { if (NDSCart::LoadROM(path, sram, direct)) @@ -883,7 +906,7 @@ u32 RunFrame() if (!(CPUStop & 0x80000000)) DMAs[1]->Run(); if (!(CPUStop & 0x80000000)) DMAs[2]->Run(); if (!(CPUStop & 0x80000000)) DMAs[3]->Run(); - DSi::RunNDMAs(0); + if (ConsoleType == 1) DSi::RunNDMAs(0); } else { @@ -906,7 +929,7 @@ u32 RunFrame() DMAs[5]->Run(); DMAs[6]->Run(); DMAs[7]->Run(); - DSi::RunNDMAs(1); + if (ConsoleType == 1) DSi::RunNDMAs(1); } else { @@ -990,7 +1013,7 @@ void CancelEvent(u32 id) void TouchScreen(u16 x, u16 y) { - if (true) // TODO!! + if (ConsoleType == 1) { DSi_SPI_TSC::SetTouchCoords(x, y); } @@ -1003,7 +1026,7 @@ void TouchScreen(u16 x, u16 y) void ReleaseScreen() { - if (true) // TODO!! + if (ConsoleType == 1) { DSi_SPI_TSC::SetTouchCoords(0x000, 0xFFF); } @@ -1144,7 +1167,8 @@ void UpdateIRQ(u32 cpu) if (IME[cpu] & 0x1) { arm->IRQ = IE[cpu] & IF[cpu]; - if (cpu) arm->IRQ |= (IE2 & IF2); + if ((ConsoleType == 1) && cpu) + arm->IRQ |= (IE2 & IF2); } else { @@ -1223,7 +1247,7 @@ void GXFIFOStall() DMAs[1]->StallIfRunning(); DMAs[2]->StallIfRunning(); DMAs[3]->StallIfRunning(); - DSi::StallNDMAs(); + if (ConsoleType == 1) DSi::StallNDMAs(); } } @@ -1361,6 +1385,7 @@ void NocashPrint(u32 ncpu, u32 addr) void MonitorARM9Jump(u32 addr) { // checkme: can the entrypoint addr be THUMB? + // also TODO: make it work in DSi mode if ((!RunningGame) && NDSCart::CartROM) { @@ -1468,7 +1493,7 @@ bool DMAsInMode(u32 cpu, u32 mode) if (DMAs[cpu+2]->IsInMode(mode)) return true; if (DMAs[cpu+3]->IsInMode(mode)) return true; - if (true) + if (ConsoleType == 1) { cpu >>= 2; return DSi::NDMAsInMode(cpu, NDMAModes[mode]); @@ -1484,7 +1509,10 @@ bool DMAsRunning(u32 cpu) if (DMAs[cpu+1]->IsRunning()) return true; if (DMAs[cpu+2]->IsRunning()) return true; if (DMAs[cpu+3]->IsRunning()) return true; - if (DSi::NDMAsRunning(cpu>>2)) return true; + if (ConsoleType == 1) + { + if (DSi::NDMAsRunning(cpu>>2)) return true; + } return false; } @@ -1496,7 +1524,7 @@ void CheckDMAs(u32 cpu, u32 mode) DMAs[cpu+2]->StartIfNeeded(mode); DMAs[cpu+3]->StartIfNeeded(mode); - if (true) + if (ConsoleType == 1) { cpu >>= 2; DSi::CheckNDMAs(cpu, NDMAModes[mode]); @@ -1511,7 +1539,7 @@ void StopDMAs(u32 cpu, u32 mode) DMAs[cpu+2]->StopIfNeeded(mode); DMAs[cpu+3]->StopIfNeeded(mode); - if (true) + if (ConsoleType == 1) { cpu >>= 2; DSi::StopNDMAs(cpu, NDMAModes[mode]); diff --git a/src/NDS.h b/src/NDS.h index 26931de..9c5fe3d 100644 --- a/src/NDS.h +++ b/src/NDS.h @@ -133,6 +133,8 @@ typedef struct } MemRegion; +extern int ConsoleType; + extern u8 ARM9MemTimings[0x40000][4]; extern u8 ARM7MemTimings[0x20000][4]; @@ -174,6 +176,9 @@ bool DoSavestate(Savestate* file); void SetARM9RegionTimings(u32 addrstart, u32 addrend, int buswidth, int nonseq, int seq); void SetARM7RegionTimings(u32 addrstart, u32 addrend, int buswidth, int nonseq, int seq); +// 0=DS 1=DSi +void SetConsoleType(int type); + bool LoadROM(const char* path, const char* sram, bool direct); bool LoadGBAROM(const char* path, const char* sram); void LoadBIOS(); diff --git a/src/NDSCart.cpp b/src/NDSCart.cpp index 9497d33..b326dd6 100644 --- a/src/NDSCart.cpp +++ b/src/NDSCart.cpp @@ -561,11 +561,18 @@ void Key1_ApplyKeycode(u32* keycode, u32 mod) void Key1_InitKeycode(bool dsi, u32 idcode, u32 level, u32 mod) { - //memcpy(Key1_KeyBuf, &NDS::ARM7BIOS[0x30], 0x1048); // hax - if (dsi) - memcpy(Key1_KeyBuf, &DSi::ARM7Init[0x254], 0x1048); // hax + // TODO: source the key data from different possible places + if (NDS::ConsoleType == 1) + { + if (dsi) + memcpy(Key1_KeyBuf, &DSi::ARM7Init[0x254], 0x1048); // hax + else + memcpy(Key1_KeyBuf, &DSi::ITCMInit[0x4894], 0x1048); // hax + } else - memcpy(Key1_KeyBuf, &DSi::ITCMInit[0x4894], 0x1048); // hax + { + memcpy(Key1_KeyBuf, &NDS::ARM7BIOS[0x30], 0x1048); // hax + } u32 keycode[3] = {idcode, idcode>>1, idcode<<1}; if (level >= 1) Key1_ApplyKeycode(keycode, mod); diff --git a/src/SPI.cpp b/src/SPI.cpp index 29f3321..ac40707 100644 --- a/src/SPI.cpp +++ b/src/SPI.cpp @@ -93,7 +93,10 @@ void Reset() if (Firmware) delete[] Firmware; Firmware = NULL; - strncpy(FirmwarePath, Config::FirmwarePath, 1023); + if (NDS::ConsoleType == 1) + strncpy(FirmwarePath, Config::DSiFirmwarePath, 1023); + else + strncpy(FirmwarePath, Config::FirmwarePath, 1023); FILE* f = Platform::OpenLocalFile(FirmwarePath, "rb"); if (!f) @@ -620,7 +623,7 @@ void Reset() SPI_Firmware::Reset(); SPI_Powerman::Reset(); SPI_TSC::Reset(); - DSi_SPI_TSC::Reset(); + if (NDS::ConsoleType == 1) DSi_SPI_TSC::Reset(); } void DoSavestate(Savestate* file) @@ -633,7 +636,7 @@ void DoSavestate(Savestate* file) SPI_Firmware::DoSavestate(file); SPI_Powerman::DoSavestate(file); SPI_TSC::DoSavestate(file); - DSi_SPI_TSC::DoSavestate(file); + if (NDS::ConsoleType == 1) DSi_SPI_TSC::DoSavestate(file); } @@ -647,8 +650,12 @@ void WriteCnt(u16 val) { case 0x0000: SPI_Powerman::Hold = 0; break; case 0x0100: SPI_Firmware::Hold = 0; break; - //case 0x0200: SPI_TSC::DataPos = 0; break; - case 0x0200: DSi_SPI_TSC::DataPos = 0; break; + case 0x0200: + if (NDS::ConsoleType == 1) + DSi_SPI_TSC::DataPos = 0; + else + SPI_TSC::DataPos = 0; + break; } } @@ -674,8 +681,11 @@ u8 ReadData() { case 0x0000: return SPI_Powerman::Read(); case 0x0100: return SPI_Firmware::Read(); - //case 0x0200: return SPI_TSC::Read(); - case 0x0200: return DSi_SPI_TSC::Read(); + case 0x0200: + if (NDS::ConsoleType == 1) + return DSi_SPI_TSC::Read(); + else + return SPI_TSC::Read(); default: return 0; } } @@ -691,8 +701,12 @@ void WriteData(u8 val) { case 0x0000: SPI_Powerman::Write(val, Cnt&(1<<11)); break; case 0x0100: SPI_Firmware::Write(val, Cnt&(1<<11)); break; - //case 0x0200: SPI_TSC::Write(val, Cnt&(1<<11)); break; - case 0x0200: DSi_SPI_TSC::Write(val, Cnt&(1<<11)); break; + case 0x0200: + if (NDS::ConsoleType == 1) + DSi_SPI_TSC::Write(val, Cnt&(1<<11)); + else + SPI_TSC::Write(val, Cnt&(1<<11)); + break; default: printf("SPI to unknown device %04X %02X\n", Cnt, val); break; } diff --git a/src/SPU.cpp b/src/SPU.cpp index 959de12..9f6b107 100644 --- a/src/SPU.cpp +++ b/src/SPU.cpp @@ -155,6 +155,11 @@ Channel::~Channel() void Channel::Reset() { + if (NDS::ConsoleType == 1) + BusRead32 = DSi::ARM7Read32; + else + BusRead32 = NDS::ARM7Read32; + SetCnt(0); SrcAddr = 0; TimerReload = 0; @@ -217,8 +222,7 @@ void Channel::FIFO_BufferData() for (u32 i = 0; i < burstlen; i += 4) { - //FIFO[FIFOWritePos] = NDS::ARM7Read32(SrcAddr + FIFOReadOffset); - FIFO[FIFOWritePos] = DSi::ARM7Read32(SrcAddr + FIFOReadOffset); + FIFO[FIFOWritePos] = BusRead32(SrcAddr + FIFOReadOffset); FIFOReadOffset += 4; FIFOWritePos++; FIFOWritePos &= 0x7; @@ -466,6 +470,11 @@ CaptureUnit::~CaptureUnit() void CaptureUnit::Reset() { + if (NDS::ConsoleType == 1) + BusWrite32 = DSi::ARM7Write32; + else + BusWrite32 = NDS::ARM7Write32; + SetCnt(0); DstAddr = 0; TimerReload = 0; @@ -501,8 +510,7 @@ void CaptureUnit::FIFO_FlushData() { for (u32 i = 0; i < 4; i++) { - //NDS::ARM7Write32(DstAddr + FIFOWriteOffset, FIFO[FIFOReadPos]); - DSi::ARM7Write32(DstAddr + FIFOWriteOffset, FIFO[FIFOReadPos]); + BusWrite32(DstAddr + FIFOWriteOffset, FIFO[FIFOReadPos]); FIFOReadPos++; FIFOReadPos &= 0x3; diff --git a/src/SPU.h b/src/SPU.h index 74a4471..8ab17a0 100644 --- a/src/SPU.h +++ b/src/SPU.h @@ -142,6 +142,9 @@ public: } void PanOutput(s32* inbuf, u32 samples, s32* leftbuf, s32* rightbuf); + +private: + u32 (*BusRead32)(u32 addr); }; class CaptureUnit @@ -196,6 +199,9 @@ public: } void Run(s32 sample); + +private: + void (*BusWrite32)(u32 addr, u32 val); }; } diff --git a/src/frontend/FrontendUtil.h b/src/frontend/FrontendUtil.h index 6b83cbc..099583f 100644 --- a/src/frontend/FrontendUtil.h +++ b/src/frontend/FrontendUtil.h @@ -46,6 +46,15 @@ enum Load_FirmwareBad, Load_FirmwareNotBootable, + Load_DSiBIOS9Missing, + Load_DSiBIOS9Bad, + + Load_DSiBIOS7Missing, + Load_DSiBIOS7Bad, + + Load_DSiNANDMissing, + Load_DSiNANDBad, + // TODO: more precise errors for ROM loading Load_ROMLoadError, }; diff --git a/src/frontend/Util_ROM.cpp b/src/frontend/Util_ROM.cpp index d410550..8116a93 100644 --- a/src/frontend/Util_ROM.cpp +++ b/src/frontend/Util_ROM.cpp @@ -96,6 +96,42 @@ int VerifyDSBIOS() return Load_OK; } +int VerifyDSiBIOS() +{ + FILE* f; + long len; + + // TODO: check the first 32 bytes + + f = Platform::OpenLocalFile(Config::DSiBIOS9Path, "rb"); + if (!f) return Load_DSiBIOS9Missing; + + fseek(f, 0, SEEK_END); + len = ftell(f); + if (len != 0x10000) + { + fclose(f); + return Load_DSiBIOS9Bad; + } + + fclose(f); + + f = Platform::OpenLocalFile(Config::DSiBIOS7Path, "rb"); + if (!f) return Load_DSiBIOS7Missing; + + fseek(f, 0, SEEK_END); + len = ftell(f); + if (len != 0x10000) + { + fclose(f); + return Load_DSiBIOS7Bad; + } + + fclose(f); + + return Load_OK; +} + int VerifyDSFirmware() { FILE* f; @@ -110,7 +146,6 @@ int VerifyDSFirmware() { // 128KB firmware, not bootable fclose(f); - return Load_OK; // FIXME!!!! return Load_FirmwareNotBootable; } else if (len != 0x40000 && len != 0x80000) @@ -124,6 +159,45 @@ int VerifyDSFirmware() return Load_OK; } +int VerifyDSiFirmware() +{ + FILE* f; + long len; + + f = Platform::OpenLocalFile(Config::DSiFirmwarePath, "rb"); + if (!f) return Load_FirmwareMissing; + + fseek(f, 0, SEEK_END); + len = ftell(f); + if (len != 0x20000) + { + // not 128KB + // TODO: check whether those work + fclose(f); + return Load_FirmwareBad; + } + + fclose(f); + + return Load_OK; +} + +int VerifyDSiNAND() +{ + FILE* f; + long len; + + f = Platform::OpenLocalFile(Config::DSiNANDPath, "rb"); + if (!f) return Load_DSiNANDMissing; + + // TODO: some basic checks + // check that it has the nocash footer, and all + + fclose(f); + + return Load_OK; +} + int LoadBIOS() { int res; @@ -131,8 +205,22 @@ int LoadBIOS() res = VerifyDSBIOS(); if (res != Load_OK) return res; - res = VerifyDSFirmware(); - if (res != Load_OK) return res; + if (Config::ConsoleType == 1) + { + res = VerifyDSiBIOS(); + if (res != Load_OK) return res; + + res = VerifyDSiFirmware(); + if (res != Load_OK) return res; + + res = VerifyDSiNAND(); + if (res != Load_OK) return res; + } + else + { + res = VerifyDSFirmware(); + if (res != Load_OK) return res; + } // TODO: // original code in the libui frontend called NDS::LoadGBAROM() if needed @@ -142,6 +230,7 @@ int LoadBIOS() ROMPath[ROMSlot_NDS][0] = '\0'; SRAMPath[ROMSlot_NDS][0] = '\0'; + NDS::SetConsoleType(Config::ConsoleType); NDS::LoadBIOS(); SavestateLoaded = false; @@ -154,16 +243,39 @@ int LoadROM(const char* file, int slot) int res; bool directboot = Config::DirectBoot != 0; + if (Config::ConsoleType == 1 && slot == 1) + { + // cannot load a GBA ROM into a DSi + return Load_ROMLoadError; + } + res = VerifyDSBIOS(); if (res != Load_OK) return res; - res = VerifyDSFirmware(); - if (res != Load_OK) + if (Config::ConsoleType == 1) { - if (res == Load_FirmwareNotBootable) - directboot = true; - else - return res; + res = VerifyDSiBIOS(); + if (res != Load_OK) return res; + + res = VerifyDSiFirmware(); + if (res != Load_OK) return res; + + res = VerifyDSiNAND(); + if (res != Load_OK) return res; + + GBACart::Eject(); + ROMPath[ROMSlot_GBA][0] = '\0'; + } + else + { + res = VerifyDSFirmware(); + if (res != Load_OK) + { + if (res == Load_FirmwareNotBootable) + directboot = true; + else + return res; + } } char oldpath[1024]; @@ -177,6 +289,8 @@ int LoadROM(const char* file, int slot) SetupSRAMPath(0); SetupSRAMPath(1); + NDS::SetConsoleType(Config::ConsoleType); + if (slot == ROMSlot_NDS && NDS::LoadROM(ROMPath[slot], SRAMPath[slot], directboot)) { SavestateLoaded = false; @@ -225,17 +339,36 @@ int Reset() res = VerifyDSBIOS(); if (res != Load_OK) return res; - res = VerifyDSFirmware(); - if (res != Load_OK) + if (Config::ConsoleType == 1) { - if (res == Load_FirmwareNotBootable) - directboot = true; - else - return res; + res = VerifyDSiBIOS(); + if (res != Load_OK) return res; + + res = VerifyDSiFirmware(); + if (res != Load_OK) return res; + + res = VerifyDSiNAND(); + if (res != Load_OK) return res; + + GBACart::Eject(); + ROMPath[ROMSlot_GBA][0] = '\0'; + } + else + { + res = VerifyDSFirmware(); + if (res != Load_OK) + { + if (res == Load_FirmwareNotBootable) + directboot = true; + else + return res; + } } SavestateLoaded = false; + NDS::SetConsoleType(Config::ConsoleType); + if (ROMPath[ROMSlot_NDS][0] == '\0') { NDS::LoadBIOS(); diff --git a/src/frontend/qt_sdl/EmuSettingsDialog.cpp b/src/frontend/qt_sdl/EmuSettingsDialog.cpp index 7760a88..09faf4e 100644 --- a/src/frontend/qt_sdl/EmuSettingsDialog.cpp +++ b/src/frontend/qt_sdl/EmuSettingsDialog.cpp @@ -49,7 +49,7 @@ EmuSettingsDialog::EmuSettingsDialog(QWidget* parent) : QDialog(parent), ui(new ui->txtDSiNANDPath->setText(Config::DSiNANDPath); ui->cbxConsoleType->addItem("DS"); - ui->cbxConsoleType->addItem("DSi"); + ui->cbxConsoleType->addItem("DSi (experimental)"); ui->cbxConsoleType->setCurrentIndex(Config::ConsoleType); ui->chkDirectBoot->setChecked(Config::DirectBoot != 0); diff --git a/src/frontend/qt_sdl/main.cpp b/src/frontend/qt_sdl/main.cpp index ef21bc7..7b3d5cd 100644 --- a/src/frontend/qt_sdl/main.cpp +++ b/src/frontend/qt_sdl/main.cpp @@ -1360,17 +1360,40 @@ QString MainWindow::loadErrorStr(int error) { switch (error) { - case Frontend::Load_BIOS9Missing: return "DS ARM9 BIOS was not found or could not be accessed. Check your emu settings."; - case Frontend::Load_BIOS9Bad: return "DS ARM9 BIOS is not a valid BIOS dump."; - - case Frontend::Load_BIOS7Missing: return "DS ARM7 BIOS was not found or could not be accessed. Check your emu settings."; - case Frontend::Load_BIOS7Bad: return "DS ARM7 BIOS is not a valid BIOS dump."; - - case Frontend::Load_FirmwareMissing: return "DS firmware was not found or could not be accessed. Check your emu settings."; - case Frontend::Load_FirmwareBad: return "DS firmware is not a valid firmware dump."; - case Frontend::Load_FirmwareNotBootable: return "DS firmware is not bootable."; - - case Frontend::Load_ROMLoadError: return "Failed to load the ROM. Make sure the file is accessible and isn't used by another application."; + case Frontend::Load_BIOS9Missing: + return "DS ARM9 BIOS was not found or could not be accessed. Check your emu settings."; + case Frontend::Load_BIOS9Bad: + return "DS ARM9 BIOS is not a valid BIOS dump."; + + case Frontend::Load_BIOS7Missing: + return "DS ARM7 BIOS was not found or could not be accessed. Check your emu settings."; + case Frontend::Load_BIOS7Bad: + return "DS ARM7 BIOS is not a valid BIOS dump."; + + case Frontend::Load_FirmwareMissing: + return "DS firmware was not found or could not be accessed. Check your emu settings."; + case Frontend::Load_FirmwareBad: + return "DS firmware is not a valid firmware dump."; + case Frontend::Load_FirmwareNotBootable: + return "DS firmware is not bootable."; + + case Frontend::Load_DSiBIOS9Missing: + return "DSi ARM9 BIOS was not found or could not be accessed. Check your emu settings."; + case Frontend::Load_DSiBIOS9Bad: + return "DSi ARM9 BIOS is not a valid BIOS dump."; + + case Frontend::Load_DSiBIOS7Missing: + return "DSi ARM7 BIOS was not found or could not be accessed. Check your emu settings."; + case Frontend::Load_DSiBIOS7Bad: + return "DSi ARM7 BIOS is not a valid BIOS dump."; + + case Frontend::Load_DSiNANDMissing: + return "DSi NAND was not found or could not be accessed. Check your emu settings."; + case Frontend::Load_DSiNANDBad: + return "DSi NAND is not a valid NAND dump."; + + case Frontend::Load_ROMLoadError: + return "Failed to load the ROM. Make sure the file is accessible and isn't used by another application."; default: return "Unknown error during launch; smack Arisotura."; } -- cgit v1.2.3