From fc5eedc7169b38e9131ed125aa3e7db630b87804 Mon Sep 17 00:00:00 2001
From: Arisotura <thetotalworm@gmail.com>
Date: Mon, 15 Jun 2020 13:39:33 +0200
Subject: * take nwifi forward some * shut up CP15 printf's for Fx0 * fix bugs
---
src/NDS.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
(limited to 'src/NDS.cpp')
diff --git a/src/NDS.cpp b/src/NDS.cpp
index 22368ae..34a9da9 100644
--- a/src/NDS.cpp
+++ b/src/NDS.cpp
@@ -1756,14 +1756,14 @@ void debug(u32 param)
}
fclose(shit);*/
FILE*
- /*shit = fopen("debug/dump9.bin", "wb");
+ shit = fopen("debug/dump9.bin", "wb");
for (u32 i = 0x02000000; i < 0x04000000; i+=4)
{
u32 val = DSi::ARM9Read32(i);
fwrite(&val, 4, 1, shit);
}
- fclose(shit);*/
- shit = fopen("debug/dump7_2.bin", "wb");
+ fclose(shit);
+ shit = fopen("debug/dump7.bin", "wb");
for (u32 i = 0x02000000; i < 0x04000000; i+=4)
{
u32 val = DSi::ARM7Read32(i);
--
cgit v1.2.3
From 2f9a6b7c0346c31cbed34a006174d9a9b4efb79e Mon Sep 17 00:00:00 2001
From: Arisotura <thetotalworm@gmail.com>
Date: Thu, 23 Jul 2020 12:59:19 +0200
Subject: SPU: delay channel start until whenever it can actually start. fixes
maxmod interpolated mode.
---
src/NDS.cpp | 2 +-
src/SPU.cpp | 9 +++++++++
src/SPU.h | 3 ++-
3 files changed, 12 insertions(+), 2 deletions(-)
(limited to 'src/NDS.cpp')
diff --git a/src/NDS.cpp b/src/NDS.cpp
index 8cd7f93..2ad6bad 100644
--- a/src/NDS.cpp
+++ b/src/NDS.cpp
@@ -493,7 +493,7 @@ void Reset()
printf("ARM7 BIOS loaded\n");
fclose(f);
}
-
+
#ifdef JIT_ENABLED
ARMJIT::Reset();
#endif
diff --git a/src/SPU.cpp b/src/SPU.cpp
index 9f6b107..cd5c5b8 100644
--- a/src/SPU.cpp
+++ b/src/SPU.cpp
@@ -160,6 +160,8 @@ void Channel::Reset()
else
BusRead32 = NDS::ARM7Read32;
+ KeyOn = false;
+
SetCnt(0);
SrcAddr = 0;
TimerReload = 0;
@@ -187,6 +189,7 @@ void Channel::DoSavestate(Savestate* file)
file->Var8(&VolumeShift);
file->Var8(&Pan);
+ file->Var8((u8*)&KeyOn);
file->Var32(&Timer);
file->Var32((u32*)&Pos);
file->Var16((u16*)&CurSample);
@@ -417,6 +420,12 @@ void Channel::Run(s32* buf, u32 samples)
{
if (!(Cnt & (1<<31))) return;
+ if (KeyOn)
+ {
+ Start();
+ KeyOn = false;
+ }
+
for (u32 s = 0; s < samples; s++)
{
Timer += 512; // 1 sample = 512 cycles at 16MHz
diff --git a/src/SPU.h b/src/SPU.h
index 8ab17a0..964841d 100644
--- a/src/SPU.h
+++ b/src/SPU.h
@@ -69,6 +69,7 @@ public:
u8 VolumeShift;
u8 Pan;
+ bool KeyOn;
u32 Timer;
s32 Pos;
s16 CurSample;
@@ -105,7 +106,7 @@ public:
if ((val & (1<<31)) && !(oldcnt & (1<<31)))
{
- Start();
+ KeyOn = true;
}
}
--
cgit v1.2.3
From 8a96dfce18b8de93d8e6d5b21d7fa0ba9bbcab23 Mon Sep 17 00:00:00 2001
From: RSDuck <rsduck@users.noreply.github.com>
Date: Sat, 25 Jul 2020 20:59:53 +0200
Subject: fix build with JIT disabled fixes #675 and #674
---
src/ARM.cpp | 2 +-
src/ARM.h | 2 +-
src/CP15.cpp | 8 ++++++--
src/DSi.cpp | 38 ++++++++++++++++++++++++++++++++++++++
src/NDS.cpp | 2 ++
5 files changed, 48 insertions(+), 4 deletions(-)
(limited to 'src/NDS.cpp')
diff --git a/src/ARM.cpp b/src/ARM.cpp
index 8530795..ecf94cd 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -80,7 +80,7 @@ ARM::~ARM()
ARMv5::ARMv5() : ARM(0)
{
#ifndef JIT_ENABLED
- DTCM = new u8[DTCMSize];
+ DTCM = new u8[DTCMPhysicalSize];
#endif
}
diff --git a/src/ARM.h b/src/ARM.h
index 0248e26..ee6ac96 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -57,7 +57,7 @@ public:
}
virtual void Execute() = 0;
-#ifdef ENABLE_JIT
+#ifdef JIT_ENABLED
virtual void ExecuteJIT() = 0;
#endif
diff --git a/src/CP15.cpp b/src/CP15.cpp
index 992c83f..6ac31aa 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -21,9 +21,11 @@
#include "NDS.h"
#include "DSi.h"
#include "ARM.h"
+
+#ifdef JIT_ENABLED
#include "ARMJIT.h"
#include "ARMJIT_Memory.h"
-
+#endif
// access timing for cached regions
// this would be an average between cache hits and cache misses
@@ -105,7 +107,7 @@ void ARMv5::UpdateDTCMSetting()
{
newDTCMBase = DTCMSetting & 0xFFFFF000;
newDTCMSize = 0x200 << ((DTCMSetting >> 1) & 0x1F);
- //printf("DTCM [%08X] enabled at %08X, size %X\n", DTCMSetting, DTCMBase, DTCMSize);
+ //printf("DTCM [%08X] enabled at %08X, size %X\n", DTCMSetting, newDTCMBase, newDTCMSize);
}
else
{
@@ -115,7 +117,9 @@ void ARMv5::UpdateDTCMSetting()
}
if (newDTCMBase != DTCMBase || newDTCMSize != DTCMSize)
{
+#ifdef JIT_ENABLED
ARMJIT_Memory::RemapDTCM(newDTCMBase, newDTCMSize);
+#endif
DTCMBase = newDTCMBase;
DTCMSize = newDTCMSize;
}
diff --git a/src/DSi.cpp b/src/DSi.cpp
index 97a63cd..839fdbf 100644
--- a/src/DSi.cpp
+++ b/src/DSi.cpp
@@ -540,7 +540,9 @@ void MapNWRAM_A(u32 num, u8 val)
return;
}
+#ifdef JIT_ENABLED
ARMJIT_Memory::RemapNWRAM(0);
+#endif
int mbkn = 0, mbks = 8*num;
@@ -573,7 +575,9 @@ void MapNWRAM_B(u32 num, u8 val)
return;
}
+#ifdef JIT_ENABLED
ARMJIT_Memory::RemapNWRAM(1);
+#endif
int mbkn = 1+(num>>2), mbks = 8*(num&3);
@@ -610,7 +614,9 @@ void MapNWRAM_C(u32 num, u8 val)
return;
}
+#ifdef JIT_ENABLED
ARMJIT_Memory::RemapNWRAM(2);
+#endif
int mbkn = 3+(num>>2), mbks = 8*(num&3);
@@ -644,7 +650,9 @@ void MapNWRAMRange(u32 cpu, u32 num, u32 val)
u32 oldval = MBK[cpu][5+num];
if (oldval == val) return;
+#ifdef JIT_ENABLED
ARMJIT_Memory::RemapNWRAM(num);
+#endif
MBK[cpu][5+num] = val;
@@ -850,7 +858,9 @@ void ARM9Write8(u32 addr, u8 val)
if (ptr)
{
*(u8*)&ptr[addr & 0xFFFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
+#endif
}
return;
}
@@ -860,7 +870,9 @@ void ARM9Write8(u32 addr, u8 val)
if (ptr)
{
*(u8*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
+#endif
}
return;
}
@@ -870,7 +882,9 @@ void ARM9Write8(u32 addr, u8 val)
if (ptr)
{
*(u8*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
+#endif
}
return;
}
@@ -895,7 +909,9 @@ void ARM9Write16(u32 addr, u16 val)
if (ptr)
{
*(u16*)&ptr[addr & 0xFFFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
+#endif
}
return;
}
@@ -905,7 +921,9 @@ void ARM9Write16(u32 addr, u16 val)
if (ptr)
{
*(u16*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
+#endif
}
return;
}
@@ -915,7 +933,9 @@ void ARM9Write16(u32 addr, u16 val)
if (ptr)
{
*(u16*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
+#endif
}
return;
}
@@ -940,7 +960,9 @@ void ARM9Write32(u32 addr, u32 val)
if (ptr)
{
*(u32*)&ptr[addr & 0xFFFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
+#endif
}
return;
}
@@ -950,7 +972,9 @@ void ARM9Write32(u32 addr, u32 val)
if (ptr)
{
*(u32*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
+#endif
}
return;
}
@@ -960,7 +984,9 @@ void ARM9Write32(u32 addr, u32 val)
if (ptr)
{
*(u32*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
+#endif
}
return;
}
@@ -1196,7 +1222,9 @@ void ARM7Write16(u32 addr, u16 val)
if (ptr)
{
*(u16*)&ptr[addr & 0xFFFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
+#endif
}
return;
}
@@ -1206,7 +1234,9 @@ void ARM7Write16(u32 addr, u16 val)
if (ptr)
{
*(u16*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
+#endif
}
return;
}
@@ -1216,7 +1246,9 @@ void ARM7Write16(u32 addr, u16 val)
if (ptr)
{
*(u16*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
+#endif
}
return;
}
@@ -1241,7 +1273,9 @@ void ARM7Write32(u32 addr, u32 val)
if (ptr)
{
*(u32*)&ptr[addr & 0xFFFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
+#endif
}
return;
}
@@ -1251,7 +1285,9 @@ void ARM7Write32(u32 addr, u32 val)
if (ptr)
{
*(u32*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
+#endif
}
return;
}
@@ -1261,7 +1297,9 @@ void ARM7Write32(u32 addr, u32 val)
if (ptr)
{
*(u32*)&ptr[addr & 0x7FFF] = val;
+#ifdef JIT_ENABLED
ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
+#endif
}
return;
}
diff --git a/src/NDS.cpp b/src/NDS.cpp
index 2ad6bad..18ae3e9 100644
--- a/src/NDS.cpp
+++ b/src/NDS.cpp
@@ -1137,7 +1137,9 @@ void MapSharedWRAM(u8 val)
if (val == WRAMCnt)
return;
+#ifdef JIT_ENABLED
ARMJIT_Memory::RemapSWRAM();
+#endif
WRAMCnt = val;
--
cgit v1.2.3
From ea734084cad4334e0a1247be99320e37f3bd2ee1 Mon Sep 17 00:00:00 2001
From: RSDuck <rsduck@users.noreply.github.com>
Date: Mon, 27 Jul 2020 23:18:33 +0200
Subject: check DSi interrupts for halted processor wakeup
---
src/NDS.cpp | 3 +++
1 file changed, 3 insertions(+)
(limited to 'src/NDS.cpp')
diff --git a/src/NDS.cpp b/src/NDS.cpp
index 65c3223..823d39a 100644
--- a/src/NDS.cpp
+++ b/src/NDS.cpp
@@ -1270,6 +1270,9 @@ bool HaltInterrupted(u32 cpu)
if (IF[cpu] & IE[cpu])
return true;
+ if ((ConsoleType == 1) && cpu && (IF2 & IE2))
+ return true;
+
return false;
}
--
cgit v1.2.3