From 7335379127f3b39298c57b1a691f1650af31d381 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Tue, 18 Jun 2019 19:00:44 +0200 Subject: HARK HARK HARK --- src/DSi_NDMA.cpp | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 src/DSi_NDMA.cpp (limited to 'src/DSi_NDMA.cpp') diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp new file mode 100644 index 0000000..6a524dd --- /dev/null +++ b/src/DSi_NDMA.cpp @@ -0,0 +1,17 @@ +/* + Copyright 2016-2019 Arisotura + + This file is part of melonDS. + + melonDS is free software: you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation, either version 3 of the License, or (at your option) + any later version. + + melonDS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with melonDS. If not, see http://www.gnu.org/licenses/. +*/ -- cgit v1.2.3 From d6bbc6f0f1ede57f0805137617ba670a49f7506f Mon Sep 17 00:00:00 2001 From: Arisotura Date: Tue, 18 Jun 2019 22:54:07 +0200 Subject: tremble upon the NDMA implementation that doesn't do much beyond getting stuck --- src/DMA.cpp | 6 -- src/DSi.cpp | 171 +++++++++++++++++++++++++++++++ src/DSi.h | 4 + src/DSi_NDMA.cpp | 301 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/DSi_NDMA.h | 74 +++++++++++++- src/NDS.cpp | 4 + src/NDS.h | 5 +- 7 files changed, 556 insertions(+), 9 deletions(-) (limited to 'src/DSi_NDMA.cpp') diff --git a/src/DMA.cpp b/src/DMA.cpp index 2814264..0826d7a 100644 --- a/src/DMA.cpp +++ b/src/DMA.cpp @@ -20,15 +20,9 @@ #include "NDS.h" #include "DSi.h" #include "DMA.h" -#include "NDSCart.h" #include "GPU.h" -// NOTES ON DMA SHIT -// -// * could use optimized code paths for common types of DMA transfers. for example, VRAM -// have to profile it to see if it's actually worth doing - // DMA TIMINGS // diff --git a/src/DSi.cpp b/src/DSi.cpp index abd3bd6..0c9c26c 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -25,6 +25,7 @@ #include "sha1/sha1.h" #include "Platform.h" +#include "DSi_NDMA.h" #include "DSi_I2C.h" #include "DSi_SD.h" @@ -57,6 +58,9 @@ u32 NWRAMStart[2][3]; u32 NWRAMEnd[2][3]; u32 NWRAMMask[2][3]; +u32 NDMACnt[2]; +DSi_NDMA* NDMAs[8]; + DSi_SDHost* SDMMC; DSi_SDHost* SDIO; @@ -68,6 +72,15 @@ bool Init() { if (!DSi_I2C::Init()) return false; + NDMAs[0] = new DSi_NDMA(0, 0); + NDMAs[1] = new DSi_NDMA(0, 1); + NDMAs[2] = new DSi_NDMA(0, 2); + NDMAs[3] = new DSi_NDMA(0, 3); + NDMAs[4] = new DSi_NDMA(1, 0); + NDMAs[5] = new DSi_NDMA(1, 1); + NDMAs[6] = new DSi_NDMA(1, 2); + NDMAs[7] = new DSi_NDMA(1, 3); + SDMMC = new DSi_SDHost(0); SDIO = new DSi_SDHost(1); @@ -78,6 +91,8 @@ void DeInit() { DSi_I2C::DeInit(); + for (int i = 0; i < 8; i++) delete NDMAs[i]; + delete SDMMC; delete SDIO; } @@ -91,6 +106,9 @@ void Reset() NDS::ARM9->JumpTo(BootAddr[0]); NDS::ARM7->JumpTo(BootAddr[1]); + NDMACnt[0] = 0; NDMACnt[1] = 0; + for (int i = 0; i < 8; i++) NDMAs[i]->Reset(); + DSi_I2C::Reset(); SDMMC->Reset(); @@ -279,6 +297,40 @@ bool LoadNAND() } +void RunNDMAs(u32 cpu) +{ + // TODO: round-robin mode (requires DMA channels to have a subblock delay set) + + if (cpu == 0) + { + if (NDS::ARM9Timestamp >= NDS::ARM9Target) return; + + // + } + else + { + if (NDS::ARM7Timestamp >= NDS::ARM7Target) return; + + // + } +} + +void StallNDMAs() +{ + // TODO +} + +bool NDMAsRunning(u32 cpu) +{ + cpu <<= 2; + if (NDMAs[cpu+0]->IsRunning()) return true; + if (NDMAs[cpu+1]->IsRunning()) return true; + if (NDMAs[cpu+2]->IsRunning()) return true; + if (NDMAs[cpu+3]->IsRunning()) return true; + return false; +} + + // new WRAM mapping // TODO: find out what happens upon overlapping slots!! @@ -872,6 +924,36 @@ u32 ARM9IORead32(u32 addr) switch (addr) { case 0x04004010: return 1; // todo + + case 0x04004100: return NDMACnt[0]; + case 0x04004104: return NDMAs[0]->SrcAddr; + case 0x04004108: return NDMAs[0]->DstAddr; + case 0x0400410C: return NDMAs[0]->TotalLength; + case 0x04004110: return NDMAs[0]->BlockLength; + case 0x04004114: return NDMAs[0]->SubblockTimer; + case 0x04004118: return NDMAs[0]->FillData; + case 0x0400411C: return NDMAs[0]->Cnt; + case 0x04004120: return NDMAs[1]->SrcAddr; + case 0x04004124: return NDMAs[1]->DstAddr; + case 0x04004128: return NDMAs[1]->TotalLength; + case 0x0400412C: return NDMAs[1]->BlockLength; + case 0x04004130: return NDMAs[1]->SubblockTimer; + case 0x04004134: return NDMAs[1]->FillData; + case 0x04004138: return NDMAs[1]->Cnt; + case 0x0400413C: return NDMAs[2]->SrcAddr; + case 0x04004140: return NDMAs[2]->DstAddr; + case 0x04004144: return NDMAs[2]->TotalLength; + case 0x04004148: return NDMAs[2]->BlockLength; + case 0x0400414C: return NDMAs[2]->SubblockTimer; + case 0x04004150: return NDMAs[2]->FillData; + case 0x04004154: return NDMAs[2]->Cnt; + case 0x04004158: return NDMAs[3]->SrcAddr; + case 0x0400415C: return NDMAs[3]->DstAddr; + case 0x04004160: return NDMAs[3]->TotalLength; + case 0x04004164: return NDMAs[3]->BlockLength; + case 0x04004168: return NDMAs[3]->SubblockTimer; + case 0x0400416C: return NDMAs[3]->FillData; + case 0x04004170: return NDMAs[3]->Cnt; } return NDS::ARM9IORead32(addr); @@ -899,6 +981,35 @@ void ARM9IOWrite32(u32 addr, u32 val) { switch (addr) { + case 0x04004100: NDMACnt[0] = val & 0x800F0000; return; + case 0x04004104: NDMAs[0]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004108: NDMAs[0]->DstAddr = val & 0xFFFFFFFC; return; + case 0x0400410C: NDMAs[0]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004110: NDMAs[0]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004114: NDMAs[0]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004118: NDMAs[0]->FillData = val; return; + case 0x0400411C: NDMAs[0]->WriteCnt(val); return; + case 0x04004120: NDMAs[1]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004124: NDMAs[1]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004128: NDMAs[1]->TotalLength = val & 0x0FFFFFFF; return; + case 0x0400412C: NDMAs[1]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004130: NDMAs[1]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004134: NDMAs[1]->FillData = val; return; + case 0x04004138: NDMAs[1]->WriteCnt(val); return; + case 0x0400413C: NDMAs[2]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004140: NDMAs[2]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004144: NDMAs[2]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004148: NDMAs[2]->BlockLength = val & 0x00FFFFFF; return; + case 0x0400414C: NDMAs[2]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004150: NDMAs[2]->FillData = val; return; + case 0x04004154: NDMAs[2]->WriteCnt(val); return; + case 0x04004158: NDMAs[3]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x0400415C: NDMAs[3]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004160: NDMAs[3]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004164: NDMAs[3]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004168: NDMAs[3]->SubblockTimer = val & 0x0003FFFF; return; + case 0x0400416C: NDMAs[3]->FillData = val; return; + case 0x04004170: NDMAs[3]->WriteCnt(val); return; } return NDS::ARM9IOWrite32(addr, val); @@ -950,6 +1061,36 @@ u32 ARM7IORead32(u32 addr) case 0x0400021C: return NDS::IF2; case 0x04004008: return 0x80000000; // HAX + + case 0x04004100: return NDMACnt[1]; + case 0x04004104: return NDMAs[4]->SrcAddr; + case 0x04004108: return NDMAs[4]->DstAddr; + case 0x0400410C: return NDMAs[4]->TotalLength; + case 0x04004110: return NDMAs[4]->BlockLength; + case 0x04004114: return NDMAs[4]->SubblockTimer; + case 0x04004118: return NDMAs[4]->FillData; + case 0x0400411C: return NDMAs[4]->Cnt; + case 0x04004120: return NDMAs[5]->SrcAddr; + case 0x04004124: return NDMAs[5]->DstAddr; + case 0x04004128: return NDMAs[5]->TotalLength; + case 0x0400412C: return NDMAs[5]->BlockLength; + case 0x04004130: return NDMAs[5]->SubblockTimer; + case 0x04004134: return NDMAs[5]->FillData; + case 0x04004138: return NDMAs[5]->Cnt; + case 0x0400413C: return NDMAs[6]->SrcAddr; + case 0x04004140: return NDMAs[6]->DstAddr; + case 0x04004144: return NDMAs[6]->TotalLength; + case 0x04004148: return NDMAs[6]->BlockLength; + case 0x0400414C: return NDMAs[6]->SubblockTimer; + case 0x04004150: return NDMAs[6]->FillData; + case 0x04004154: return NDMAs[6]->Cnt; + case 0x04004158: return NDMAs[7]->SrcAddr; + case 0x0400415C: return NDMAs[7]->DstAddr; + case 0x04004160: return NDMAs[7]->TotalLength; + case 0x04004164: return NDMAs[7]->BlockLength; + case 0x04004168: return NDMAs[7]->SubblockTimer; + case 0x0400416C: return NDMAs[7]->FillData; + case 0x04004170: return NDMAs[7]->Cnt; } if (addr >= 0x04004800 && addr < 0x04004A00) @@ -1003,6 +1144,36 @@ void ARM7IOWrite32(u32 addr, u32 val) { case 0x04000218: NDS::IE2 = (val & 0x7FF7); NDS::UpdateIRQ(1); return; case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return; + + case 0x04004100: NDMACnt[1] = val & 0x800F0000; return; + case 0x04004104: NDMAs[4]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004108: NDMAs[4]->DstAddr = val & 0xFFFFFFFC; return; + case 0x0400410C: NDMAs[4]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004110: NDMAs[4]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004114: NDMAs[4]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004118: NDMAs[4]->FillData = val; return; + case 0x0400411C: NDMAs[4]->WriteCnt(val); return; + case 0x04004120: NDMAs[5]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004124: NDMAs[5]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004128: NDMAs[5]->TotalLength = val & 0x0FFFFFFF; return; + case 0x0400412C: NDMAs[5]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004130: NDMAs[5]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004134: NDMAs[5]->FillData = val; return; + case 0x04004138: NDMAs[5]->WriteCnt(val); return; + case 0x0400413C: NDMAs[6]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x04004140: NDMAs[6]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004144: NDMAs[6]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004148: NDMAs[6]->BlockLength = val & 0x00FFFFFF; return; + case 0x0400414C: NDMAs[6]->SubblockTimer = val & 0x0003FFFF; return; + case 0x04004150: NDMAs[6]->FillData = val; return; + case 0x04004154: NDMAs[6]->WriteCnt(val); return; + case 0x04004158: NDMAs[7]->SrcAddr = val & 0xFFFFFFFC; return; + case 0x0400415C: NDMAs[7]->DstAddr = val & 0xFFFFFFFC; return; + case 0x04004160: NDMAs[7]->TotalLength = val & 0x0FFFFFFF; return; + case 0x04004164: NDMAs[7]->BlockLength = val & 0x00FFFFFF; return; + case 0x04004168: NDMAs[7]->SubblockTimer = val & 0x0003FFFF; return; + case 0x0400416C: NDMAs[7]->FillData = val; return; + case 0x04004170: NDMAs[7]->WriteCnt(val); return; } if (addr >= 0x04004800 && addr < 0x04004A00) diff --git a/src/DSi.h b/src/DSi.h index efd533a..32253a7 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -38,6 +38,10 @@ void Reset(); bool LoadBIOS(); bool LoadNAND(); +void RunNDMAs(u32 cpu); +void StallNDMAs(); +bool NDMAsRunning(u32 cpu); + void MapNWRAM_A(u32 num, u8 val); void MapNWRAM_B(u32 num, u8 val); void MapNWRAM_C(u32 num, u8 val); diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index 6a524dd..a8055eb 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -15,3 +15,304 @@ You should have received a copy of the GNU General Public License along with melonDS. If not, see http://www.gnu.org/licenses/. */ + +#include +#include "NDS.h" +#include "DSi.h" +#include "DSi_NDMA.h" +#include "GPU.h" + + + +DSi_NDMA::DSi_NDMA(u32 cpu, u32 num) +{ + CPU = cpu; + Num = num; + + Reset(); +} + +DSi_NDMA::~DSi_NDMA() +{ +} + +void DSi_NDMA::Reset() +{ + SrcAddr = 0; + DstAddr = 0; + TotalLength = 0; + BlockLength = 0; + SubblockTimer = 0; + FillData = 0; + Cnt = 0; + + StartMode = 0; + CurSrcAddr = 0; + CurDstAddr = 0; + SubblockLength = 0; + RemCount = 0; + IterCount = 0; + TotalRemCount = 0; + SrcAddrInc = 0; + DstAddrInc = 0; + + Running = false; + InProgress = false; +} + +void DSi_NDMA::DoSavestate(Savestate* file) +{ + // TODO! +} + +void DSi_NDMA::WriteCnt(u32 val) +{ + u32 oldcnt = Cnt; + Cnt = val; + + if ((!(oldcnt & 0x80000000)) && (val & 0x80000000)) // checkme + { + CurSrcAddr = SrcAddr; + CurDstAddr = DstAddr; + TotalRemCount = TotalLength; + + switch ((Cnt >> 10) & 0x3) + { + case 0: DstAddrInc = 1; break; + case 1: DstAddrInc = -1; break; + case 2: DstAddrInc = 0; break; + case 3: DstAddrInc = 1; printf("BAD NDMA DST INC MODE 3\n"); break; + } + + switch ((Cnt >> 13) & 0x3) + { + case 0: SrcAddrInc = 1; break; + case 1: SrcAddrInc = -1; break; + case 2: SrcAddrInc = 0; break; + case 3: SrcAddrInc = 0; break; // fill mode + } + + StartMode = (Cnt >> 24) & 0x1F; + if (StartMode > 0x10) StartMode = 0x10; + if (CPU == 1) StartMode |= 0x20; + + if ((StartMode & 0x1F) == 0x10) + Start(); + + if (StartMode != 0x10 && StartMode != 0x30) + printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X\n", CPU?7:9, Num, StartMode, SrcAddr, DstAddr); + } +} + +void DSi_NDMA::Start() +{ + if (Running) return; + + if (!InProgress) + { + RemCount = BlockLength; + if (!RemCount) + RemCount = 0x1000000; + } + + // TODO: how does GXFIFO DMA work with all the block shito? + IterCount = RemCount; + + if (IterCount > TotalRemCount) + IterCount = TotalRemCount; + + if (Cnt & (1<<12)) CurDstAddr = DstAddr; + if (Cnt & (1<<15)) CurSrcAddr = SrcAddr; + + printf("ARM%d NDMA%d %08X %02X %08X->%08X %d bytes\n", CPU?7:9, Num, Cnt, StartMode, CurSrcAddr, CurDstAddr, RemCount*4); + + //IsGXFIFODMA = (CPU == 0 && (CurSrcAddr>>24) == 0x02 && CurDstAddr == 0x04000400 && DstAddrInc == 0); + + // TODO eventually: not stop if we're running code in ITCM + + if (SubblockTimer & 0xFFFF) + printf("TODO! NDMA SUBBLOCK TIMER: %08X\n", SubblockTimer); + + if (NDS::DMAsRunning(CPU)) + Running = 1; + else + Running = 2; + + InProgress = true; + NDS::StopCPU(CPU, 1<<(Num+4)); +} + +void DSi_NDMA::Run() +{ + if (!Running) return; + if (CPU == 0) return Run9(); + else return Run7(); +} + +void DSi_NDMA::Run9() +{ + if (NDS::ARM9Timestamp >= NDS::ARM9Target) return; + + Executing = true; + + // add NS penalty for first accesses in burst + bool burststart = (Running == 2); + Running = 1; + + s32 unitcycles; + //s32 lastcycles = cycles; + + bool dofill = ((Cnt >> 13) & 0x3) == 3; + + if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02) + { + unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2]; + } + else + { + unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][3] + NDS::ARM9MemTimings[CurDstAddr >> 14][3]; + if ((CurSrcAddr >> 24) == (CurDstAddr >> 24)) + unitcycles++; + else if ((CurSrcAddr >> 24) == 0x02) + unitcycles--; + + /*if (burststart) + { + cycles -= 2; + cycles -= (NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2]); + cycles += unitcycles; + }*/ + } + + while (IterCount > 0 && !Stall) + { + NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift); + + if (dofill) + DSi::ARM9Write32(CurDstAddr, FillData); + else + DSi::ARM9Write32(CurDstAddr, DSi::ARM9Read32(CurSrcAddr)); + + CurSrcAddr += SrcAddrInc<<2; + CurDstAddr += DstAddrInc<<2; + IterCount--; + RemCount--; + TotalRemCount--; + + if (NDS::ARM9Timestamp >= NDS::ARM9Target) break; + } + + Executing = false; + Stall = false; + + if (RemCount) + { + if (IterCount == 0) + { + Running = 0; + NDS::ResumeCPU(0, 1<<(Num+4)); + + //if (StartMode == 0x07) + // GPU3D::CheckFIFODMA(); + } + + return; + } + + if ((StartMode & 0x1F) == 0x10) // CHECKME + Cnt &= ~(1<<31); + else if (!(Cnt & (1<<29))) + { + if (TotalRemCount == 0) + Cnt &= ~(1<<31); + } + + if (Cnt & (1<<30)) + NDS::SetIRQ(0, NDS::IRQ_DSi_NDMA0 + Num); + + Running = 0; + InProgress = false; + NDS::ResumeCPU(0, 1<<(Num+4)); +} + +void DSi_NDMA::Run7() +{ + if (NDS::ARM7Timestamp >= NDS::ARM7Target) return; + + Executing = true; + + // add NS penalty for first accesses in burst + bool burststart = (Running == 2); + Running = 1; + + s32 unitcycles; + //s32 lastcycles = cycles; + + bool dofill = ((Cnt >> 13) & 0x3) == 3; + + if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02) + { + unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2]; + } + else + { + unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][3] + NDS::ARM7MemTimings[CurDstAddr >> 15][3]; + if ((CurSrcAddr >> 23) == (CurDstAddr >> 23)) + unitcycles++; + else if ((CurSrcAddr >> 24) == 0x02) + unitcycles--; + + /*if (burststart) + { + cycles -= 2; + cycles -= (NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2]); + cycles += unitcycles; + }*/ + } + + while (IterCount > 0 && !Stall) + { + NDS::ARM7Timestamp += unitcycles; + + if (dofill) + DSi::ARM7Write32(CurDstAddr, FillData); + else + DSi::ARM7Write32(CurDstAddr, DSi::ARM7Read32(CurSrcAddr)); + + CurSrcAddr += SrcAddrInc<<2; + CurDstAddr += DstAddrInc<<2; + IterCount--; + RemCount--; + + if (NDS::ARM7Timestamp >= NDS::ARM7Target) break; + } + + Executing = false; + Stall = false; + + if (RemCount) + { + if (IterCount == 0) + { + Running = 0; + NDS::ResumeCPU(1, 1<<(Num+4)); + } + + return; + } + + if ((StartMode & 0x1F) == 0x10) // CHECKME + Cnt &= ~(1<<31); + else if (!(Cnt & (1<<29))) + { + if (TotalRemCount == 0) + Cnt &= ~(1<<31); + } + + if (Cnt & (1<<30)) + NDS::SetIRQ(1, NDS::IRQ_DSi_NDMA0 + Num); + + Running = 0; + InProgress = false; + NDS::ResumeCPU(1, 1<<(Num+4)); +} diff --git a/src/DSi_NDMA.h b/src/DSi_NDMA.h index 6661652..d7b7483 100644 --- a/src/DSi_NDMA.h +++ b/src/DSi_NDMA.h @@ -19,6 +19,78 @@ #ifndef DSI_NDMA_H #define DSI_NDMA_H -// +#include "types.h" + +class DSi_NDMA +{ +public: + DSi_NDMA(u32 cpu, u32 num); + ~DSi_NDMA(); + + void Reset(); + + void DoSavestate(Savestate* file); + + void WriteCnt(u32 val); + void Start(); + + void Run(); + + void Run9(); + void Run7(); + + bool IsInMode(u32 mode) + { + return ((mode == StartMode) && (Cnt & 0x80000000)); + } + + bool IsRunning() { return Running!=0; } + + void StartIfNeeded(u32 mode) + { + if ((mode == StartMode) && (Cnt & 0x80000000)) + Start(); + } + + void StopIfNeeded(u32 mode) + { + if (mode == StartMode) + Cnt &= ~0x80000000; + } + + void StallIfRunning() + { + if (Executing) Stall = true; + } + + u32 SrcAddr; + u32 DstAddr; + u32 TotalLength; // total length, when transferring multiple blocks + u32 BlockLength; // length of one transfer + u32 SubblockTimer; // optional delay between subblocks (only in round-robin mode) + u32 FillData; + u32 Cnt; + +private: + u32 CPU, Num; + + u32 StartMode; + u32 CurSrcAddr; + u32 CurDstAddr; + u32 SubblockLength; // length transferred per run when delay is used + u32 RemCount; + u32 IterCount; + u32 TotalRemCount; + u32 SrcAddrInc; + u32 DstAddrInc; + + u32 Running; + bool InProgress; + + bool Executing; + bool Stall; + + bool IsGXFIFODMA; +}; #endif // DSI_NDMA_H diff --git a/src/NDS.cpp b/src/NDS.cpp index 414f87c..e20f62f 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -827,6 +827,7 @@ u32 RunFrame() if (!(CPUStop & 0x80000000)) DMAs[1]->Run(); if (!(CPUStop & 0x80000000)) DMAs[2]->Run(); if (!(CPUStop & 0x80000000)) DMAs[3]->Run(); + DSi::RunNDMAs(0); } else { @@ -849,6 +850,7 @@ u32 RunFrame() DMAs[5]->Run(); DMAs[6]->Run(); DMAs[7]->Run(); + DSi::RunNDMAs(1); } else { @@ -1153,6 +1155,7 @@ void GXFIFOStall() DMAs[1]->StallIfRunning(); DMAs[2]->StallIfRunning(); DMAs[3]->StallIfRunning(); + DSi::StallNDMAs(); } } @@ -1367,6 +1370,7 @@ bool DMAsRunning(u32 cpu) if (DMAs[cpu+1]->IsRunning()) return true; if (DMAs[cpu+2]->IsRunning()) return true; if (DMAs[cpu+3]->IsRunning()) return true; + if (DSi::NDMAsRunning(cpu>>2)) return true; return false; } diff --git a/src/NDS.h b/src/NDS.h index f87ffed..850e829 100644 --- a/src/NDS.h +++ b/src/NDS.h @@ -101,7 +101,7 @@ enum IRQ2_DSi_GPIO18_0 = 0, IRQ2_DSi_GPIO18_1, IRQ2_DSi_GPIO18_2, - IRQ2_DSi_Unused35, + IRQ2_DSi_Unused3, IRQ2_DSi_GPIO33_0, IRQ2_DSi_Headphone, IRQ2_DSi_PowerButton, @@ -138,7 +138,6 @@ extern u64 ARM9Timestamp, ARM9Target; extern u64 ARM7Timestamp, ARM7Target; extern u32 ARM9ClockShift; -// hax extern u32 IME[2]; extern u32 IE[2]; extern u32 IF[2]; @@ -146,6 +145,8 @@ extern u32 IE2; extern u32 IF2; extern Timer Timers[8]; +extern u32 CPUStop; + extern u16 PowerControl9; extern u16 ExMemCnt[2]; -- cgit v1.2.3 From b1ed835ae91d9bb507d4d7b2084bbcdcce729e2d Mon Sep 17 00:00:00 2001 From: Arisotura Date: Tue, 18 Jun 2019 23:05:36 +0200 Subject: might be more impressive if it actually worked, like this --- src/DSi_NDMA.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/DSi_NDMA.cpp') diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index a8055eb..7c0b2a1 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -118,13 +118,16 @@ void DSi_NDMA::Start() // TODO: how does GXFIFO DMA work with all the block shito? IterCount = RemCount; - if (IterCount > TotalRemCount) - IterCount = TotalRemCount; + if (((StartMode & 0x1F) != 0x10) && !(Cnt & (1<<29))) + { + if (IterCount > TotalRemCount) + IterCount = TotalRemCount; + } if (Cnt & (1<<12)) CurDstAddr = DstAddr; if (Cnt & (1<<15)) CurSrcAddr = SrcAddr; - printf("ARM%d NDMA%d %08X %02X %08X->%08X %d bytes\n", CPU?7:9, Num, Cnt, StartMode, CurSrcAddr, CurDstAddr, RemCount*4); + printf("ARM%d NDMA%d %08X %02X %08X->%08X %d bytes, total=%d\n", CPU?7:9, Num, Cnt, StartMode, CurSrcAddr, CurDstAddr, RemCount*4, TotalRemCount*4); //IsGXFIFODMA = (CPU == 0 && (CurSrcAddr>>24) == 0x02 && CurDstAddr == 0x04000400 && DstAddrInc == 0); -- cgit v1.2.3 From 81dde71ebac19cf9a68dd7a2a41561cbcbfacc68 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Wed, 19 Jun 2019 14:24:49 +0200 Subject: add AES, fix a bunch of bugs we're getting an error screen! wee --- src/ARM.cpp | 37 ------- src/DSi.cpp | 55 ++++++++++ src/DSi.h | 3 + src/DSi_AES.cpp | 303 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/DSi_AES.h | 26 ++++- src/DSi_NDMA.cpp | 21 ++-- src/DSi_SD.cpp | 21 ++-- src/NDS.cpp | 6 +- 8 files changed, 416 insertions(+), 56 deletions(-) (limited to 'src/DSi_NDMA.cpp') diff --git a/src/ARM.cpp b/src/ARM.cpp index 60dec9a..b7fe3c7 100644 --- a/src/ARM.cpp +++ b/src/ARM.cpp @@ -239,36 +239,6 @@ void ARMv4::JumpTo(u32 addr, bool restorecpsr) else addr &= ~0x1; } - /*if (addr==0x037D4668) printf("MYSTERY START\n"); - if (addr==0x037CA71C) printf("MYSTERY END\n"); - if (addr==0x037CCD68) printf("atomic_store %08X %08X, %08X\n", R[0], R[1], R[15]); - if (addr==0x037CDD00) printf("zog %08X\n", R[15]);*/ - /*if (addr==0x037CDC00) printf("sendcmd %08X %08X\n", R[0], R[15]); - if (addr==0x037CA700) printf("prepare CID, %08X\n", R[15]); - if(addr==0x037D4498) printf("READ SHITTY FIFO. %08X\n", R[15]); - if (addr==0x037CCD68) printf("atomic_store %08X %08X, %08X\n", R[0], R[1], R[15]); - if (addr>=0x037CEE00 && addr<=0x037CEE30) printf("shitty loop: %08X->%08X\n", R[15], addr); - if (R[15]==0x037CCD8C) printf("BERG!!! %08X\n", addr); - if (addr==0x037CD600) printf("XFER IRQ HANDLER\n"); - if (R[15]==0x037CD62C) printf("TERRIBLE HANDLER: %08X\n", addr); - if (addr==0x037CCE24) printf("SD IRQ HANDLER\n"); - if (addr==0x037CCD94) printf("atomic_load %08X %08X, %08X\n", R[0], R[1], R[15]); - if (addr==0x037CEB7C) printf("CHECK CSR RESULT. %08X %08X %08X, %08X\n", R[0], R[1], R[2], R[15]); - if (R[15]==0x037CEC6C) printf("RETURN FROM CSR CHECK: %08X %08X\n", R[0], R[3]+0x38); - if (addr==0x037CB2AC) printf("ZOG!\n"); - if (addr==0x037CB2A0) printf("GONP %08X %08X, %08X\n", R[1]+0x28, R[3]+0x34, R[15]); - if (addr==0x037CCFC0) printf("SDMMC TIMEOUT. %08X\n", R[15]); - if (addr==0x037D68A8) printf("BARKBARKBARK. %08X\n", R[15]); - if (addr==0x037CCF04) printf("BAKAAA\n"); - if (addr==0x037D6988) printf("MORPMORPMORPMORPMORPMORPMORPMORPMORP %08X\n", R[15]); - if (addr==0x37D6904) printf("TIMEOUT FARTORED! %08X, %08X %08X, %08X\n", R[4], R[3], R[12], R[15]); - // TIMEOUT FARTORED! 037E89B8, 00000000 00200BFB, 037D68FC - if (addr==0x037CD660) printf("BRAAAAAAAAAAAP %08X\n", R[15]); - if (addr==0x037CD798) printf("BRAAPP SHATORED. %08X, %08X %08X\n", R[0], R[1], R[2]); - if (addr==0x037CCD34) printf("atomic_and %08X %08X, %08X\n", R[0], R[1], R[15]);*/ - // atomic_and 0400481C 0000FFE7, 037CD850 - - u32 oldregion = R[15] >> 23; u32 newregion = addr >> 23; @@ -607,13 +577,6 @@ void ARMv4::Execute() } else AddCycles_C(); - - /*if (R[15]==0x037CEE18) printf("SHITTY POINTER = %08X\n", R[0]+0x34); - if (R[15]==0x037CEE1C) printf("SHITTY FLAG = %08X\n", R[0]); - if (R[15]==0x037D68F0) printf("TIMESTAMP THING = %08X:%08X, CUR=%08X:%08X, ptr=%08X\n", - R[3], R[12], R[1], R[0], R[4]); - //if (R[15]==0x037CB29C) printf("GLORG!!! %08X\n", R[3]+0x34); 037E8A8C - if (R[15]==0x037CD730) printf("COUNT OF SHITO. %08X %08X\n", R[0], R[2]);*/ } // TODO optimize this shit!!! diff --git a/src/DSi.cpp b/src/DSi.cpp index fc590e1..fd58872 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -28,6 +28,7 @@ #include "DSi_NDMA.h" #include "DSi_I2C.h" #include "DSi_SD.h" +#include "DSi_AES.h" namespace NDS @@ -71,6 +72,7 @@ u8 eMMC_CID[16]; bool Init() { if (!DSi_I2C::Init()) return false; + if (!DSi_AES::Init()) return false; NDMAs[0] = new DSi_NDMA(0, 0); NDMAs[1] = new DSi_NDMA(0, 1); @@ -90,6 +92,7 @@ bool Init() void DeInit() { DSi_I2C::DeInit(); + DSi_AES::DeInit(); for (int i = 0; i < 8; i++) delete NDMAs[i]; @@ -110,6 +113,7 @@ void Reset() for (int i = 0; i < 8; i++) NDMAs[i]->Reset(); DSi_I2C::Reset(); + DSi_AES::Reset(); SDMMC->Reset(); SDIO->Reset(); @@ -336,6 +340,24 @@ bool NDMAsRunning(u32 cpu) return false; } +void CheckNDMAs(u32 cpu, u32 mode) +{ + cpu <<= 2; + NDMAs[cpu+0]->StartIfNeeded(mode); + NDMAs[cpu+1]->StartIfNeeded(mode); + NDMAs[cpu+2]->StartIfNeeded(mode); + NDMAs[cpu+3]->StartIfNeeded(mode); +} + +void StopNDMAs(u32 cpu, u32 mode) +{ + cpu <<= 2; + NDMAs[cpu+0]->StopIfNeeded(mode); + NDMAs[cpu+1]->StopIfNeeded(mode); + NDMAs[cpu+2]->StopIfNeeded(mode); + NDMAs[cpu+3]->StopIfNeeded(mode); +} + // new WRAM mapping // TODO: find out what happens upon overlapping slots!! @@ -1097,6 +1119,9 @@ u32 ARM7IORead32(u32 addr) case 0x04004168: return NDMAs[7]->SubblockTimer; case 0x0400416C: return NDMAs[7]->FillData; case 0x04004170: return NDMAs[7]->Cnt; + + case 0x04004400: return DSi_AES::ReadCnt(); + case 0x0400440C: return DSi_AES::ReadOutputFIFO(); } if (addr >= 0x04004800 && addr < 0x04004A00) @@ -1182,6 +1207,36 @@ void ARM7IOWrite32(u32 addr, u32 val) case 0x04004168: NDMAs[7]->SubblockTimer = val & 0x0003FFFF; return; case 0x0400416C: NDMAs[7]->FillData = val; return; case 0x04004170: NDMAs[7]->WriteCnt(val); return; + + case 0x04004400: DSi_AES::WriteCnt(val); return; + case 0x04004404: DSi_AES::WriteBlkCnt(val); return; + case 0x04004408: DSi_AES::WriteInputFIFO(val); return; + } + + if (addr >= 0x04004420 && addr < 0x04004430) + { + addr -= 0x04004420; + DSi_AES::WriteIV(addr, val, 0xFFFFFFFF); + return; + } + if (addr >= 0x04004430 && addr < 0x04004440) + { + addr -= 0x04004430; + DSi_AES::WriteMAC(addr, val, 0xFFFFFFFF); + return; + } + if (addr >= 0x04004440 && addr < 0x04004500) + { + addr -= 0x04004440; + int n = 0; + while (addr > 0x30) { addr -= 0x30; n++; } + + switch (addr >> 4) + { + case 0: DSi_AES::WriteKeyNormal(n, addr&0xF, val, 0xFFFFFFFF); return; + case 1: DSi_AES::WriteKeyX(n, addr&0xF, val, 0xFFFFFFFF); return; + case 2: DSi_AES::WriteKeyY(n, addr&0xF, val, 0xFFFFFFFF); return; + } } if (addr >= 0x04004800 && addr < 0x04004A00) diff --git a/src/DSi.h b/src/DSi.h index 32253a7..642a56a 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -26,6 +26,7 @@ namespace DSi { extern u8 eMMC_CID[16]; +extern u64 ConsoleID; extern DSi_SDHost* SDMMC; extern DSi_SDHost* SDIO; @@ -41,6 +42,8 @@ bool LoadNAND(); void RunNDMAs(u32 cpu); void StallNDMAs(); bool NDMAsRunning(u32 cpu); +void CheckNDMAs(u32 cpu, u32 mode); +void StopNDMAs(u32 cpu, u32 mode); void MapNWRAM_A(u32 num, u8 val); void MapNWRAM_B(u32 num, u8 val); diff --git a/src/DSi_AES.cpp b/src/DSi_AES.cpp index 6a524dd..8271e3e 100644 --- a/src/DSi_AES.cpp +++ b/src/DSi_AES.cpp @@ -15,3 +15,306 @@ You should have received a copy of the GNU General Public License along with melonDS. If not, see http://www.gnu.org/licenses/. */ + +#include +#include +#include "DSi.h" +#include "DSi_AES.h" +#include "FIFO.h" +#include "tiny-AES-c/aes.hpp" + + +namespace DSi_AES +{ + +u32 Cnt; + +u32 BlkCnt; +u32 RemBlocks; + +u32 InputDMASize, OutputDMASize; +u32 AESMode; + +FIFO* InputFIFO; +FIFO* OutputFIFO; + +u8 IV[16]; + +u8 KeyNormal[4][16]; +u8 KeyX[4][16]; +u8 KeyY[4][16]; + +u8 CurKey[16]; + +AES_ctx Ctx; + + +void Swap16(u8* dst, u8* src) +{ + for (int i = 0; i < 16; i++) + dst[i] = src[15-i]; +} + +void ROL16(u8* val, u32 n) +{ + u32 n_coarse = n >> 3; + u32 n_fine = n & 7; + u8 tmp[16]; + + for (u32 i = 0; i < 16; i++) + { + tmp[i] = val[(i - n_coarse) & 0xF]; + } + + for (u32 i = 0; i < 16; i++) + { + val[i] = (tmp[i] << n_fine) | (tmp[(i - 1) & 0xF] >> (8-n_fine)); + } +} + +#define _printhex(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); printf("\n"); } + + +bool Init() +{ + InputFIFO = new FIFO(16); + OutputFIFO = new FIFO(16); + + const u8 zero[16] = {0}; + AES_init_ctx_iv(&Ctx, zero, zero); + + return true; +} + +void DeInit() +{ + delete InputFIFO; + delete OutputFIFO; +} + +void Reset() +{ + Cnt = 0; + + BlkCnt = 0; + RemBlocks = 0; + + InputDMASize = 0; + OutputDMASize = 0; + AESMode = 0; + + InputFIFO->Clear(); + OutputFIFO->Clear(); + + memset(KeyNormal, 0, sizeof(KeyNormal)); + memset(KeyX, 0, sizeof(KeyX)); + memset(KeyY, 0, sizeof(KeyY)); + + memset(CurKey, 0, sizeof(CurKey)); + + // initialize keys, as per GBAtek + + // slot 3: console-unique eMMC crypto + *(u32*)&KeyX[3][0] = (u32)DSi::ConsoleID; + *(u32*)&KeyX[3][4] = (u32)DSi::ConsoleID ^ 0x24EE6906; + *(u32*)&KeyX[3][8] = (u32)(DSi::ConsoleID >> 32) ^ 0xE65B601D; + *(u32*)&KeyX[3][12] = (u32)(DSi::ConsoleID >> 32); + *(u32*)&KeyY[3][0] = 0x0AB9DC76; + *(u32*)&KeyY[3][4] = 0xBD4DC4D3; + *(u32*)&KeyY[3][8] = 0x202DDD1D; +} + + +void ProcessBlock_CTR() +{ + u8 data[16]; + u8 data_rev[16]; + + *(u32*)&data[0] = InputFIFO->Read(); + *(u32*)&data[4] = InputFIFO->Read(); + *(u32*)&data[8] = InputFIFO->Read(); + *(u32*)&data[12] = InputFIFO->Read(); + + //printf("AES-CTR: INPUT: "); _printhex(data, 16); + + Swap16(data_rev, data); + AES_CTR_xcrypt_buffer(&Ctx, data_rev, 16); + Swap16(data, data_rev); + + //printf("AES-CTR: OUTPUT: "); _printhex(data, 16); + + OutputFIFO->Write(*(u32*)&data[0]); + OutputFIFO->Write(*(u32*)&data[4]); + OutputFIFO->Write(*(u32*)&data[8]); + OutputFIFO->Write(*(u32*)&data[12]); +} + + +u32 ReadCnt() +{ + u32 ret = Cnt; + + ret |= InputFIFO->Level(); + ret |= (OutputFIFO->Level() << 5); + + return ret; +} + +void WriteCnt(u32 val) +{ + u32 oldcnt = Cnt; + Cnt = val & 0xFC1FF000; + + if (val & (1<<10)) InputFIFO->Clear(); + if (val & (1<<11)) OutputFIFO->Clear(); + + u32 dmasize[4] = {4, 8, 12, 16}; + InputDMASize = dmasize[3 - ((val >> 12) & 0x3)]; + OutputDMASize = dmasize[(val >> 14) & 0x3]; + + AESMode = (val >> 28) & 0x3; + if (AESMode < 2) printf("AES-CCM TODO\n"); + + if (val & (1<<24)) + { + u32 slot = (val >> 26) & 0x3; + memcpy(CurKey, KeyNormal[slot], 16); + + //printf("AES: key(%d): ", slot); _printhex(CurKey, 16); + + u8 tmp[16]; + Swap16(tmp, CurKey); + AES_init_ctx(&Ctx, tmp); + } + + if (!(oldcnt & (1<<31)) && (val & (1<<31))) + { + // transfer start (checkme) + RemBlocks = BlkCnt >> 16; + } + + printf("AES CNT: %08X / mode=%d inDMA=%d outDMA=%d blocks=%d\n", + val, AESMode, InputDMASize, OutputDMASize, RemBlocks); +} + +void WriteBlkCnt(u32 val) +{ + BlkCnt = val; +} + +u32 ReadOutputFIFO() +{ + return OutputFIFO->Read(); +} + +void WriteInputFIFO(u32 val) +{ + // TODO: add some delay to processing + + InputFIFO->Write(val); + + if (!(Cnt & (1<<31))) return; + + while (InputFIFO->Level() >= 4 && RemBlocks > 0) + { + switch (AESMode) + { + case 2: + case 3: ProcessBlock_CTR(); break; + default: + // dorp + OutputFIFO->Write(InputFIFO->Read()); + OutputFIFO->Write(InputFIFO->Read()); + OutputFIFO->Write(InputFIFO->Read()); + OutputFIFO->Write(InputFIFO->Read()); + } + + RemBlocks--; + } + + if (OutputFIFO->Level() >= OutputDMASize) + { + // trigger DMA + DSi::CheckNDMAs(1, 0x2B); + } + // TODO: DMA the other way around + + if (RemBlocks == 0) + { + Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ2(NDS::IRQ2_DSi_AES); + } +} + + +void WriteIV(u32 offset, u32 val, u32 mask) +{ + u32 old = *(u32*)&IV[offset]; + + *(u32*)&IV[offset] = (old & ~mask) | (val & mask); + + //printf("AES: IV: "); _printhex(IV, 16); + + u8 tmp[16]; + Swap16(tmp, IV); + AES_ctx_set_iv(&Ctx, tmp); +} + +void WriteMAC(u32 offset, u32 val, u32 mask) +{ + // +} + +void DeriveNormalKey(u32 slot) +{ + const u8 key_const[16] = {0xFF, 0xFE, 0xFB, 0x4E, 0x29, 0x59, 0x02, 0x58, 0x2A, 0x68, 0x0F, 0x5F, 0x1A, 0x4F, 0x3E, 0x79}; + u8 tmp[16]; + + //printf("keyX: "); _printhex(KeyX[slot], 16); + //printf("keyY: "); _printhex(KeyY[slot], 16); + + for (int i = 0; i < 16; i++) + tmp[i] = KeyX[slot][i] ^ KeyY[slot][i]; + + u32 carry = 0; + for (int i = 0; i < 16; i++) + { + u32 res = tmp[i] + key_const[15-i] + carry; + tmp[i] = res & 0xFF; + carry = res >> 8; + } + + ROL16(tmp, 42); + + //printf("derive normalkey %d\n", slot); _printhex(tmp, 16); + + memcpy(KeyNormal[slot], tmp, 16); +} + +void WriteKeyNormal(u32 slot, u32 offset, u32 val, u32 mask) +{ + u32 old = *(u32*)&KeyNormal[slot][offset]; + + *(u32*)&KeyNormal[slot][offset] = (old & ~mask) | (val & mask); +} + +void WriteKeyX(u32 slot, u32 offset, u32 val, u32 mask) +{ + u32 old = *(u32*)&KeyX[slot][offset]; + + *(u32*)&KeyX[slot][offset] = (old & ~mask) | (val & mask); +} + +void WriteKeyY(u32 slot, u32 offset, u32 val, u32 mask) +{ + u32 old = *(u32*)&KeyY[slot][offset]; + + *(u32*)&KeyY[slot][offset] = (old & ~mask) | (val & mask); + + if (offset >= 0xC) + { + DeriveNormalKey(slot); + } +} + +} diff --git a/src/DSi_AES.h b/src/DSi_AES.h index 028523a..7c388f5 100644 --- a/src/DSi_AES.h +++ b/src/DSi_AES.h @@ -19,6 +19,30 @@ #ifndef DSI_AES_H #define DSI_AES_H -// +#include "types.h" + +namespace DSi_AES +{ + +extern u32 Cnt; + +bool Init(); +void DeInit(); +void Reset(); + +u32 ReadCnt(); +void WriteCnt(u32 val); +void WriteBlkCnt(u32 val); + +u32 ReadOutputFIFO(); +void WriteInputFIFO(u32 val); + +void WriteIV(u32 offset, u32 val, u32 mask); +void WriteMAC(u32 offset, u32 val, u32 mask); +void WriteKeyNormal(u32 slot, u32 offset, u32 val, u32 mask); +void WriteKeyX(u32 slot, u32 offset, u32 val, u32 mask); +void WriteKeyY(u32 slot, u32 offset, u32 val, u32 mask); + +} #endif // DSI_AES_H diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index 7c0b2a1..aed78af 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -99,7 +99,8 @@ void DSi_NDMA::WriteCnt(u32 val) if ((StartMode & 0x1F) == 0x10) Start(); - if (StartMode != 0x10 && StartMode != 0x30) + if (StartMode != 0x10 && StartMode != 0x30 && + StartMode != 0x2B) printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X\n", CPU?7:9, Num, StartMode, SrcAddr, DstAddr); } } @@ -223,16 +224,19 @@ void DSi_NDMA::Run9() } if ((StartMode & 0x1F) == 0x10) // CHECKME + { Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ(0, NDS::IRQ_DSi_NDMA0 + Num); + } else if (!(Cnt & (1<<29))) { if (TotalRemCount == 0) + { Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ(0, NDS::IRQ_DSi_NDMA0 + Num); + } } - if (Cnt & (1<<30)) - NDS::SetIRQ(0, NDS::IRQ_DSi_NDMA0 + Num); - Running = 0; InProgress = false; NDS::ResumeCPU(0, 1<<(Num+4)); @@ -305,16 +309,19 @@ void DSi_NDMA::Run7() } if ((StartMode & 0x1F) == 0x10) // CHECKME + { Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ(1, NDS::IRQ_DSi_NDMA0 + Num); + } else if (!(Cnt & (1<<29))) { if (TotalRemCount == 0) + { Cnt &= ~(1<<31); + if (Cnt & (1<<30)) NDS::SetIRQ(1, NDS::IRQ_DSi_NDMA0 + Num); + } } - if (Cnt & (1<<30)) - NDS::SetIRQ(1, NDS::IRQ_DSi_NDMA0 + Num); - Running = 0; InProgress = false; NDS::ResumeCPU(1, 1<<(Num+4)); diff --git a/src/DSi_SD.cpp b/src/DSi_SD.cpp index 42b515c..bb3c4a4 100644 --- a/src/DSi_SD.cpp +++ b/src/DSi_SD.cpp @@ -473,10 +473,10 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param) case 2: case 10: // get CID - Host->SendResponse(*(u32*)&CID[0], false); - Host->SendResponse(*(u32*)&CID[1], false); - Host->SendResponse(*(u32*)&CID[2], false); - Host->SendResponse(*(u32*)&CID[3], true); + Host->SendResponse(*(u32*)&CID[12], false); + Host->SendResponse(*(u32*)&CID[8], false); + Host->SendResponse(*(u32*)&CID[4], false); + Host->SendResponse(*(u32*)&CID[0], true); //if (cmd == 2) SetState(0x02); return; @@ -502,13 +502,18 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param) return; case 9: // get CSD - Host->SendResponse(*(u32*)&CSD[0], false); - Host->SendResponse(*(u32*)&CSD[1], false); - Host->SendResponse(*(u32*)&CSD[2], false); - Host->SendResponse(*(u32*)&CSD[3], true); + Host->SendResponse(*(u32*)&CSD[12], false); + Host->SendResponse(*(u32*)&CSD[8], false); + Host->SendResponse(*(u32*)&CSD[4], false); + Host->SendResponse(*(u32*)&CSD[0], true); return; case 12: // stop operation + // TODO + Host->SendResponse(CSR, true); + return; + + case 13: // get status Host->SendResponse(CSR, true); return; diff --git a/src/NDS.cpp b/src/NDS.cpp index e20f62f..7513d57 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -1582,12 +1582,12 @@ void debug(u32 param) printf("ARM7 PC=%08X LR=%08X %08X\n", ARM7->R[15], ARM7->R[14], ARM7->R_IRQ[1]); printf("ARM9 IME=%08X IE=%08X IF=%08X\n", IME[0], IE[0], IF[0]); - printf("ARM7 IME=%08X IE=%08X IF=%08X\n", IME[1], IE[1], IF[1]); + printf("ARM7 IME=%08X IE=%08X IF=%08X IE2=%04X IF2=%04X\n", IME[1], IE[1], IF[1], IE2, IF2); //for (int i = 0; i < 9; i++) // printf("VRAM %c: %02X\n", 'A'+i, GPU::VRAMCNT[i]); - FILE* + /*FILE* shit = fopen("debug/card.bin", "wb"); for (u32 i = 0x02000000; i < 0x02400000; i+=4) { @@ -1599,7 +1599,7 @@ void debug(u32 param) u32 val = ARM7Read32(i); fwrite(&val, 4, 1, shit); } - fclose(shit); + fclose(shit);*/ } -- cgit v1.2.3 From dcae9788e510e44341b7535c267262b89667720b Mon Sep 17 00:00:00 2001 From: Arisotura Date: Wed, 19 Jun 2019 19:19:51 +0200 Subject: add NDMA start mode 0x0A (AES input FIFO) --- src/DSi_AES.cpp | 22 +++++++++++++++++++--- src/DSi_AES.h | 1 + src/DSi_NDMA.cpp | 8 +++++++- 3 files changed, 27 insertions(+), 4 deletions(-) (limited to 'src/DSi_NDMA.cpp') diff --git a/src/DSi_AES.cpp b/src/DSi_AES.cpp index 1ba690f..b427dcd 100644 --- a/src/DSi_AES.cpp +++ b/src/DSi_AES.cpp @@ -191,6 +191,8 @@ void WriteCnt(u32 val) { // transfer start (checkme) RemBlocks = BlkCnt >> 16; + + DSi::CheckNDMAs(1, 0x2A); } printf("AES CNT: %08X / mode=%d inDMA=%d outDMA=%d blocks=%d\n", @@ -204,7 +206,8 @@ void WriteBlkCnt(u32 val) u32 ReadOutputFIFO() { - return OutputFIFO->Read(); + u32 ret = OutputFIFO->Read(); + return ret; } void WriteInputFIFO(u32 val) @@ -234,17 +237,30 @@ void WriteInputFIFO(u32 val) if (OutputFIFO->Level() >= OutputDMASize) { - // trigger DMA + // trigger output DMA DSi::CheckNDMAs(1, 0x2B); } - // TODO: DMA the other way around if (RemBlocks == 0) { Cnt &= ~(1<<31); if (Cnt & (1<<30)) NDS::SetIRQ2(NDS::IRQ2_DSi_AES); + DSi::StopNDMAs(1, 0x2A); DSi::StopNDMAs(1, 0x2B); } + else + { + CheckInputDMA(); + } +} + +void CheckInputDMA() +{ + if (InputFIFO->Level() < InputDMASize) + { + // trigger input DMA + DSi::CheckNDMAs(1, 0x2A); + } } diff --git a/src/DSi_AES.h b/src/DSi_AES.h index 7c388f5..77a4400 100644 --- a/src/DSi_AES.h +++ b/src/DSi_AES.h @@ -36,6 +36,7 @@ void WriteBlkCnt(u32 val); u32 ReadOutputFIFO(); void WriteInputFIFO(u32 val); +void CheckInputDMA(); void WriteIV(u32 offset, u32 val, u32 mask); void WriteMAC(u32 offset, u32 val, u32 mask); diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index aed78af..cd84901 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -21,6 +21,7 @@ #include "DSi.h" #include "DSi_NDMA.h" #include "GPU.h" +#include "DSi_AES.h" @@ -100,7 +101,7 @@ void DSi_NDMA::WriteCnt(u32 val) Start(); if (StartMode != 0x10 && StartMode != 0x30 && - StartMode != 0x2B) + StartMode != 0x2A && StartMode != 0x2B) printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X\n", CPU?7:9, Num, StartMode, SrcAddr, DstAddr); } } @@ -290,6 +291,7 @@ void DSi_NDMA::Run7() CurDstAddr += DstAddrInc<<2; IterCount--; RemCount--; + TotalRemCount--; if (NDS::ARM7Timestamp >= NDS::ARM7Target) break; } @@ -303,6 +305,8 @@ void DSi_NDMA::Run7() { Running = 0; NDS::ResumeCPU(1, 1<<(Num+4)); + + DSi_AES::CheckInputDMA(); } return; @@ -325,4 +329,6 @@ void DSi_NDMA::Run7() Running = 0; InProgress = false; NDS::ResumeCPU(1, 1<<(Num+4)); + + DSi_AES::CheckInputDMA(); } -- cgit v1.2.3 From 3807c9bf5b19bbea6eb10c12734a17e0c55b4f51 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Wed, 19 Jun 2019 21:57:08 +0200 Subject: combat AES overflowing and/or getting stuck --- src/DSi_AES.cpp | 59 +++++++++++++++++++++++++++++++++++--------------------- src/DSi_AES.h | 2 ++ src/DSi_NDMA.cpp | 4 +++- 3 files changed, 42 insertions(+), 23 deletions(-) (limited to 'src/DSi_NDMA.cpp') diff --git a/src/DSi_AES.cpp b/src/DSi_AES.cpp index b427dcd..9f48519 100644 --- a/src/DSi_AES.cpp +++ b/src/DSi_AES.cpp @@ -207,6 +207,9 @@ void WriteBlkCnt(u32 val) u32 ReadOutputFIFO() { u32 ret = OutputFIFO->Read(); + + CheckInputDMA(); + CheckOutputDMA(); return ret; } @@ -218,28 +221,7 @@ void WriteInputFIFO(u32 val) if (!(Cnt & (1<<31))) return; - while (InputFIFO->Level() >= 4 && RemBlocks > 0) - { - switch (AESMode) - { - case 2: - case 3: ProcessBlock_CTR(); break; - default: - // dorp - OutputFIFO->Write(InputFIFO->Read()); - OutputFIFO->Write(InputFIFO->Read()); - OutputFIFO->Write(InputFIFO->Read()); - OutputFIFO->Write(InputFIFO->Read()); - } - - RemBlocks--; - } - - if (OutputFIFO->Level() >= OutputDMASize) - { - // trigger output DMA - DSi::CheckNDMAs(1, 0x2B); - } + Update(); if (RemBlocks == 0) { @@ -261,6 +243,39 @@ void CheckInputDMA() // trigger input DMA DSi::CheckNDMAs(1, 0x2A); } + + Update(); +} + +void CheckOutputDMA() +{ + if (OutputFIFO->Level() >= OutputDMASize) + { + // trigger output DMA + DSi::CheckNDMAs(1, 0x2B); + } +} + +void Update() +{ + while (InputFIFO->Level() >= 4 && OutputFIFO->Level() <= 12 && RemBlocks > 0) + { + switch (AESMode) + { + case 2: + case 3: ProcessBlock_CTR(); break; + default: + // dorp + OutputFIFO->Write(InputFIFO->Read()); + OutputFIFO->Write(InputFIFO->Read()); + OutputFIFO->Write(InputFIFO->Read()); + OutputFIFO->Write(InputFIFO->Read()); + } + + RemBlocks--; + } + + CheckOutputDMA(); } diff --git a/src/DSi_AES.h b/src/DSi_AES.h index 77a4400..5e726cd 100644 --- a/src/DSi_AES.h +++ b/src/DSi_AES.h @@ -37,6 +37,8 @@ void WriteBlkCnt(u32 val); u32 ReadOutputFIFO(); void WriteInputFIFO(u32 val); void CheckInputDMA(); +void CheckOutputDMA(); +void Update(); void WriteIV(u32 offset, u32 val, u32 mask); void WriteMAC(u32 offset, u32 val, u32 mask); diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index cd84901..a62904a 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -129,7 +129,7 @@ void DSi_NDMA::Start() if (Cnt & (1<<12)) CurDstAddr = DstAddr; if (Cnt & (1<<15)) CurSrcAddr = SrcAddr; - printf("ARM%d NDMA%d %08X %02X %08X->%08X %d bytes, total=%d\n", CPU?7:9, Num, Cnt, StartMode, CurSrcAddr, CurDstAddr, RemCount*4, TotalRemCount*4); + //printf("ARM%d NDMA%d %08X %02X %08X->%08X %d bytes, total=%d\n", CPU?7:9, Num, Cnt, StartMode, CurSrcAddr, CurDstAddr, RemCount*4, TotalRemCount*4); //IsGXFIFODMA = (CPU == 0 && (CurSrcAddr>>24) == 0x02 && CurDstAddr == 0x04000400 && DstAddrInc == 0); @@ -307,6 +307,7 @@ void DSi_NDMA::Run7() NDS::ResumeCPU(1, 1<<(Num+4)); DSi_AES::CheckInputDMA(); + DSi_AES::CheckOutputDMA(); } return; @@ -331,4 +332,5 @@ void DSi_NDMA::Run7() NDS::ResumeCPU(1, 1<<(Num+4)); DSi_AES::CheckInputDMA(); + DSi_AES::CheckOutputDMA(); } -- cgit v1.2.3 From d943a51b9658e1898f49b6773f85778ae7348400 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Thu, 20 Jun 2019 03:19:51 +0200 Subject: ayyy getting there! --- src/DSi.cpp | 2 +- src/DSi_I2C.cpp | 9 ++++----- src/DSi_NDMA.cpp | 4 ++-- src/DSi_SD.cpp | 5 ++++- src/NDS.cpp | 4 ++-- 5 files changed, 13 insertions(+), 11 deletions(-) (limited to 'src/DSi_NDMA.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index ee9d21c..0e35d53 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -1239,7 +1239,7 @@ u8 ARM7IORead8(u32 addr) CASE_READ8_32BIT(0x04004060, MBK[1][8]) case 0x04004500: return DSi_I2C::ReadData(); - case 0x04004501: printf("read I2C CNT %02X\n", DSi_I2C::Cnt); return DSi_I2C::Cnt; + case 0x04004501: return DSi_I2C::Cnt; case 0x04004D00: return ConsoleID & 0xFF; case 0x04004D01: return (ConsoleID >> 8) & 0xFF; diff --git a/src/DSi_I2C.cpp b/src/DSi_I2C.cpp index 8b01b0e..845dd9d 100644 --- a/src/DSi_I2C.cpp +++ b/src/DSi_I2C.cpp @@ -152,7 +152,7 @@ void Reset() void WriteCnt(u8 val) { - printf("I2C: write CNT %02X\n", val); + //printf("I2C: write CNT %02X\n", val); // TODO: check ACK flag // TODO: transfer delay @@ -174,7 +174,7 @@ void WriteCnt(u8 val) default: Data = 0; break; } - printf("I2C read, device=%02X, cnt=%02X, data=%02X, last=%d\n", Device, val, Data, islast); + //printf("I2C read, device=%02X, cnt=%02X, data=%02X, last=%d\n", Device, val, Data, islast); } else { @@ -184,7 +184,7 @@ void WriteCnt(u8 val) if (val & (1<<1)) { Device = Data & 0xFE; - printf("I2C: %s start, device=%02X\n", (Data&0x01)?"read":"write", Device); + //printf("I2C: %s start, device=%02X\n", (Data&0x01)?"read":"write", Device); switch (Device) { @@ -193,7 +193,7 @@ void WriteCnt(u8 val) } else { - printf("I2C write, device=%02X, cnt=%02X, data=%02X, last=%d\n", Device, val, Data, islast); + //printf("I2C write, device=%02X, cnt=%02X, data=%02X, last=%d\n", Device, val, Data, islast); switch (Device) { @@ -212,7 +212,6 @@ void WriteCnt(u8 val) u8 ReadData() { - printf("I2C: read the data: %02X\n", Data); return Data; } diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index a62904a..37eb687 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -135,8 +135,8 @@ void DSi_NDMA::Start() // TODO eventually: not stop if we're running code in ITCM - if (SubblockTimer & 0xFFFF) - printf("TODO! NDMA SUBBLOCK TIMER: %08X\n", SubblockTimer); + //if (SubblockTimer & 0xFFFF) + // printf("TODO! NDMA SUBBLOCK TIMER: %08X\n", SubblockTimer); if (NDS::DMAsRunning(CPU)) Running = 1; diff --git a/src/DSi_SD.cpp b/src/DSi_SD.cpp index fbb2e14..3764a3c 100644 --- a/src/DSi_SD.cpp +++ b/src/DSi_SD.cpp @@ -218,6 +218,8 @@ u16 DSi_SDHost::Read(u32 addr) case 0x026: return BlockLen16; case 0x028: return SDOption; + case 0x02C: return 0; // TODO + case 0x030: // FIFO16 { // TODO: decrement BlockLen???? @@ -275,7 +277,7 @@ u16 DSi_SDHost::Read(u32 addr) case 0x108: return BlockCount32; } - printf("unknown %s read %08X\n", SD_DESC, addr); + printf("unknown %s read %08X @ %08X\n", SD_DESC, addr, NDS::GetPC(1)); return 0; } @@ -356,6 +358,7 @@ void DSi_SDHost::Write(u32 addr, u16 val) break; } } + else printf("%s: SENDING CMD %04X TO NULL DEVICE\n", SD_DESC, val); } return; diff --git a/src/NDS.cpp b/src/NDS.cpp index 6622373..61cf547 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -1600,7 +1600,7 @@ void debug(u32 param) fwrite(&val, 4, 1, shit); } fclose(shit);*/ - FILE* + /*FILE* shit = fopen("debug/dump9.bin", "wb"); for (u32 i = 0x02000000; i < 0x04000000; i+=4) { @@ -1614,7 +1614,7 @@ void debug(u32 param) u32 val = DSi::ARM7Read32(i); fwrite(&val, 4, 1, shit); } - fclose(shit); + fclose(shit);*/ } -- cgit v1.2.3 From 851e255b4099904b4784fa7e1c672f03e5ca531b Mon Sep 17 00:00:00 2001 From: Arisotura Date: Tue, 2 Jul 2019 23:46:39 +0200 Subject: * AES-CCM decrypt * fix a bunch of bugs --- src/DSi.cpp | 36 +++++++++++++-- src/DSi_AES.cpp | 134 +++++++++++++++++++++++++++++++++++++++++++++++++------ src/DSi_NDMA.cpp | 3 ++ src/DSi_SD.cpp | 23 +++++++--- src/DSi_SD.h | 1 + src/SPU.cpp | 7 ++- 6 files changed, 180 insertions(+), 24 deletions(-) (limited to 'src/DSi_NDMA.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index 8f35d91..e601da9 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -44,6 +44,8 @@ namespace DSi u32 BootAddr[2]; +u16 SCFG_Clock9; +u16 SCFG_Clock7; u32 SCFG_MC; u32 MBK[2][9]; @@ -123,11 +125,19 @@ void Reset() SDMMC->Reset(); SDIO->Reset(); + SCFG_Clock9 = 0x0187; // CHECKME + SCFG_Clock7 = 0x0187; SCFG_MC = 0x0011; // LCD init flag GPU::DispStat[0] |= (1<<6); GPU::DispStat[1] |= (1<<6); + + NDS::MapSharedWRAM(3); + + // TEST + u8 derp[16] = {0xE5, 0xCC, 0x5A, 0x8B, 0x56, 0xD0, 0xC9, 0x72, 0x9C, 0x17, 0xE8, 0xDC, 0x39, 0x12, 0x36, 0xA9}; + for (int i = 0; i < 16; i+=4) ARM7Write32(0x03FFC580+i, *(u32*)&derp[i]); } bool LoadBIOS() @@ -1007,7 +1017,7 @@ u16 ARM9IORead16(u32 addr) { switch (addr) { - case 0x04004004: return 0; // TODO + case 0x04004004: return SCFG_Clock9; case 0x04004010: return SCFG_MC & 0xFFFF; CASE_READ16_32BIT(0x04004040, MBK[0][0]) @@ -1079,6 +1089,16 @@ void ARM9IOWrite8(u32 addr, u8 val) { switch (addr) { + case 0x04000301: + // TODO: OPTIONAL PERFORMANCE HACK + // the DSi ARM9 BIOS has a bug where the IRQ wait function attempts to use (ARM7-only) HALTCNT + // effectively causing it to wait in a busy loop. + // for better DSi performance, we can implement an actual IRQ wait here. + // in practice this would only matter when running DS software in DSi mode (ie already a hack). + // DSi software does not use the BIOS IRQ wait function. + //if (val == 0x80 && NDS::ARM9->R[15] == 0xFFFF0268) NDS::ARM9->Halt(1); + return; + case 0x04004040: MapNWRAM_A(0, val); return; case 0x04004041: MapNWRAM_A(1, val); return; case 0x04004042: MapNWRAM_A(2, val); return; @@ -1108,6 +1128,12 @@ void ARM9IOWrite16(u32 addr, u16 val) { switch (addr) { + case 0x04004004: + // TODO: actually change clock! + printf("CLOCK9=%04X\n", val); + SCFG_Clock9 = val & 0x0187; + return; + case 0x04004040: MapNWRAM_A(0, val & 0xFF); MapNWRAM_A(1, val >> 8); @@ -1267,7 +1293,7 @@ u16 ARM7IORead16(u32 addr) case 0x04000218: return NDS::IE2; case 0x0400021C: return NDS::IF2; - case 0x04004004: return 0x0187; + case 0x04004004: return SCFG_Clock7; case 0x04004006: return 0; // JTAG register case 0x04004010: return SCFG_MC & 0xFFFF; @@ -1390,6 +1416,10 @@ void ARM7IOWrite16(u32 addr, u16 val) case 0x04000218: NDS::IE2 = (val & 0x7FF7); NDS::UpdateIRQ(1); return; case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return; + case 0x04004004: + SCFG_Clock7 = val & 0x0187; + return; + case 0x04004010: val &= 0x800C; if ((val & 0xC) == 0xC) val &= ~0xC; // hax @@ -1482,7 +1512,7 @@ void ARM7IOWrite32(u32 addr, u32 val) { addr -= 0x04004440; int n = 0; - while (addr > 0x30) { addr -= 0x30; n++; } + while (addr >= 0x30) { addr -= 0x30; n++; } switch (addr >> 4) { diff --git a/src/DSi_AES.cpp b/src/DSi_AES.cpp index 7f962fd..8ae9082 100644 --- a/src/DSi_AES.cpp +++ b/src/DSi_AES.cpp @@ -42,11 +42,14 @@ FIFO* OutputFIFO; u8 IV[16]; +u8 MAC[16]; + u8 KeyNormal[4][16]; u8 KeyX[4][16]; u8 KeyY[4][16]; u8 CurKey[16]; +u8 CurMAC[16]; AES_ctx Ctx; @@ -77,6 +80,9 @@ void ROL16(u8* val, u32 n) #define _printhex(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); printf("\n"); } #define _printhex2(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); } +#define _printhexR(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[((size)-1)-z]); printf("\n"); } +#define _printhex2R(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[((size)-1)-z]); } + bool Init() { @@ -111,11 +117,16 @@ void Reset() InputFIFO->Clear(); OutputFIFO->Clear(); + memset(IV, 0, sizeof(IV)); + + memset(MAC, 0, sizeof(MAC)); + memset(KeyNormal, 0, sizeof(KeyNormal)); memset(KeyX, 0, sizeof(KeyX)); memset(KeyY, 0, sizeof(KeyY)); memset(CurKey, 0, sizeof(CurKey)); + memset(CurMAC, 0, sizeof(CurMAC)); // initialize keys, as per GBAtek @@ -123,6 +134,12 @@ void Reset() *(u32*)&KeyX[0][0] = 0x746E694E; *(u32*)&KeyX[0][4] = 0x6F646E65; + // slot 1: 'Tad'/dev.kp + *(u32*)&KeyX[1][0] = 0x4E00004A; + *(u32*)&KeyX[1][4] = 0x4A00004E; + *(u32*)&KeyX[1][8] = (u32)(DSi::ConsoleID >> 32) ^ 0xC80C4B72; + *(u32*)&KeyX[1][12] = (u32)DSi::ConsoleID; + // slot 3: console-unique eMMC crypto *(u32*)&KeyX[3][0] = (u32)DSi::ConsoleID; *(u32*)&KeyX[3][4] = (u32)DSi::ConsoleID ^ 0x24EE6906; @@ -134,6 +151,34 @@ void Reset() } +void ProcessBlock_CCM_Decrypt() +{ + u8 data[16]; + u8 data_rev[16]; + + *(u32*)&data[0] = InputFIFO->Read(); + *(u32*)&data[4] = InputFIFO->Read(); + *(u32*)&data[8] = InputFIFO->Read(); + *(u32*)&data[12] = InputFIFO->Read(); + + //printf("AES-CCM: "); _printhex2(data, 16); + + Swap16(data_rev, data); + AES_CTR_xcrypt_buffer(&Ctx, data_rev, 16); + + for (int i = 0; i < 16; i++) CurMAC[i] ^= data_rev[i]; + AES_ECB_encrypt(&Ctx, CurMAC); + + Swap16(data, data_rev); + + //printf(" -> "); _printhex2(data, 16); + + OutputFIFO->Write(*(u32*)&data[0]); + OutputFIFO->Write(*(u32*)&data[4]); + OutputFIFO->Write(*(u32*)&data[8]); + OutputFIFO->Write(*(u32*)&data[12]); +} + void ProcessBlock_CTR() { u8 data[16]; @@ -186,18 +231,12 @@ void WriteCnt(u32 val) OutputDMASize = dmasize_out[(val >> 14) & 0x3]; AESMode = (val >> 28) & 0x3; - if (AESMode < 2) printf("AES-CCM TODO\n"); + if (AESMode == 1) printf("AES-CCM TODO\n"); if (val & (1<<24)) { u32 slot = (val >> 26) & 0x3; memcpy(CurKey, KeyNormal[slot], 16); - - //printf("AES: key(%d): ", slot); _printhex(CurKey, 16); - - u8 tmp[16]; - Swap16(tmp, CurKey); - AES_init_ctx(&Ctx, tmp); } if (!(oldcnt & (1<<31)) && (val & (1<<31))) @@ -205,11 +244,45 @@ void WriteCnt(u32 val) // transfer start (checkme) RemBlocks = BlkCnt >> 16; + u8 key[16]; + u8 iv[16]; + + Swap16(key, CurKey); + Swap16(iv, IV); + + if (AESMode < 2) + { + if (BlkCnt & 0xFFFF) printf("AES: CCM EXTRA LEN TODO\n"); + + u32 maclen = (val >> 16) & 0x7; + if (maclen < 1) maclen = 1; + + iv[0] = 0x02; + for (int i = 0; i < 12; i++) iv[1+i] = iv[4+i]; + iv[13] = 0x00; + iv[14] = 0x00; + iv[15] = 0x01; + + AES_init_ctx_iv(&Ctx, key, iv); + + iv[0] |= (maclen << 3) | ((BlkCnt & 0xFFFF) ? (1<<6) : 0); + iv[13] = RemBlocks >> 12; + iv[14] = RemBlocks >> 4; + iv[15] = RemBlocks << 4; + + memcpy(CurMAC, iv, 16); + AES_ECB_encrypt(&Ctx, CurMAC); + } + else + { + AES_init_ctx_iv(&Ctx, key, iv); + } + DSi::CheckNDMAs(1, 0x2A); } - printf("AES CNT: %08X / mode=%d inDMA=%d outDMA=%d blocks=%d\n", - val, AESMode, InputDMASize, OutputDMASize, RemBlocks); + printf("AES CNT: %08X / mode=%d key=%d inDMA=%d outDMA=%d blocks=%d\n", + val, AESMode, (val >> 26) & 0x3, InputDMASize, OutputDMASize, RemBlocks); } void WriteBlkCnt(u32 val) @@ -219,6 +292,8 @@ void WriteBlkCnt(u32 val) u32 ReadOutputFIFO() { + if (OutputFIFO->IsEmpty()) printf("!!! AES OUTPUT FIFO EMPTY\n"); + u32 ret = OutputFIFO->Read(); if (Cnt & (1<<31)) @@ -241,6 +316,8 @@ void WriteInputFIFO(u32 val) { // TODO: add some delay to processing + if (InputFIFO->IsFull()) printf("!!! AES INPUT FIFO FULL\n"); + InputFIFO->Write(val); if (!(Cnt & (1<<31))) return; @@ -276,6 +353,7 @@ void Update() { switch (AESMode) { + case 0: ProcessBlock_CCM_Decrypt(); break; case 2: case 3: ProcessBlock_CTR(); break; default: @@ -293,6 +371,28 @@ void Update() if (RemBlocks == 0) { + if (AESMode == 0) + { + Ctx.Iv[13] = 0x00; + Ctx.Iv[14] = 0x00; + Ctx.Iv[15] = 0x00;_printhex(Ctx.Iv, 16); + AES_CTR_xcrypt_buffer(&Ctx, CurMAC, 16); + + //printf("FINAL MAC: "); _printhexR(CurMAC, 16); + //printf("INPUT MAC: "); _printhex(MAC, 16); + + Cnt |= (1<<21); + for (int i = 0; i < 16; i++) + { + if (CurMAC[15-i] != MAC[i]) Cnt &= ~(1<<21); + } + } + else + { + // CHECKME + Cnt &= ~(1<<21); + } + Cnt &= ~(1<<31); if (Cnt & (1<<30)) NDS::SetIRQ2(NDS::IRQ2_DSi_AES); DSi::StopNDMAs(1, 0x2A); @@ -313,15 +413,15 @@ void WriteIV(u32 offset, u32 val, u32 mask) *(u32*)&IV[offset] = (old & ~mask) | (val & mask); //printf("AES: IV: "); _printhex(IV, 16); - - u8 tmp[16]; - Swap16(tmp, IV); - AES_ctx_set_iv(&Ctx, tmp); } void WriteMAC(u32 offset, u32 val, u32 mask) { - // + u32 old = *(u32*)&MAC[offset]; + + *(u32*)&MAC[offset] = (old & ~mask) | (val & mask); + + //printf("AES: MAC: "); _printhex(MAC, 16); } void DeriveNormalKey(u32 slot) @@ -355,6 +455,8 @@ void WriteKeyNormal(u32 slot, u32 offset, u32 val, u32 mask) u32 old = *(u32*)&KeyNormal[slot][offset]; *(u32*)&KeyNormal[slot][offset] = (old & ~mask) | (val & mask); + + //printf("KeyNormal(%d): ", slot); _printhex(KeyNormal[slot], 16); } void WriteKeyX(u32 slot, u32 offset, u32 val, u32 mask) @@ -362,6 +464,8 @@ void WriteKeyX(u32 slot, u32 offset, u32 val, u32 mask) u32 old = *(u32*)&KeyX[slot][offset]; *(u32*)&KeyX[slot][offset] = (old & ~mask) | (val & mask); + + //printf("KeyX(%d): ", slot); _printhex(KeyX[slot], 16); } void WriteKeyY(u32 slot, u32 offset, u32 val, u32 mask) @@ -370,6 +474,8 @@ void WriteKeyY(u32 slot, u32 offset, u32 val, u32 mask) *(u32*)&KeyY[slot][offset] = (old & ~mask) | (val & mask); + //printf("[%08X] KeyY(%d): ", NDS::GetPC(1), slot); _printhex(KeyY[slot], 16); + if (offset >= 0xC) { DeriveNormalKey(slot); diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index 37eb687..e7fc7ab 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -123,7 +123,10 @@ void DSi_NDMA::Start() if (((StartMode & 0x1F) != 0x10) && !(Cnt & (1<<29))) { if (IterCount > TotalRemCount) + { IterCount = TotalRemCount; + RemCount = IterCount; + } } if (Cnt & (1<<12)) CurDstAddr = DstAddr; diff --git a/src/DSi_SD.cpp b/src/DSi_SD.cpp index 7367eea..93431b5 100644 --- a/src/DSi_SD.cpp +++ b/src/DSi_SD.cpp @@ -185,6 +185,17 @@ void DSi_SDHost::SendData(u8* data, u32 len) NDS::ScheduleEvent(NDS::Event_DSi_SDTransfer, false, 512, FinishSend, param); } +void DSi_SDHost::FinishReceive(u32 param) +{ + DSi_SDHost* host = (param & 0x1) ? DSi::SDIO : DSi::SDMMC; + DSi_SDDevice* dev = host->Ports[host->PortSelect & 0x1]; + + host->ClearIRQ(24); + host->SetIRQ(25); + + if (dev) dev->ContinueTransfer(); +} + void DSi_SDHost::ReceiveData(u8* data, u32 len) { printf("%s: data TX, len=%d, blkcnt=%d (%d) blklen=%d, irq=%08X\n", SD_DESC, len, BlockCount16, BlockCountInternal, BlockLen16, IRQMask); @@ -481,10 +492,12 @@ void DSi_SDHost::WriteFIFO32(u32 val) // we completed one block, send it to the SD card - ClearIRQ(24); - SetIRQ(25); + //ClearIRQ(24); + //SetIRQ(25); - if (dev) dev->ContinueTransfer(); + //if (dev) dev->ContinueTransfer(); + // TODO measure the actual delay!! + NDS::ScheduleEvent(NDS::Event_DSi_SDTransfer, false, 2048, FinishReceive, Num); } @@ -622,10 +635,10 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param) Host->SendResponse(CSR, true); WriteBlock(RWAddress); RWAddress += BlockSize; - SetState(0x06); + SetState(0x04); return; - case 55: // ?? + case 55: // appcmd prefix CSR |= (1<<5); Host->SendResponse(CSR, true); return; diff --git a/src/DSi_SD.h b/src/DSi_SD.h index 007a8a8..855dd5e 100644 --- a/src/DSi_SD.h +++ b/src/DSi_SD.h @@ -37,6 +37,7 @@ public: void DoSavestate(Savestate* file); static void FinishSend(u32 param); + static void FinishReceive(u32 param); void SendResponse(u32 val, bool last); void SendData(u8* data, u32 len); void ReceiveData(u8* data, u32 len); diff --git a/src/SPU.cpp b/src/SPU.cpp index ee9237f..d31a371 100644 --- a/src/SPU.cpp +++ b/src/SPU.cpp @@ -19,6 +19,7 @@ #include #include #include "NDS.h" +#include "DSi.h" #include "SPU.h" @@ -216,7 +217,8 @@ void Channel::FIFO_BufferData() for (u32 i = 0; i < burstlen; i += 4) { - FIFO[FIFOWritePos] = NDS::ARM7Read32(SrcAddr + FIFOReadOffset); + //FIFO[FIFOWritePos] = NDS::ARM7Read32(SrcAddr + FIFOReadOffset); + FIFO[FIFOWritePos] = DSi::ARM7Read32(SrcAddr + FIFOReadOffset); FIFOReadOffset += 4; FIFOWritePos++; FIFOWritePos &= 0x7; @@ -499,7 +501,8 @@ void CaptureUnit::FIFO_FlushData() { for (u32 i = 0; i < 4; i++) { - NDS::ARM7Write32(DstAddr + FIFOWriteOffset, FIFO[FIFOReadPos]); + //NDS::ARM7Write32(DstAddr + FIFOWriteOffset, FIFO[FIFOReadPos]); + DSi::ARM7Write32(DstAddr + FIFOWriteOffset, FIFO[FIFOReadPos]); FIFOReadPos++; FIFOReadPos &= 0x3; -- cgit v1.2.3 From e82364f010f6ad4e4883c241a05a4aac10cd75d6 Mon Sep 17 00:00:00 2001 From: Arisotura Date: Sat, 19 Oct 2019 16:03:59 +0200 Subject: * some fixes to SD controller support, make it clear that there is no SD inserted, makes Flipnote work somewhat better * immediately clear AES busy flag when the block count is zero (occurs when loading DSi cart games) * implement NDMA start modes that have an old-DMA equivalent (except for GXFIFO mode) now it boots DSi carts! --- src/DSi.cpp | 16 +++++++++- src/DSi.h | 1 + src/DSi_AES.cpp | 90 +++++++++++++++++++++++++------------------------------- src/DSi_NDMA.cpp | 6 ++-- src/DSi_SD.cpp | 62 +++++++++++++++++++++++++++++++++----- src/NDS.cpp | 42 ++++++++++++++++++++++++++ src/NDSCart.cpp | 4 +-- 7 files changed, 159 insertions(+), 62 deletions(-) (limited to 'src/DSi_NDMA.cpp') diff --git a/src/DSi.cpp b/src/DSi.cpp index 9f07fa1..ef4e6da 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -411,6 +411,16 @@ void StallNDMAs() // TODO } +bool NDMAsInMode(u32 cpu, u32 mode) +{ + cpu <<= 2; + if (NDMAs[cpu+0]->IsInMode(mode)) return true; + if (NDMAs[cpu+1]->IsInMode(mode)) return true; + if (NDMAs[cpu+2]->IsInMode(mode)) return true; + if (NDMAs[cpu+3]->IsInMode(mode)) return true; + return false; +} + bool NDMAsRunning(u32 cpu) { cpu <<= 2; @@ -1156,7 +1166,7 @@ u8 ARM9IORead8(u32 addr) return NDS::ARM9IORead8(addr); } - +//u16 dicks = 0; u16 ARM9IORead16(u32 addr) { switch (addr) @@ -1174,6 +1184,8 @@ u16 ARM9IORead16(u32 addr) CASE_READ16_32BIT(0x04004058, MBK[0][6]) CASE_READ16_32BIT(0x0400405C, MBK[0][7]) CASE_READ16_32BIT(0x04004060, MBK[0][8]) + + //case 0x04004202: return dicks & 0xEF1F; } return NDS::ARM9IORead16(addr); @@ -1318,6 +1330,8 @@ void ARM9IOWrite16(u32 addr, u16 val) MapNWRAM_C(6, val & 0xFF); MapNWRAM_C(7, val >> 8); return; + + //case 0x04004202: dicks = val & 0xEF3F; return; } return NDS::ARM9IOWrite16(addr, val); diff --git a/src/DSi.h b/src/DSi.h index bd37550..5697237 100644 --- a/src/DSi.h +++ b/src/DSi.h @@ -47,6 +47,7 @@ bool LoadNAND(); void RunNDMAs(u32 cpu); void StallNDMAs(); +bool NDMAsInMode(u32 cpu, u32 mode); bool NDMAsRunning(u32 cpu); void CheckNDMAs(u32 cpu, u32 mode); void StopNDMAs(u32 cpu, u32 mode); diff --git a/src/DSi_AES.cpp b/src/DSi_AES.cpp index e49ebf5..7aae8f3 100644 --- a/src/DSi_AES.cpp +++ b/src/DSi_AES.cpp @@ -129,28 +129,8 @@ void Reset() memset(CurKey, 0, sizeof(CurKey)); memset(CurMAC, 0, sizeof(CurMAC)); - // initialize keys, as per GBAtek - -#if 0 - // slot 0: modcrypt - *(u32*)&KeyX[0][0] = 0x746E694E; - *(u32*)&KeyX[0][4] = 0x6F646E65; - - // slot 1: 'Tad'/dev.kp - *(u32*)&KeyX[1][0] = 0x4E00004A; - *(u32*)&KeyX[1][4] = 0x4A00004E; - *(u32*)&KeyX[1][8] = (u32)(DSi::ConsoleID >> 32) ^ 0xC80C4B72; - *(u32*)&KeyX[1][12] = (u32)DSi::ConsoleID; - - // slot 3: console-unique eMMC crypto - *(u32*)&KeyX[3][0] = (u32)DSi::ConsoleID; - *(u32*)&KeyX[3][4] = (u32)DSi::ConsoleID ^ 0x24EE6906; - *(u32*)&KeyX[3][8] = (u32)(DSi::ConsoleID >> 32) ^ 0xE65B601D; - *(u32*)&KeyX[3][12] = (u32)(DSi::ConsoleID >> 32); - *(u32*)&KeyY[3][0] = 0x0AB9DC76; - *(u32*)&KeyY[3][4] = 0xBD4DC4D3; - *(u32*)&KeyY[3][8] = 0x202DDD1D; -#endif + // initialize keys + FILE* f = Platform::OpenLocalFile("aeskeys.bin", "rb"); if (f) { @@ -233,12 +213,12 @@ u32 ReadCnt() ret |= InputFIFO->Level(); ret |= (OutputFIFO->Level() << 5); - +//printf("READ AES CNT: %08X, LEVELS: IN=%d OUT=%d\n", ret, InputFIFO->Level(), OutputFIFO->Level()); return ret; } void WriteCnt(u32 val) -{ +{printf("AES CNT = %08X\n", val); u32 oldcnt = Cnt; Cnt = val & 0xFC1FF000; @@ -267,41 +247,51 @@ void WriteCnt(u32 val) // transfer start (checkme) RemBlocks = BlkCnt >> 16; - u8 key[16]; - u8 iv[16]; + if (RemBlocks > 0) + { + u8 key[16]; + u8 iv[16]; - Swap16(key, CurKey); - Swap16(iv, IV); + Swap16(key, CurKey); + Swap16(iv, IV); - if (AESMode < 2) - { - if (BlkCnt & 0xFFFF) printf("AES: CCM EXTRA LEN TODO\n"); + if (AESMode < 2) + { + if (BlkCnt & 0xFFFF) printf("AES: CCM EXTRA LEN TODO\n"); - u32 maclen = (val >> 16) & 0x7; - if (maclen < 1) maclen = 1; + u32 maclen = (val >> 16) & 0x7; + if (maclen < 1) maclen = 1; - iv[0] = 0x02; - for (int i = 0; i < 12; i++) iv[1+i] = iv[4+i]; - iv[13] = 0x00; - iv[14] = 0x00; - iv[15] = 0x01; + iv[0] = 0x02; + for (int i = 0; i < 12; i++) iv[1+i] = iv[4+i]; + iv[13] = 0x00; + iv[14] = 0x00; + iv[15] = 0x01; - AES_init_ctx_iv(&Ctx, key, iv); + AES_init_ctx_iv(&Ctx, key, iv); - iv[0] |= (maclen << 3) | ((BlkCnt & 0xFFFF) ? (1<<6) : 0); - iv[13] = RemBlocks >> 12; - iv[14] = RemBlocks >> 4; - iv[15] = RemBlocks << 4; + iv[0] |= (maclen << 3) | ((BlkCnt & 0xFFFF) ? (1<<6) : 0); + iv[13] = RemBlocks >> 12; + iv[14] = RemBlocks >> 4; + iv[15] = RemBlocks << 4; - memcpy(CurMAC, iv, 16); - AES_ECB_encrypt(&Ctx, CurMAC); + memcpy(CurMAC, iv, 16); + AES_ECB_encrypt(&Ctx, CurMAC); + } + else + { + AES_init_ctx_iv(&Ctx, key, iv); + } + + DSi::CheckNDMAs(1, 0x2A); } else { - AES_init_ctx_iv(&Ctx, key, iv); - } + // no blocks to process? oh well. mark it finished + // CHECKME: does this trigger any IRQ or shit? - DSi::CheckNDMAs(1, 0x2A); + Cnt &= ~(1<<31); + } } printf("AES CNT: %08X / mode=%d key=%d inDMA=%d outDMA=%d blocks=%d\n", @@ -309,7 +299,7 @@ void WriteCnt(u32 val) } void WriteBlkCnt(u32 val) -{ +{printf("AES BLOCK CNT %08X / %d\n", val, val>>16); BlkCnt = val; } @@ -415,7 +405,7 @@ void Update() // CHECKME Cnt &= ~(1<<21); } - +printf("AES: FINISHED\n"); Cnt &= ~(1<<31); if (Cnt & (1<<30)) NDS::SetIRQ2(NDS::IRQ2_DSi_AES); DSi::StopNDMAs(1, 0x2A); diff --git a/src/DSi_NDMA.cpp b/src/DSi_NDMA.cpp index e7fc7ab..19c72b6 100644 --- a/src/DSi_NDMA.cpp +++ b/src/DSi_NDMA.cpp @@ -101,8 +101,10 @@ void DSi_NDMA::WriteCnt(u32 val) Start(); if (StartMode != 0x10 && StartMode != 0x30 && - StartMode != 0x2A && StartMode != 0x2B) - printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X\n", CPU?7:9, Num, StartMode, SrcAddr, DstAddr); + StartMode != 0x04 && StartMode != 0x06 && StartMode != 0x07 && StartMode != 0x08 && StartMode != 0x09 && + StartMode != 0x24 && StartMode != 0x26 && StartMode != 0x28 && StartMode != 0x29 && StartMode != 0x2A && StartMode != 0x2B) + printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X LEN=%d BLK=%d CNT=%08X\n", + CPU?7:9, Num, StartMode, SrcAddr, DstAddr, TotalLength, BlockLength, Cnt); } } diff --git a/src/DSi_SD.cpp b/src/DSi_SD.cpp index 796466d..a45a8ce 100644 --- a/src/DSi_SD.cpp +++ b/src/DSi_SD.cpp @@ -91,10 +91,16 @@ void DSi_SDHost::Reset() if (Num == 0) { + // TODO: eventually pull from host filesystem + /*DSi_MMCStorage* sd = new DSi_MMCStorage(this, false, "sd.bin"); + u8 sd_cid[16] = {0xBD, 0x12, 0x34, 0x56, 0x78, 0x03, 0x4D, 0x30, 0x30, 0x46, 0x50, 0x41, 0x00, 0x00, 0x15, 0x00}; + sd->SetCID(sd_cid);*/ + DSi_MMCStorage* sd = NULL; + DSi_MMCStorage* mmc = new DSi_MMCStorage(this, true, "nand.bin"); mmc->SetCID(DSi::eMMC_CID); - // TODO: port 0 (SD) + Ports[0] = sd; Ports[1] = mmc; } else @@ -196,6 +202,14 @@ void DSi_SDHost::FinishSend(u32 param) host->ClearIRQ(25); host->SetIRQ(24); //if (param & 0x2) host->SetIRQ(2); + + // TODO: this is an assumption and should eventually be confirmed + // Flipnote sets DMA blocklen to 128 words and totallen to 1024 words + // so, presumably, DMA should trigger when the FIFO is full + // 'full' being when it reaches whatever BlockLen16 is set to, or the + // other blocklen register, or when it is actually full (but that makes + // less sense) + DSi::CheckNDMAs(1, host->Num ? 0x29 : 0x28); } u32 DSi_SDHost::SendData(u8* data, u32 len) @@ -286,7 +300,7 @@ u32 DSi_SDHost::GetTransferrableLen(u32 len) u16 DSi_SDHost::Read(u32 addr) { - //if(Num)printf("SDIO READ %08X %08X\n", addr, NDS::GetPC(1)); + if(!Num)printf("SDMMC READ %08X %08X\n", addr, NDS::GetPC(1)); switch (addr & 0x1FF) { @@ -307,7 +321,24 @@ u16 DSi_SDHost::Read(u32 addr) case 0x018: return ResponseBuffer[6]; case 0x01A: return ResponseBuffer[7]; - case 0x01C: return (IRQStatus & 0x031D) | 0x0030; // TODO: adjust insert flags for SD card + case 0x01C: + { + u16 ret = (IRQStatus & 0x031D); + + if (!Num) + { + if (Ports[0]) // basic check of whether the SD card is inserted + ret |= 0x0030; + else + ret |= 0x0008; + } + else + { + // SDIO wifi is always inserted, I guess + ret |= 0x0030; + } + return ret; + } case 0x01E: return ((IRQStatus >> 16) & 0x8B7F); case 0x020: return IRQMask & 0x031D; case 0x022: return (IRQMask >> 16) & 0x8B7F; @@ -436,7 +467,7 @@ u32 DSi_SDHost::ReadFIFO32() void DSi_SDHost::Write(u32 addr, u16 val) { - //if(Num)printf("SDIO WRITE %08X %04X %08X\n", addr, val, NDS::GetPC(1)); + if(!Num)printf("SDMMC WRITE %08X %04X %08X\n", addr, val, NDS::GetPC(1)); switch (addr & 0x1FF) { @@ -464,7 +495,7 @@ void DSi_SDHost::Write(u32 addr, u16 val) } return; - case 0x002: PortSelect = val; printf("%s: PORT SELECT %04X\n", SD_DESC, val); return; + case 0x002: PortSelect = (val & 0x040F) | (PortSelect & 0x0300); printf("%s: PORT SELECT %04X (%04X)\n", SD_DESC, val, PortSelect); return; case 0x004: Param = (Param & 0xFFFF0000) | val; return; case 0x006: Param = (Param & 0x0000FFFF) | (val << 16); return; @@ -504,7 +535,7 @@ void DSi_SDHost::Write(u32 addr, u16 val) if (DataFIFO[f]->IsFull()) { // TODO - printf("!!!! %s FIFO FULL\n", SD_DESC); + printf("!!!! %s FIFO (16) FULL\n", SD_DESC); return; } @@ -582,12 +613,14 @@ void DSi_SDHost::WriteFIFO32(u32 val) { if (DataMode != 1) return; + printf("%s: WRITE FIFO32: LEVEL=%d/%d\n", SD_DESC, DataFIFO[CurFIFO]->Level(), (BlockLen16>>1)); + DSi_SDDevice* dev = Ports[PortSelect & 0x1]; u32 f = CurFIFO; if (DataFIFO[f]->IsFull()) { // TODO - printf("!!!! %s FIFO FULL\n", SD_DESC); + printf("!!!! %s FIFO (32) FULL\n", SD_DESC); return; } @@ -608,12 +641,26 @@ void DSi_SDHost::WriteFIFO32(u32 val) } +#define MMC_DESC (Internal?"NAND":"SDcard") + DSi_MMCStorage::DSi_MMCStorage(DSi_SDHost* host, bool internal, const char* path) : DSi_SDDevice(host) { Internal = internal; strncpy(FilePath, path, 1023); FilePath[1023] = '\0'; File = Platform::OpenLocalFile(path, "r+b"); + if (!File) + { + if (internal) + { + // TODO: proper failure + printf("!! MMC file %s does not exist\n", path); + } + else + { + File = Platform::OpenLocalFile(path, "w+b"); + } + } CSR = 0x00000100; // checkme @@ -674,6 +721,7 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param) { // TODO printf("CMD3 on SD card: TODO\n"); + Host->SendResponse((CSR & 0x1FFF) | ((CSR >> 6) & 0x2000) | ((CSR >> 8) & 0xC000) | (1 << 16), true); } return; diff --git a/src/NDS.cpp b/src/NDS.cpp index 95265cf..6933e95 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -1371,6 +1371,29 @@ void RunTimers(u32 cpu) +// matching NDMA modes for DSi +const u32 NDMAModes[] = +{ + // ARM9 + + 0x10, // immediate + 0x06, // VBlank + 0x07, // HBlank + 0x08, // scanline start + 0x09, // mainmem FIFO + 0x04, // DS cart slot + 0xFF, // GBA cart slot + 0x0A, // GX FIFO + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + + // ARM7 + + 0x30, // immediate + 0x26, // VBlank + 0x24, // DS cart slot + 0xFF, // wifi / GBA cart slot (TODO) +}; + bool DMAsInMode(u32 cpu, u32 mode) { cpu <<= 2; @@ -1378,6 +1401,13 @@ bool DMAsInMode(u32 cpu, u32 mode) if (DMAs[cpu+1]->IsInMode(mode)) return true; if (DMAs[cpu+2]->IsInMode(mode)) return true; if (DMAs[cpu+3]->IsInMode(mode)) return true; + + if (true) + { + cpu >>= 2; + return DSi::NDMAsInMode(cpu, NDMAModes[mode]); + } + return false; } @@ -1399,6 +1429,12 @@ void CheckDMAs(u32 cpu, u32 mode) DMAs[cpu+1]->StartIfNeeded(mode); DMAs[cpu+2]->StartIfNeeded(mode); DMAs[cpu+3]->StartIfNeeded(mode); + + if (true) + { + cpu >>= 2; + DSi::CheckNDMAs(cpu, NDMAModes[mode]); + } } void StopDMAs(u32 cpu, u32 mode) @@ -1408,6 +1444,12 @@ void StopDMAs(u32 cpu, u32 mode) DMAs[cpu+1]->StopIfNeeded(mode); DMAs[cpu+2]->StopIfNeeded(mode); DMAs[cpu+3]->StopIfNeeded(mode); + + if (true) + { + cpu >>= 2; + DSi::StopNDMAs(cpu, NDMAModes[mode]); + } } diff --git a/src/NDSCart.cpp b/src/NDSCart.cpp index 65cf8ae..b0e9837 100644 --- a/src/NDSCart.cpp +++ b/src/NDSCart.cpp @@ -1227,11 +1227,11 @@ void WriteROMCnt(u32 val) *(u32*)&cmd[4] = *(u32*)&ROMCommand[4]; } - printf("ROM COMMAND %04X %08X %02X%02X%02X%02X%02X%02X%02X%02X SIZE %04X\n", + /*printf("ROM COMMAND %04X %08X %02X%02X%02X%02X%02X%02X%02X%02X SIZE %04X\n", SPICnt, ROMCnt, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], cmd[5], cmd[6], cmd[7], - datasize); + datasize);*/ switch (cmd[0]) { -- cgit v1.2.3