From 298b958e2a105ba29f07ee110cd9f856da1f66d7 Mon Sep 17 00:00:00 2001
From: webgeek1234 <webgeek1234@gmail.com>
Date: Tue, 1 Dec 2020 12:48:46 -0600
Subject: Rename jit linkage asm files (#836)

An extension of lower case s indicates to not run the
preprocessor while upper case S does. These files have defines.
---
 src/ARMJIT_x64/ARMJIT_Linkage.S | 88 +++++++++++++++++++++++++++++++++++++++++
 src/ARMJIT_x64/ARMJIT_Linkage.s | 88 -----------------------------------------
 2 files changed, 88 insertions(+), 88 deletions(-)
 create mode 100644 src/ARMJIT_x64/ARMJIT_Linkage.S
 delete mode 100644 src/ARMJIT_x64/ARMJIT_Linkage.s

(limited to 'src/ARMJIT_x64')

diff --git a/src/ARMJIT_x64/ARMJIT_Linkage.S b/src/ARMJIT_x64/ARMJIT_Linkage.S
new file mode 100644
index 0000000..8cc0b5f
--- /dev/null
+++ b/src/ARMJIT_x64/ARMJIT_Linkage.S
@@ -0,0 +1,88 @@
+.intel_syntax noprefix
+
+#include "ARMJIT_Offsets.h"
+
+.text
+
+#define RCPU rbp
+#define RCPSR r15d
+
+#ifdef WIN64
+#define ARG1_REG ecx
+#define ARG2_REG edx
+#define ARG3_REG r8d
+#define ARG4_REG r9d
+#define ARG1_REG64 rcx
+#define ARG2_REG64 rdx
+#define ARG3_REG64 r8
+#define ARG4_REG64 r9
+#else
+#define ARG1_REG edi
+#define ARG2_REG esi
+#define ARG3_REG edx
+#define ARG4_REG ecx
+#define ARG1_REG64 rdi
+#define ARG2_REG64 rsi
+#define ARG3_REG64 rdx
+#define ARG4_REG64 rcx
+#endif
+
+.p2align 4,,15
+
+#ifdef __APPLE__
+.global _ARM_Dispatch
+_ARM_Dispatch:
+#else
+.global ARM_Dispatch
+ARM_Dispatch:
+#endif
+#ifdef WIN64
+    push rdi
+    push rsi
+#endif
+    push rbx
+    push r12
+    push r13
+    push r14
+    push r15
+    push rbp
+
+#ifdef WIN64
+    sub rsp, 0x28
+#else
+    sub rsp, 0x8
+#endif
+    mov RCPU, ARG1_REG64
+    mov RCPSR, [RCPU + ARM_CPSR_offset]
+
+    jmp ARG2_REG64
+
+.p2align 4,,15
+
+#ifdef __APPLE__
+.global _ARM_Ret
+_ARM_Ret:
+#else
+.global ARM_Ret
+ARM_Ret:
+#endif
+    mov [RCPU + ARM_CPSR_offset], RCPSR
+
+#ifdef WIN64
+    add rsp, 0x28
+#else
+    add rsp, 0x8
+#endif
+
+    pop rbp
+    pop r15
+    pop r14
+    pop r13
+    pop r12
+    pop rbx
+#ifdef WIN64
+    pop rsi
+    pop rdi
+#endif
+
+    ret
diff --git a/src/ARMJIT_x64/ARMJIT_Linkage.s b/src/ARMJIT_x64/ARMJIT_Linkage.s
deleted file mode 100644
index 8cc0b5f..0000000
--- a/src/ARMJIT_x64/ARMJIT_Linkage.s
+++ /dev/null
@@ -1,88 +0,0 @@
-.intel_syntax noprefix
-
-#include "ARMJIT_Offsets.h"
-
-.text
-
-#define RCPU rbp
-#define RCPSR r15d
-
-#ifdef WIN64
-#define ARG1_REG ecx
-#define ARG2_REG edx
-#define ARG3_REG r8d
-#define ARG4_REG r9d
-#define ARG1_REG64 rcx
-#define ARG2_REG64 rdx
-#define ARG3_REG64 r8
-#define ARG4_REG64 r9
-#else
-#define ARG1_REG edi
-#define ARG2_REG esi
-#define ARG3_REG edx
-#define ARG4_REG ecx
-#define ARG1_REG64 rdi
-#define ARG2_REG64 rsi
-#define ARG3_REG64 rdx
-#define ARG4_REG64 rcx
-#endif
-
-.p2align 4,,15
-
-#ifdef __APPLE__
-.global _ARM_Dispatch
-_ARM_Dispatch:
-#else
-.global ARM_Dispatch
-ARM_Dispatch:
-#endif
-#ifdef WIN64
-    push rdi
-    push rsi
-#endif
-    push rbx
-    push r12
-    push r13
-    push r14
-    push r15
-    push rbp
-
-#ifdef WIN64
-    sub rsp, 0x28
-#else
-    sub rsp, 0x8
-#endif
-    mov RCPU, ARG1_REG64
-    mov RCPSR, [RCPU + ARM_CPSR_offset]
-
-    jmp ARG2_REG64
-
-.p2align 4,,15
-
-#ifdef __APPLE__
-.global _ARM_Ret
-_ARM_Ret:
-#else
-.global ARM_Ret
-ARM_Ret:
-#endif
-    mov [RCPU + ARM_CPSR_offset], RCPSR
-
-#ifdef WIN64
-    add rsp, 0x28
-#else
-    add rsp, 0x8
-#endif
-
-    pop rbp
-    pop r15
-    pop r14
-    pop r13
-    pop r12
-    pop rbx
-#ifdef WIN64
-    pop rsi
-    pop rdi
-#endif
-
-    ret
-- 
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