From 961b4252e21e217878ef0cf36bee18a3784add84 Mon Sep 17 00:00:00 2001 From: RSDuck Date: Thu, 23 Jul 2020 19:07:33 +0000 Subject: Make it buildable on aarch64 --- src/ARMJIT_A64/ARMJIT_LoadStore.cpp | 65 +++++++++++++++++++++++++------------ 1 file changed, 44 insertions(+), 21 deletions(-) (limited to 'src/ARMJIT_A64/ARMJIT_LoadStore.cpp') diff --git a/src/ARMJIT_A64/ARMJIT_LoadStore.cpp b/src/ARMJIT_A64/ARMJIT_LoadStore.cpp index bdd9f43..6aad0eb 100644 --- a/src/ARMJIT_A64/ARMJIT_LoadStore.cpp +++ b/src/ARMJIT_A64/ARMJIT_LoadStore.cpp @@ -174,8 +174,8 @@ void Compiler::Comp_MemAccess(int rd, int rn, Op2 offset, int size, int flags) LoadStorePatch patch; patch.PatchFunc = flags & memop_Store - ? PatchedStoreFuncs[Num][__builtin_ctz(size) - 3][rdMapped - W19] - : PatchedLoadFuncs[Num][__builtin_ctz(size) - 3][!!(flags & memop_SignExtend)][rdMapped - W19]; + ? PatchedStoreFuncs[NDS::ConsoleType][Num][__builtin_ctz(size) - 3][rdMapped - W19] + : PatchedLoadFuncs[NDS::ConsoleType][Num][__builtin_ctz(size) - 3][!!(flags & memop_SignExtend)][rdMapped - W19]; assert(rdMapped - W19 >= 0 && rdMapped - W19 < 8); MOVP2R(X7, Num == 0 ? ARMJIT_Memory::FastMem9Start : ARMJIT_Memory::FastMem7Start); @@ -241,20 +241,26 @@ void Compiler::Comp_MemAccess(int rd, int rn, Op2 offset, int size, int flags) if (flags & memop_Store) { MOV(W2, rdMapped); - switch (size) + switch (size | NDS::ConsoleType) { - case 32: QuickCallFunction(X3, SlowWrite9); break; - case 16: QuickCallFunction(X3, SlowWrite9); break; - case 8: QuickCallFunction(X3, SlowWrite9); break; + case 32: QuickCallFunction(X3, SlowWrite9); break; + case 33: QuickCallFunction(X3, SlowWrite9); break; + case 16: QuickCallFunction(X3, SlowWrite9); break; + case 17: QuickCallFunction(X3, SlowWrite9); break; + case 8: QuickCallFunction(X3, SlowWrite9); break; + case 9: QuickCallFunction(X3, SlowWrite9); break; } } else { switch (size) { - case 32: QuickCallFunction(X3, SlowRead9); break; - case 16: QuickCallFunction(X3, SlowRead9); break; - case 8: QuickCallFunction(X3, SlowRead9); break; + case 32: QuickCallFunction(X3, SlowRead9); break; + case 33: QuickCallFunction(X3, SlowRead9); break; + case 16: QuickCallFunction(X3, SlowRead9); break; + case 17: QuickCallFunction(X3, SlowRead9); break; + case 8: QuickCallFunction(X3, SlowRead9); break; + case 9: QuickCallFunction(X3, SlowRead9); break; } } } @@ -265,18 +271,24 @@ void Compiler::Comp_MemAccess(int rd, int rn, Op2 offset, int size, int flags) MOV(W1, rdMapped); switch (size) { - case 32: QuickCallFunction(X3, SlowWrite7); break; - case 16: QuickCallFunction(X3, SlowWrite7); break; - case 8: QuickCallFunction(X3, SlowWrite7); break; + case 32: QuickCallFunction(X3, SlowWrite7); break; + case 33: QuickCallFunction(X3, SlowWrite7); break; + case 16: QuickCallFunction(X3, SlowWrite7); break; + case 17: QuickCallFunction(X3, SlowWrite7); break; + case 8: QuickCallFunction(X3, SlowWrite7); break; + case 9: QuickCallFunction(X3, SlowWrite7); break; } } else { switch (size) { - case 32: QuickCallFunction(X3, SlowRead7); break; - case 16: QuickCallFunction(X3, SlowRead7); break; - case 8: QuickCallFunction(X3, SlowRead7); break; + case 32: QuickCallFunction(X3, SlowRead7); break; + case 33: QuickCallFunction(X3, SlowRead7); break; + case 16: QuickCallFunction(X3, SlowRead7); break; + case 17: QuickCallFunction(X3, SlowRead7); break; + case 8: QuickCallFunction(X3, SlowRead7); break; + case 9: QuickCallFunction(X3, SlowRead7); break; } } } @@ -465,15 +477,25 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc if (decrement) { - SUB(W0, MapReg(rn), regsCount * 4); - ANDI2R(W0, W0, ~3); - preinc ^= true; + s32 offset = -regsCount * 4 + (preinc ? 0 : 4); + if (offset) + { + ADDI2R(W0, MapReg(rn), offset); + ANDI2R(W0, W0, ~3); + } + else + { + ANDI2R(W0, MapReg(rn), ~3); + } } else { ANDI2R(W0, MapReg(rn), ~3); + if (preinc) + ADD(W0, W0, 4); } + u8* patchFunc; if (compileFastPath) { ptrdiff_t fastPathStart = GetCodeOffset(); @@ -482,7 +504,7 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc MOVP2R(X1, Num == 0 ? ARMJIT_Memory::FastMem9Start : ARMJIT_Memory::FastMem7Start); ADD(X1, X1, X0); - u32 offset = preinc ? 4 : 0; + u32 offset = 0; BitSet16::Iterator it = regs.begin(); u32 i = 0; @@ -545,7 +567,8 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc LoadStorePatch patch; patch.PatchSize = GetCodeOffset() - fastPathStart; SwapCodeRegion(); - patch.PatchFunc = GetRXPtr(); + patchFunc = (u8*)GetRXPtr(); + patch.PatchFunc = patchFunc; for (i = 0; i < regsCount; i++) { patch.PatchOffset = fastPathStart - loadStoreOffsets[i]; @@ -705,7 +728,7 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc ABI_PopRegisters({30}); RET(); - FlushIcacheSection((u8*)patch.PatchFunc, (u8*)GetRXPtr()); + FlushIcacheSection(patchFunc, (u8*)GetRXPtr()); SwapCodeRegion(); } -- cgit v1.2.3 From e85d2e2cf3439a79305f7132fbcd9774385e9020 Mon Sep 17 00:00:00 2001 From: RSDuck Date: Thu, 23 Jul 2020 19:12:25 +0000 Subject: Use the correct slow path for block read/write --- src/ARMJIT_A64/ARMJIT_LoadStore.cpp | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'src/ARMJIT_A64/ARMJIT_LoadStore.cpp') diff --git a/src/ARMJIT_A64/ARMJIT_LoadStore.cpp b/src/ARMJIT_A64/ARMJIT_LoadStore.cpp index 6aad0eb..0bddf74 100644 --- a/src/ARMJIT_A64/ARMJIT_LoadStore.cpp +++ b/src/ARMJIT_A64/ARMJIT_LoadStore.cpp @@ -643,22 +643,22 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc if (Num == 0) { MOV(X3, RCPU); - switch (preinc * 2 | store) + switch (store * 2 | NDS::ConsoleType) { - case 0: QuickCallFunction(X4, SlowBlockTransfer9); break; - case 1: QuickCallFunction(X4, SlowBlockTransfer9); break; - case 2: QuickCallFunction(X4, SlowBlockTransfer9); break; - case 3: QuickCallFunction(X4, SlowBlockTransfer9); break; + case 0: QuickCallFunction(X4, SlowBlockTransfer9); break; + case 1: QuickCallFunction(X4, SlowBlockTransfer9); break; + case 2: QuickCallFunction(X4, SlowBlockTransfer9); break; + case 3: QuickCallFunction(X4, SlowBlockTransfer9); break; } } else { - switch (preinc * 2 | store) + switch (store * 2 | NDS::ConsoleType) { - case 0: QuickCallFunction(X4, SlowBlockTransfer7); break; - case 1: QuickCallFunction(X4, SlowBlockTransfer7); break; - case 2: QuickCallFunction(X4, SlowBlockTransfer7); break; - case 3: QuickCallFunction(X4, SlowBlockTransfer7); break; + case 0: QuickCallFunction(X4, SlowBlockTransfer7); break; + case 1: QuickCallFunction(X4, SlowBlockTransfer7); break; + case 2: QuickCallFunction(X4, SlowBlockTransfer7); break; + case 3: QuickCallFunction(X4, SlowBlockTransfer7); break; } } -- cgit v1.2.3 From f5130f82eb75376b6bd508b01a50f6d79669a20b Mon Sep 17 00:00:00 2001 From: RSDuck Date: Thu, 23 Jul 2020 19:56:09 +0000 Subject: Arisotura isn't the only derp --- src/ARMJIT_A64/ARMJIT_LoadStore.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/ARMJIT_A64/ARMJIT_LoadStore.cpp') diff --git a/src/ARMJIT_A64/ARMJIT_LoadStore.cpp b/src/ARMJIT_A64/ARMJIT_LoadStore.cpp index 0bddf74..c965d80 100644 --- a/src/ARMJIT_A64/ARMJIT_LoadStore.cpp +++ b/src/ARMJIT_A64/ARMJIT_LoadStore.cpp @@ -253,7 +253,7 @@ void Compiler::Comp_MemAccess(int rd, int rn, Op2 offset, int size, int flags) } else { - switch (size) + switch (size | NDS::ConsoleType) { case 32: QuickCallFunction(X3, SlowRead9); break; case 33: QuickCallFunction(X3, SlowRead9); break; @@ -269,7 +269,7 @@ void Compiler::Comp_MemAccess(int rd, int rn, Op2 offset, int size, int flags) if (flags & memop_Store) { MOV(W1, rdMapped); - switch (size) + switch (size | NDS::ConsoleType) { case 32: QuickCallFunction(X3, SlowWrite7); break; case 33: QuickCallFunction(X3, SlowWrite7); break; @@ -281,7 +281,7 @@ void Compiler::Comp_MemAccess(int rd, int rn, Op2 offset, int size, int flags) } else { - switch (size) + switch (size | NDS::ConsoleType) { case 32: QuickCallFunction(X3, SlowRead7); break; case 33: QuickCallFunction(X3, SlowRead7); break; -- cgit v1.2.3 From 116d831cfd1b46afd436a4026a046e38dfd4ada6 Mon Sep 17 00:00:00 2001 From: RSDuck Date: Thu, 23 Jul 2020 20:06:44 +0000 Subject: Fix 16-bit DSi ARM9 read --- src/ARMJIT_A64/ARMJIT_LoadStore.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/ARMJIT_A64/ARMJIT_LoadStore.cpp') diff --git a/src/ARMJIT_A64/ARMJIT_LoadStore.cpp b/src/ARMJIT_A64/ARMJIT_LoadStore.cpp index c965d80..6140ffc 100644 --- a/src/ARMJIT_A64/ARMJIT_LoadStore.cpp +++ b/src/ARMJIT_A64/ARMJIT_LoadStore.cpp @@ -258,7 +258,7 @@ void Compiler::Comp_MemAccess(int rd, int rn, Op2 offset, int size, int flags) case 32: QuickCallFunction(X3, SlowRead9); break; case 33: QuickCallFunction(X3, SlowRead9); break; case 16: QuickCallFunction(X3, SlowRead9); break; - case 17: QuickCallFunction(X3, SlowRead9); break; + case 17: QuickCallFunction(X3, SlowRead9); break; case 8: QuickCallFunction(X3, SlowRead9); break; case 9: QuickCallFunction(X3, SlowRead9); break; } @@ -643,7 +643,7 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc if (Num == 0) { MOV(X3, RCPU); - switch (store * 2 | NDS::ConsoleType) + switch ((u32)store * 2 | NDS::ConsoleType) { case 0: QuickCallFunction(X4, SlowBlockTransfer9); break; case 1: QuickCallFunction(X4, SlowBlockTransfer9); break; @@ -653,7 +653,7 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc } else { - switch (store * 2 | NDS::ConsoleType) + switch ((u32)store * 2 | NDS::ConsoleType) { case 0: QuickCallFunction(X4, SlowBlockTransfer7); break; case 1: QuickCallFunction(X4, SlowBlockTransfer7); break; -- cgit v1.2.3