From 6f3b0498dbfb4f264f406901a774078fbe0eca6e Mon Sep 17 00:00:00 2001
From: StapleButter <thetotalworm@gmail.com>
Date: Mon, 30 Jan 2017 18:36:11 +0100
Subject: start refactoring shit: more accurate timing and way of counting
 cycles.

---
 ARMInterpreter_ALU.cpp | 280 ++++++++++++++++++++-----------------------------
 1 file changed, 112 insertions(+), 168 deletions(-)

(limited to 'ARMInterpreter_ALU.cpp')

diff --git a/ARMInterpreter_ALU.cpp b/ARMInterpreter_ALU.cpp
index 702c1c8..8e897b6 100644
--- a/ARMInterpreter_ALU.cpp
+++ b/ARMInterpreter_ALU.cpp
@@ -139,92 +139,92 @@ namespace ARMInterpreter
 
 #define A_IMPLEMENT_ALU_OP(x,s) \
 \
-s32 A_##x##_IMM(ARM* cpu) \
+void A_##x##_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_IMM \
     A_##x(0) \
 } \
-s32 A_##x##_REG_LSL_IMM(ARM* cpu) \
+void A_##x##_REG_LSL_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM) \
     A_##x(0) \
 } \
-s32 A_##x##_REG_LSR_IMM(ARM* cpu) \
+void A_##x##_REG_LSR_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM) \
     A_##x(0) \
 } \
-s32 A_##x##_REG_ASR_IMM(ARM* cpu) \
+void A_##x##_REG_ASR_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM) \
     A_##x(0) \
 } \
-s32 A_##x##_REG_ROR_IMM(ARM* cpu) \
+void A_##x##_REG_ROR_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM) \
     A_##x(0) \
 } \
-s32 A_##x##_REG_LSL_REG(ARM* cpu) \
+void A_##x##_REG_LSL_REG(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(LSL_REG) \
     A_##x(1) \
 } \
-s32 A_##x##_REG_LSR_REG(ARM* cpu) \
+void A_##x##_REG_LSR_REG(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(LSR_REG) \
     A_##x(1) \
 } \
-s32 A_##x##_REG_ASR_REG(ARM* cpu) \
+void A_##x##_REG_ASR_REG(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(ASR_REG) \
     A_##x(1) \
 } \
-s32 A_##x##_REG_ROR_REG(ARM* cpu) \
+void A_##x##_REG_ROR_REG(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(ROR_REG) \
     A_##x(1) \
 } \
-s32 A_##x##_IMM_S(ARM* cpu) \
+void A_##x##_IMM_S(ARM* cpu) \
 { \
     A_CALC_OP2_IMM \
     A_##x##_S(0) \
 } \
-s32 A_##x##_REG_LSL_IMM_S(ARM* cpu) \
+void A_##x##_REG_LSL_IMM_S(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM##s) \
     A_##x##_S(0) \
 } \
-s32 A_##x##_REG_LSR_IMM_S(ARM* cpu) \
+void A_##x##_REG_LSR_IMM_S(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM##s) \
     A_##x##_S(0) \
 } \
-s32 A_##x##_REG_ASR_IMM_S(ARM* cpu) \
+void A_##x##_REG_ASR_IMM_S(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM##s) \
     A_##x##_S(0) \
 } \
-s32 A_##x##_REG_ROR_IMM_S(ARM* cpu) \
+void A_##x##_REG_ROR_IMM_S(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM##s) \
     A_##x##_S(0) \
 } \
-s32 A_##x##_REG_LSL_REG_S(ARM* cpu) \
+void A_##x##_REG_LSL_REG_S(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(LSL_REG##s) \
     A_##x##_S(1) \
 } \
-s32 A_##x##_REG_LSR_REG_S(ARM* cpu) \
+void A_##x##_REG_LSR_REG_S(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(LSR_REG##s) \
     A_##x##_S(1) \
 } \
-s32 A_##x##_REG_ASR_REG_S(ARM* cpu) \
+void A_##x##_REG_ASR_REG_S(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(ASR_REG##s) \
     A_##x##_S(1) \
 } \
-s32 A_##x##_REG_ROR_REG_S(ARM* cpu) \
+void A_##x##_REG_ROR_REG_S(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(ROR_REG##s) \
     A_##x##_S(1) \
@@ -232,47 +232,47 @@ s32 A_##x##_REG_ROR_REG_S(ARM* cpu) \
 
 #define A_IMPLEMENT_ALU_TEST(x,s) \
 \
-s32 A_##x##_IMM(ARM* cpu) \
+void A_##x##_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_IMM \
     A_##x(0) \
 } \
-s32 A_##x##_REG_LSL_IMM(ARM* cpu) \
+void A_##x##_REG_LSL_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM##s) \
     A_##x(0) \
 } \
-s32 A_##x##_REG_LSR_IMM(ARM* cpu) \
+void A_##x##_REG_LSR_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM##s) \
     A_##x(0) \
 } \
-s32 A_##x##_REG_ASR_IMM(ARM* cpu) \
+void A_##x##_REG_ASR_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM##s) \
     A_##x(0) \
 } \
-s32 A_##x##_REG_ROR_IMM(ARM* cpu) \
+void A_##x##_REG_ROR_IMM(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM##s) \
     A_##x(0) \
 } \
-s32 A_##x##_REG_LSL_REG(ARM* cpu) \
+void A_##x##_REG_LSL_REG(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(LSL_REG##s) \
     A_##x(1) \
 } \
-s32 A_##x##_REG_LSR_REG(ARM* cpu) \
+void A_##x##_REG_LSR_REG(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(LSR_REG##s) \
     A_##x(1) \
 } \
-s32 A_##x##_REG_ASR_REG(ARM* cpu) \
+void A_##x##_REG_ASR_REG(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(ASR_REG##s) \
     A_##x(1) \
 } \
-s32 A_##x##_REG_ROR_REG(ARM* cpu) \
+void A_##x##_REG_ROR_REG(ARM* cpu) \
 { \
     A_CALC_OP2_REG_SHIFT_REG(ROR_REG##s) \
     A_##x(1) \
@@ -282,15 +282,14 @@ s32 A_##x##_REG_ROR_REG(ARM* cpu) \
 #define A_AND(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = a & b; \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_AND_S(c) \
@@ -298,15 +297,14 @@ s32 A_##x##_REG_ROR_REG(ARM* cpu) \
     u32 res = a & b; \
     cpu->SetNZ(res & 0x80000000, \
                !res); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(AND,_S)
@@ -315,15 +313,14 @@ A_IMPLEMENT_ALU_OP(AND,_S)
 #define A_EOR(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = a ^ b; \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_EOR_S(c) \
@@ -331,15 +328,14 @@ A_IMPLEMENT_ALU_OP(AND,_S)
     u32 res = a ^ b; \
     cpu->SetNZ(res & 0x80000000, \
                !res); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(EOR,_S)
@@ -348,15 +344,14 @@ A_IMPLEMENT_ALU_OP(EOR,_S)
 #define A_SUB(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = a - b; \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_SUB_S(c) \
@@ -366,15 +361,14 @@ A_IMPLEMENT_ALU_OP(EOR,_S)
                  !res, \
                  CARRY_SUB(a, b), \
                  OVERFLOW_SUB(a, b, res)); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(SUB,)
@@ -383,15 +377,14 @@ A_IMPLEMENT_ALU_OP(SUB,)
 #define A_RSB(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = b - a; \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_RSB_S(c) \
@@ -401,15 +394,14 @@ A_IMPLEMENT_ALU_OP(SUB,)
                  !res, \
                  CARRY_SUB(b, a), \
                  OVERFLOW_SUB(b, a, res)); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(RSB,)
@@ -418,15 +410,14 @@ A_IMPLEMENT_ALU_OP(RSB,)
 #define A_ADD(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = a + b; \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_ADD_S(c) \
@@ -436,15 +427,14 @@ A_IMPLEMENT_ALU_OP(RSB,)
                  !res, \
                  CARRY_ADD(a, b), \
                  OVERFLOW_ADD(a, b, res)); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(ADD,)
@@ -453,15 +443,14 @@ A_IMPLEMENT_ALU_OP(ADD,)
 #define A_ADC(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = a + b + (cpu->CPSR&0x20000000 ? 1:0); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_ADC_S(c) \
@@ -473,15 +462,14 @@ A_IMPLEMENT_ALU_OP(ADD,)
                  !res, \
                  CARRY_ADD(a, b) | CARRY_ADD(res_tmp, carry), \
                  OVERFLOW_ADD(a, b, res_tmp) | OVERFLOW_ADD(res_tmp, carry, res)); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(ADC,)
@@ -490,15 +478,14 @@ A_IMPLEMENT_ALU_OP(ADC,)
 #define A_SBC(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = a - b - (cpu->CPSR&0x20000000 ? 0:1); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_SBC_S(c) \
@@ -510,15 +497,14 @@ A_IMPLEMENT_ALU_OP(ADC,)
                  !res, \
                  CARRY_SUB(a, b) & CARRY_SUB(res_tmp, carry), \
                  OVERFLOW_SUB(a, b, res_tmp) | OVERFLOW_SUB(res_tmp, carry, res)); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(SBC,)
@@ -527,15 +513,14 @@ A_IMPLEMENT_ALU_OP(SBC,)
 #define A_RSC(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = b - a - (cpu->CPSR&0x20000000 ? 0:1); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_RSC_S(c) \
@@ -547,15 +532,14 @@ A_IMPLEMENT_ALU_OP(SBC,)
                  !res, \
                  CARRY_SUB(b, a) & CARRY_SUB(res_tmp, carry), \
                  OVERFLOW_SUB(b, a, res_tmp) | OVERFLOW_SUB(res_tmp, carry, res)); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(RSC,)
@@ -566,7 +550,7 @@ A_IMPLEMENT_ALU_OP(RSC,)
     u32 res = a & b; \
     cpu->SetNZ(res & 0x80000000, \
                !res); \
-    return C_S(1) + C_I(c);
+    cpu->Cycles += c;
 
 A_IMPLEMENT_ALU_TEST(TST,_S)
 
@@ -576,7 +560,7 @@ A_IMPLEMENT_ALU_TEST(TST,_S)
     u32 res = a ^ b; \
     cpu->SetNZ(res & 0x80000000, \
                !res); \
-    return C_S(1) + C_I(c);
+    cpu->Cycles += c;
 
 A_IMPLEMENT_ALU_TEST(TEQ,_S)
 
@@ -588,7 +572,7 @@ A_IMPLEMENT_ALU_TEST(TEQ,_S)
                  !res, \
                  CARRY_SUB(a, b), \
                  OVERFLOW_SUB(a, b, res)); \
-    return C_S(1) + C_I(c);
+    cpu->Cycles += c;
 
 A_IMPLEMENT_ALU_TEST(CMP,)
 
@@ -600,7 +584,7 @@ A_IMPLEMENT_ALU_TEST(CMP,)
                  !res, \
                  CARRY_ADD(a, b), \
                  OVERFLOW_ADD(a, b, res)); \
-    return C_S(1) + C_I(c);
+    cpu->Cycles += c;
 
 A_IMPLEMENT_ALU_TEST(CMN,)
 
@@ -608,15 +592,14 @@ A_IMPLEMENT_ALU_TEST(CMN,)
 #define A_ORR(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = a | b; \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_ORR_S(c) \
@@ -624,44 +607,41 @@ A_IMPLEMENT_ALU_TEST(CMN,)
     u32 res = a | b; \
     cpu->SetNZ(res & 0x80000000, \
                !res); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(ORR,_S)
 
 
 #define A_MOV(c) \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(b); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = b; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_MOV_S(c) \
     cpu->SetNZ(b & 0x80000000, \
                !b); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(b, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = b; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(MOV,_S)
@@ -670,15 +650,14 @@ A_IMPLEMENT_ALU_OP(MOV,_S)
 #define A_BIC(c) \
     u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 res = a & ~b; \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_BIC_S(c) \
@@ -686,15 +665,14 @@ A_IMPLEMENT_ALU_OP(MOV,_S)
     u32 res = a & ~b; \
     cpu->SetNZ(res & 0x80000000, \
                !res); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(res, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(BIC,_S)
@@ -702,37 +680,35 @@ A_IMPLEMENT_ALU_OP(BIC,_S)
 
 #define A_MVN(c) \
     b = ~b; \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(b); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = b; \
-        return C_S(1) + C_I(c); \
     }
 
 #define A_MVN_S(c) \
     b = ~b; \
     cpu->SetNZ(b & 0x80000000, \
                !b); \
+    cpu->Cycles += c; \
     if (((cpu->CurInstr>>12) & 0xF) == 15) \
     { \
         cpu->JumpTo(b, true); \
-        return C_S(2) + C_I(c) + C_N(1); \
     } \
     else \
     { \
         cpu->R[(cpu->CurInstr>>12) & 0xF] = b; \
-        return C_S(1) + C_I(c); \
     }
 
 A_IMPLEMENT_ALU_OP(MVN,_S)
 
 
 
-s32 A_MUL(ARM* cpu)
+void A_MUL(ARM* cpu)
 {
     u32 rm = cpu->R[cpu->CurInstr & 0xF];
     u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@@ -753,10 +729,10 @@ s32 A_MUL(ARM* cpu)
     else if ((rs & 0xFF000000) == 0x00000000 || (rs & 0xFF000000) == 0xFF000000) cycles = 3;
     else cycles = 4;
 
-    return C_S(1) + C_I(cycles);
+    cpu->Cycles += cycles;
 }
 
-s32 A_MLA(ARM* cpu)
+void A_MLA(ARM* cpu)
 {
     u32 rm = cpu->R[cpu->CurInstr & 0xF];
     u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@@ -778,10 +754,10 @@ s32 A_MLA(ARM* cpu)
     else if ((rs & 0xFF000000) == 0x00000000 || (rs & 0xFF000000) == 0xFF000000) cycles = 4;
     else cycles = 5;
 
-    return C_S(1) + C_I(cycles);
+    cpu->Cycles += cycles;
 }
 
-s32 A_UMULL(ARM* cpu)
+void A_UMULL(ARM* cpu)
 {
     u32 rm = cpu->R[cpu->CurInstr & 0xF];
     u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@@ -803,10 +779,10 @@ s32 A_UMULL(ARM* cpu)
     else if ((rs & 0xFF000000) == 0x00000000) cycles = 4;
     else cycles = 5;
 
-    return C_S(1) + C_I(cycles);
+    cpu->Cycles += cycles;
 }
 
-s32 A_UMLAL(ARM* cpu)
+void A_UMLAL(ARM* cpu)
 {
     u32 rm = cpu->R[cpu->CurInstr & 0xF];
     u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@@ -831,10 +807,10 @@ s32 A_UMLAL(ARM* cpu)
     else if ((rs & 0xFF000000) == 0x00000000) cycles = 4;
     else cycles = 5;
 
-    return C_S(1) + C_I(cycles);
+    cpu->Cycles += cycles;
 }
 
-s32 A_SMULL(ARM* cpu)
+void A_SMULL(ARM* cpu)
 {
     u32 rm = cpu->R[cpu->CurInstr & 0xF];
     u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@@ -856,10 +832,10 @@ s32 A_SMULL(ARM* cpu)
     else if ((rs & 0xFF000000) == 0x00000000 || (rs & 0xFF000000) == 0xFF000000) cycles = 4;
     else cycles = 5;
 
-    return C_S(1) + C_I(cycles);
+    cpu->Cycles += cycles;
 }
 
-s32 A_SMLAL(ARM* cpu)
+void A_SMLAL(ARM* cpu)
 {
     u32 rm = cpu->R[cpu->CurInstr & 0xF];
     u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@@ -884,12 +860,12 @@ s32 A_SMLAL(ARM* cpu)
     else if ((rs & 0xFF000000) == 0x00000000 || (rs & 0xFF000000) == 0xFF000000) cycles = 4;
     else cycles = 5;
 
-    return C_S(1) + C_I(cycles);
+    cpu->Cycles += cycles;
 }
 
 
 
-s32 A_CLZ(ARM* cpu)
+void A_CLZ(ARM* cpu)
 {
     // TODO: ARM9 only
 
@@ -910,8 +886,6 @@ s32 A_CLZ(ARM* cpu)
     }
 
     cpu->R[(cpu->CurInstr >> 12) & 0xF] = res;
-
-    return C_S(1);
 }
 
 
@@ -920,7 +894,7 @@ s32 A_CLZ(ARM* cpu)
 
 
 
-s32 T_LSL_IMM(ARM* cpu)
+void T_LSL_IMM(ARM* cpu)
 {
     u32 op = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 s = (cpu->CurInstr >> 6) & 0x1F;
@@ -928,10 +902,9 @@ s32 T_LSL_IMM(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = op;
     cpu->SetNZ(op & 0x80000000,
                !op);
-    return C_S(1);
 }
 
-s32 T_LSR_IMM(ARM* cpu)
+void T_LSR_IMM(ARM* cpu)
 {
     u32 op = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 s = (cpu->CurInstr >> 6) & 0x1F;
@@ -939,10 +912,9 @@ s32 T_LSR_IMM(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = op;
     cpu->SetNZ(op & 0x80000000,
                !op);
-    return C_S(1);
 }
 
-s32 T_ASR_IMM(ARM* cpu)
+void T_ASR_IMM(ARM* cpu)
 {
     u32 op = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 s = (cpu->CurInstr >> 6) & 0x1F;
@@ -950,10 +922,9 @@ s32 T_ASR_IMM(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = op;
     cpu->SetNZ(op & 0x80000000,
                !op);
-    return C_S(1);
 }
 
-s32 T_ADD_REG_(ARM* cpu)
+void T_ADD_REG_(ARM* cpu)
 {
     u32 a = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 6) & 0x7];
@@ -963,10 +934,9 @@ s32 T_ADD_REG_(ARM* cpu)
                  !res,
                  CARRY_ADD(a, b),
                  OVERFLOW_ADD(a, b, res));
-    return C_S(1);
 }
 
-s32 T_SUB_REG_(ARM* cpu)
+void T_SUB_REG_(ARM* cpu)
 {
     u32 a = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 6) & 0x7];
@@ -976,10 +946,9 @@ s32 T_SUB_REG_(ARM* cpu)
                  !res,
                  CARRY_SUB(a, b),
                  OVERFLOW_SUB(a, b, res));
-    return C_S(1);
 }
 
-s32 T_ADD_IMM_(ARM* cpu)
+void T_ADD_IMM_(ARM* cpu)
 {
     u32 a = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 b = (cpu->CurInstr >> 6) & 0x7;
@@ -989,10 +958,9 @@ s32 T_ADD_IMM_(ARM* cpu)
                  !res,
                  CARRY_ADD(a, b),
                  OVERFLOW_ADD(a, b, res));
-    return C_S(1);
 }
 
-s32 T_SUB_IMM_(ARM* cpu)
+void T_SUB_IMM_(ARM* cpu)
 {
     u32 a = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 b = (cpu->CurInstr >> 6) & 0x7;
@@ -1002,19 +970,17 @@ s32 T_SUB_IMM_(ARM* cpu)
                  !res,
                  CARRY_SUB(a, b),
                  OVERFLOW_SUB(a, b, res));
-    return C_S(1);
 }
 
-s32 T_MOV_IMM(ARM* cpu)
+void T_MOV_IMM(ARM* cpu)
 {
     u32 b = cpu->CurInstr & 0xFF;
     cpu->R[(cpu->CurInstr >> 8) & 0x7] = b;
     cpu->SetNZ(0,
                !b);
-    return C_S(1);
 }
 
-s32 T_CMP_IMM(ARM* cpu)
+void T_CMP_IMM(ARM* cpu)
 {
     u32 a = cpu->R[(cpu->CurInstr >> 8) & 0x7];
     u32 b = cpu->CurInstr & 0xFF;
@@ -1023,10 +989,9 @@ s32 T_CMP_IMM(ARM* cpu)
                  !res,
                  CARRY_SUB(a, b),
                  OVERFLOW_SUB(a, b, res));
-    return C_S(1);
 }
 
-s32 T_ADD_IMM(ARM* cpu)
+void T_ADD_IMM(ARM* cpu)
 {
     u32 a = cpu->R[(cpu->CurInstr >> 8) & 0x7];
     u32 b = cpu->CurInstr & 0xFF;
@@ -1036,10 +1001,9 @@ s32 T_ADD_IMM(ARM* cpu)
                  !res,
                  CARRY_ADD(a, b),
                  OVERFLOW_ADD(a, b, res));
-    return C_S(1);
 }
 
-s32 T_SUB_IMM(ARM* cpu)
+void T_SUB_IMM(ARM* cpu)
 {
     u32 a = cpu->R[(cpu->CurInstr >> 8) & 0x7];
     u32 b = cpu->CurInstr & 0xFF;
@@ -1049,11 +1013,10 @@ s32 T_SUB_IMM(ARM* cpu)
                  !res,
                  CARRY_SUB(a, b),
                  OVERFLOW_SUB(a, b, res));
-    return C_S(1);
 }
 
 
-s32 T_AND_REG(ARM* cpu)
+void T_AND_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
@@ -1061,10 +1024,9 @@ s32 T_AND_REG(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = res;
     cpu->SetNZ(res & 0x80000000,
                !res);
-    return C_S(1);
 }
 
-s32 T_EOR_REG(ARM* cpu)
+void T_EOR_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
@@ -1072,10 +1034,9 @@ s32 T_EOR_REG(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = res;
     cpu->SetNZ(res & 0x80000000,
                !res);
-    return C_S(1);
 }
 
-s32 T_LSL_REG(ARM* cpu)
+void T_LSL_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7] & 0xFF;
@@ -1083,10 +1044,10 @@ s32 T_LSL_REG(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = a;
     cpu->SetNZ(a & 0x80000000,
                !a);
-    return C_S(1) + C_I(1);
+    cpu->Cycles += 1;
 }
 
-s32 T_LSR_REG(ARM* cpu)
+void T_LSR_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7] & 0xFF;
@@ -1094,10 +1055,10 @@ s32 T_LSR_REG(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = a;
     cpu->SetNZ(a & 0x80000000,
                !a);
-    return C_S(1) + C_I(1);
+    cpu->Cycles += 1;
 }
 
-s32 T_ASR_REG(ARM* cpu)
+void T_ASR_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7] & 0xFF;
@@ -1105,10 +1066,10 @@ s32 T_ASR_REG(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = a;
     cpu->SetNZ(a & 0x80000000,
                !a);
-    return C_S(1) + C_I(1);
+    cpu->Cycles += 1;
 }
 
-s32 T_ADC_REG(ARM* cpu)
+void T_ADC_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
@@ -1120,10 +1081,9 @@ s32 T_ADC_REG(ARM* cpu)
                  !res,
                  CARRY_ADD(a, b) | CARRY_ADD(res_tmp, carry),
                  OVERFLOW_ADD(a, b, res_tmp) | OVERFLOW_ADD(res_tmp, carry, res));
-    return C_S(1);
 }
 
-s32 T_SBC_REG(ARM* cpu)
+void T_SBC_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
@@ -1135,10 +1095,9 @@ s32 T_SBC_REG(ARM* cpu)
                  !res,
                  CARRY_SUB(a, b) & CARRY_SUB(res_tmp, carry),
                  OVERFLOW_SUB(a, b, res_tmp) | OVERFLOW_SUB(res_tmp, carry, res));
-    return C_S(1);
 }
 
-s32 T_ROR_REG(ARM* cpu)
+void T_ROR_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7] & 0xFF;
@@ -1146,30 +1105,28 @@ s32 T_ROR_REG(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = a;
     cpu->SetNZ(a & 0x80000000,
                !a);
-    return C_S(1) + C_I(1);
+    cpu->Cycles += 1;
 }
 
-s32 T_TST_REG(ARM* cpu)
+void T_TST_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 res = a & b;
     cpu->SetNZ(res & 0x80000000,
                !res);
-    return C_S(1);
 }
 
-s32 T_NEG_REG(ARM* cpu)
+void T_NEG_REG(ARM* cpu)
 {
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 res = -b;
     cpu->R[cpu->CurInstr & 0x7] = res;
     cpu->SetNZ(res & 0x80000000,
                !res);
-    return C_S(1);
 }
 
-s32 T_CMP_REG(ARM* cpu)
+void T_CMP_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
@@ -1178,10 +1135,9 @@ s32 T_CMP_REG(ARM* cpu)
                  !res,
                  CARRY_SUB(a, b),
                  OVERFLOW_SUB(a, b, res));
-    return C_S(1);
 }
 
-s32 T_CMN_REG(ARM* cpu)
+void T_CMN_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
@@ -1190,10 +1146,9 @@ s32 T_CMN_REG(ARM* cpu)
                  !res,
                  CARRY_ADD(a, b),
                  OVERFLOW_ADD(a, b, res));
-    return C_S(1);
 }
 
-s32 T_ORR_REG(ARM* cpu)
+void T_ORR_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
@@ -1201,10 +1156,9 @@ s32 T_ORR_REG(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = res;
     cpu->SetNZ(res & 0x80000000,
                !res);
-    return C_S(1);
 }
 
-s32 T_MUL_REG(ARM* cpu)
+void T_MUL_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
@@ -1213,23 +1167,23 @@ s32 T_MUL_REG(ARM* cpu)
     cpu->SetNZ(res & 0x80000000,
                !res);
 
-    s32 cycles = C_S(1);
+    s32 cycles = 0;
     if (cpu->Num == 0)
     {
-        cycles += C_I(3);
+        cycles += 3;
     }
     else
     {
         cpu->SetC(0); // carry flag destroyed, they say. whatever that means...
-        if      (a & 0xFF000000) cycles += C_I(4);
-        else if (a & 0x00FF0000) cycles += C_I(3);
-        else if (a & 0x0000FF00) cycles += C_I(2);
-        else                     cycles += C_I(1);
+        if      (a & 0xFF000000) cycles += 4;
+        else if (a & 0x00FF0000) cycles += 3;
+        else if (a & 0x0000FF00) cycles += 2;
+        else                     cycles += 1;
     }
-    return cycles;
+    cpu->Cycles += cycles;
 }
 
-s32 T_BIC_REG(ARM* cpu)
+void T_BIC_REG(ARM* cpu)
 {
     u32 a = cpu->R[cpu->CurInstr & 0x7];
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
@@ -1237,21 +1191,19 @@ s32 T_BIC_REG(ARM* cpu)
     cpu->R[cpu->CurInstr & 0x7] = res;
     cpu->SetNZ(res & 0x80000000,
                !res);
-    return C_S(1);
 }
 
-s32 T_MVN_REG(ARM* cpu)
+void T_MVN_REG(ARM* cpu)
 {
     u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
     u32 res = ~b;
     cpu->R[cpu->CurInstr & 0x7] = res;
     cpu->SetNZ(res & 0x80000000,
                !res);
-    return C_S(1);
 }
 
 
-s32 T_ADD_HIREG(ARM* cpu)
+void T_ADD_HIREG(ARM* cpu)
 {
     u32 rd = (cpu->CurInstr & 0x7) | ((cpu->CurInstr >> 4) & 0x8);
     u32 rs = (cpu->CurInstr >> 3) & 0xF;
@@ -1262,16 +1214,14 @@ s32 T_ADD_HIREG(ARM* cpu)
     if (rd == 15)
     {
         cpu->JumpTo((a + b) | 1);
-        return C_S(2) + C_N(1);
     }
     else
     {
         cpu->R[rd] = a + b;
-        return C_S(1);
     }
 }
 
-s32 T_CMP_HIREG(ARM* cpu)
+void T_CMP_HIREG(ARM* cpu)
 {
     u32 rd = (cpu->CurInstr & 0x7) | ((cpu->CurInstr >> 4) & 0x8);
     u32 rs = (cpu->CurInstr >> 3) & 0xF;
@@ -1284,10 +1234,9 @@ s32 T_CMP_HIREG(ARM* cpu)
                  !res,
                  CARRY_SUB(a, b),
                  OVERFLOW_SUB(a, b, res));
-    return C_S(1);
 }
 
-s32 T_MOV_HIREG(ARM* cpu)
+void T_MOV_HIREG(ARM* cpu)
 {
     u32 rd = (cpu->CurInstr & 0x7) | ((cpu->CurInstr >> 4) & 0x8);
     u32 rs = (cpu->CurInstr >> 3) & 0xF;
@@ -1295,33 +1244,29 @@ s32 T_MOV_HIREG(ARM* cpu)
     if (rd == 15)
     {
         cpu->JumpTo(cpu->R[rs] | 1);
-        return C_S(2) + C_N(1);
     }
     else
     {
         cpu->R[rd] = cpu->R[rs];
-        return C_S(1);
     }
 }
 
 
-s32 T_ADD_PCREL(ARM* cpu)
+void T_ADD_PCREL(ARM* cpu)
 {
     u32 val = cpu->R[15] & ~2;
     val += ((cpu->CurInstr & 0xFF) << 2);
     cpu->R[(cpu->CurInstr >> 8) & 0x7] = val;
-    return C_S(1);
 }
 
-s32 T_ADD_SPREL(ARM* cpu)
+void T_ADD_SPREL(ARM* cpu)
 {
     u32 val = cpu->R[13];
     val += ((cpu->CurInstr & 0xFF) << 2);
     cpu->R[(cpu->CurInstr >> 8) & 0x7] = val;
-    return C_S(1);
 }
 
-s32 T_ADD_SP(ARM* cpu)
+void T_ADD_SP(ARM* cpu)
 {
     u32 val = cpu->R[13];
     if (cpu->CurInstr & (1<<7))
@@ -1329,7 +1274,6 @@ s32 T_ADD_SP(ARM* cpu)
     else
         val += ((cpu->CurInstr & 0x7F) << 2);
     cpu->R[13] = val;
-    return C_S(1);
 }
 
 
-- 
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