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path: root/src/ARMJIT_x64
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* implement block linking + some refactoringRSDuck2020-04-26
| | | | currently only supported for x64
* include more information in DataRegionRSDuck2020-04-26
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* improve nop handling and proper behaviour for LDM^RSDuck2020-04-26
| | | | fixes dslinux
* disable literal optimations in DTCMRSDuck2020-04-26
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* make literal optimisation more reliableRSDuck2020-04-26
| | | | fixes spanish Pokemon HeartGold
* integrate changes from ARM64 backend and moreRSDuck2020-04-26
| | | | | | | | | - better handle LDM/STM in reg alloc - unify Halted and IRQ in anticipation for branch inlining - literal optimisations can be disabled in gui - jit blocks follow simple returns - fix idle loop detection - break jit blocks on IRQ (fixes saving in Pokemon White)
* decrease jit block cache address granularityRSDuck2020-04-26
| | | | | | | fixes Dragon Quest IX move code with side effects out of assert, fixes release build (thanks to m4wx for this one) also remove some leftovers of jit pipelining
* remove leftover debug codeRSDuck2020-04-26
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* new block cache and much more...RSDuck2020-04-26
| | | | | | | | | - more reliable code invalidation detection - blocks aren't stopped at any branch, but are being followed if possible to get larger blocks - idle loop recognition - optimised literal loads, load/store cycle counting and loads/stores from constant addresses
* load register only if neededRSDuck2020-04-26
| | | | | - do thumb bl long merge in the first step - preparations for better branch jitting
* more fixes for flag optimisationRSDuck2020-04-26
| | | | + small cycle counting optimisation
* remove debug printingRSDuck2020-04-26
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* fixes for flag optimisationRSDuck2020-04-26
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* optimise away unneeded flag setsRSDuck2020-04-26
| | | | | - especially useful for thumb code and larger max block sizes - can still be improved upon
* abandon pipelining on jitRSDuck2020-04-26
| | | | | fixes Golden Sun Dawn this makes the cpu state incompatible between interpreter and JIT. That's why switching cpu mode requires a restart(not requiring is stupid anyway) and the pipeline is manually filled when making a save state.
* remove unneeded dolphin code, C++11 static_assertRSDuck2020-04-26
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* jit: fix RSCRSDuck2020-04-26
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* jit: fix thumb hi reg alu and mcr haltRSDuck2020-04-26
| | | | + mcr/mrc aren't always, msr_imm is never unk on ARM7
* jit: decrease blockcache AddrMapping size for ARM9RSDuck2020-04-26
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* jit: fix misc static branch thingsRSDuck2020-04-26
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* jit: LDM/STM keep proper stack alignmentRSDuck2020-04-26
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* jit: fix BLX_reg with rn=lrRSDuck2020-04-26
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* jit: add compile optionRSDuck2020-04-26
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* jit: make everything configurableRSDuck2020-04-26
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* jit: fix linuxRSDuck2020-04-26
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* jit: fix wrongly placed constRSDuck2020-04-26
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* jit: SMULL and SMLALRSDuck2020-04-26
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* jit: LDM/STM finally(!) working + MUL, MLA and CLZRSDuck2020-04-26
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* jit: branch instructionsRSDuck2020-04-26
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* jit: thumb block transfer workingRSDuck2020-04-26
| | | | also pc and sp relative loads and some refactoring
* JIT: most mem instructions workingRSDuck2020-04-26
| | | | + branching
* JIT: compilation of word load and storeRSDuck2020-04-26
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* jit: correct cycle counting for thumb shift by regRSDuck2020-04-26
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* JIT: implemented most ALU instructionsRSDuck2020-04-26
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* JIT: baseRSDuck2020-04-26
all instructions are interpreted