| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | misc JIT changes | RSDuck | 2020-07-08 |
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| * | make linux work and fix a few bugs | RSDuck | 2020-07-04 |
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| * | reconcile DSi and JIT, fastmem for x64 and Windows | RSDuck | 2020-06-30 |
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| * | make literal optimisation work again | RSDuck | 2020-06-16 |
| | | | | | enable single register block load/store optimisations for x64 aswell | ||
| * | first steps in bringing over the JIT refactor/fastmem | RSDuck | 2020-06-16 |
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| * | fix inlined IO register access | RSDuck | 2020-06-16 |
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| * | allow allocating caller saved regs on windows | RSDuck | 2020-05-09 |
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| * | allow allocating caller saved registers | RSDuck | 2020-05-09 |
| | | | | | currently system-v only | ||
| * | rewrite JIT memory emulation | RSDuck | 2020-05-09 |
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| * | fix regression from last commit | RSDuck | 2020-04-26 |
| | | | | | also a small mistake with msr | ||
| * | don't use param registers for ReadBanked/WriteBanked | RSDuck | 2020-04-26 |
| | | | | | should fix linux build | ||
| * | hopefully fix stack handling for linux | RSDuck | 2020-04-26 |
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| * | implement msr and mrs for the x64 JIT | RSDuck | 2020-04-26 |
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| * | compile UMULLs and some fixes | RSDuck | 2020-04-26 |
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| * | implement block linking + some refactoring | RSDuck | 2020-04-26 |
| | | | | | currently only supported for x64 | ||
| * | include more information in DataRegion | RSDuck | 2020-04-26 |
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| * | improve nop handling and proper behaviour for LDM^ | RSDuck | 2020-04-26 |
| | | | | | fixes dslinux | ||
| * | disable literal optimations in DTCM | RSDuck | 2020-04-26 |
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| * | make literal optimisation more reliable | RSDuck | 2020-04-26 |
| | | | | | fixes spanish Pokemon HeartGold | ||
| * | integrate changes from ARM64 backend and more | RSDuck | 2020-04-26 |
| | | | | | | | | | | - better handle LDM/STM in reg alloc - unify Halted and IRQ in anticipation for branch inlining - literal optimisations can be disabled in gui - jit blocks follow simple returns - fix idle loop detection - break jit blocks on IRQ (fixes saving in Pokemon White) | ||
| * | decrease jit block cache address granularity | RSDuck | 2020-04-26 |
| | | | | | | | | fixes Dragon Quest IX move code with side effects out of assert, fixes release build (thanks to m4wx for this one) also remove some leftovers of jit pipelining | ||
| * | remove leftover debug code | RSDuck | 2020-04-26 |
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| * | new block cache and much more... | RSDuck | 2020-04-26 |
| | | | | | | | | | | - more reliable code invalidation detection - blocks aren't stopped at any branch, but are being followed if possible to get larger blocks - idle loop recognition - optimised literal loads, load/store cycle counting and loads/stores from constant addresses | ||
| * | load register only if needed | RSDuck | 2020-04-26 |
| | | | | | | - do thumb bl long merge in the first step - preparations for better branch jitting | ||
| * | more fixes for flag optimisation | RSDuck | 2020-04-26 |
| | | | | | + small cycle counting optimisation | ||
| * | remove debug printing | RSDuck | 2020-04-26 |
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| * | fixes for flag optimisation | RSDuck | 2020-04-26 |
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| * | optimise away unneeded flag sets | RSDuck | 2020-04-26 |
| | | | | | | - especially useful for thumb code and larger max block sizes - can still be improved upon | ||
| * | abandon pipelining on jit | RSDuck | 2020-04-26 |
| | | | | | | fixes Golden Sun Dawn this makes the cpu state incompatible between interpreter and JIT. That's why switching cpu mode requires a restart(not requiring is stupid anyway) and the pipeline is manually filled when making a save state. | ||
| * | remove unneeded dolphin code, C++11 static_assert | RSDuck | 2020-04-26 |
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| * | jit: fix RSC | RSDuck | 2020-04-26 |
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| * | jit: fix thumb hi reg alu and mcr halt | RSDuck | 2020-04-26 |
| | | | | | + mcr/mrc aren't always, msr_imm is never unk on ARM7 | ||
| * | jit: decrease blockcache AddrMapping size for ARM9 | RSDuck | 2020-04-26 |
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| * | jit: fix misc static branch things | RSDuck | 2020-04-26 |
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| * | jit: LDM/STM keep proper stack alignment | RSDuck | 2020-04-26 |
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| * | jit: fix BLX_reg with rn=lr | RSDuck | 2020-04-26 |
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| * | jit: add compile option | RSDuck | 2020-04-26 |
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| * | jit: make everything configurable | RSDuck | 2020-04-26 |
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| * | jit: fix linux | RSDuck | 2020-04-26 |
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| * | jit: fix wrongly placed const | RSDuck | 2020-04-26 |
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| * | jit: SMULL and SMLAL | RSDuck | 2020-04-26 |
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| * | jit: LDM/STM finally(!) working + MUL, MLA and CLZ | RSDuck | 2020-04-26 |
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| * | jit: branch instructions | RSDuck | 2020-04-26 |
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| * | jit: thumb block transfer working | RSDuck | 2020-04-26 |
| | | | | | also pc and sp relative loads and some refactoring | ||
| * | JIT: most mem instructions working | RSDuck | 2020-04-26 |
| | | | | | + branching | ||
| * | JIT: compilation of word load and store | RSDuck | 2020-04-26 |
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| * | jit: correct cycle counting for thumb shift by reg | RSDuck | 2020-04-26 |
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| * | JIT: implemented most ALU instructions | RSDuck | 2020-04-26 |
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| * | JIT: base | RSDuck | 2020-04-26 |
| all instructions are interpreted | |||