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path: root/src/ARMJIT_RegisterCache.h
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* for some reason tabs and spaces were mixedRSDuck2020-07-23
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* rewrite JIT memory emulationRSDuck2020-05-09
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* git played a prank on me haha very funnyRSDuck2020-04-26
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* this it should workRSDuck2020-04-26
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* fixup for aarch64 JITRSDuck2020-04-26
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* improve nop handling and proper behaviour for LDM^RSDuck2020-04-26
| | | | fixes dslinux
* integrate changes from ARM64 backend and moreRSDuck2020-04-26
| | | | | | | | | - better handle LDM/STM in reg alloc - unify Halted and IRQ in anticipation for branch inlining - literal optimisations can be disabled in gui - jit blocks follow simple returns - fix idle loop detection - break jit blocks on IRQ (fixes saving in Pokemon White)
* new block cache and much more...RSDuck2020-04-26
| | | | | | | | | - more reliable code invalidation detection - blocks aren't stopped at any branch, but are being followed if possible to get larger blocks - idle loop recognition - optimised literal loads, load/store cycle counting and loads/stores from constant addresses
* load register only if neededRSDuck2020-04-26
| | | | | - do thumb bl long merge in the first step - preparations for better branch jitting
* jit: thumb block transfer workingRSDuck2020-04-26
also pc and sp relative loads and some refactoring