| Commit message (Collapse) | Author | Age |
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* Reorganize namespaces
- Most types are now moved into the `melonDS` namespace
- Only good chance to do this for a while, since a big refactor is next
* Fix the build
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* gdbstub beginnings
* gdbstub: finish gdb impl things, next up is integration with melonDS
* holy fuck the gdbstub works
* gdb breakpoints work, but there's a mysterious crash on continue
* fix memory corruption that sometimes happened, and make resetting the console thru gdb work
* remove some gdb debug printing
* fix things in gdbstub
* separate option for enabling gdbstub
* add mode-dependent CPU registers
* C++ize the GDBstub code
* add gdbstub config in emu settings dialog
* make sure gdb is disabled when jit is enabled
* Remove unnecessary compiler flags, mark ARMJIT assembly code as no-execute-stack
This hardens the binary a little bit against common exploitation methods
* add option to wait for debugger attach on startup
* only insert GNU stack notes on linux
* disable gdbstub enable checkbox when jit is enabled
* fix non-linux incompatibilities
* enable gdbstub by default
* fix issues with gdbstub settings disable stuff
* format stuff
* update gdb test code
* Fix segfault when calling StubCallbacks->GetCPU()
C++ overrides are hard. Please I'm just a lowly C programmer.
* fix packet size not being sent correctly
Thanks to @GlowingUmbreon on Github for troubleshooting this
* fix select(2) calls (i should read docs more properly)
* fix GDB command sequencing/parsing issue (hopefully)
* [GDB] implement no-ack mode
* fix sending ack on handshake
* get lldb to work
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* Add Platform::Log and Platform::LogLevel
* Replace most printf calls with Platform::Log calls
* Move a brace down
* Move some log entries to one Log call
- Some implementations of Log may assume a full line
* Log the MAC address as LogLevel::Info
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* non-defined CPU modes are actually possible
* bit4 of all PSRs is forced to one (modes 00-0F aren't possible)
* modes 14/15/16 and 18/19/1A share a SPSR with modes 17 and 1B respectively (but they don't share the register banks)
* modes 10 and 1C/1D/1E don't have a SPSR (MRS returns the CPSR always)
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but it'll be a gross hack
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caches were off, so everything will be slow as shit.
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* make ARM9-only instructions fail on ARM7
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