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Diffstat (limited to 'src/NDS.cpp')
-rw-r--r--src/NDS.cpp220
1 files changed, 109 insertions, 111 deletions
diff --git a/src/NDS.cpp b/src/NDS.cpp
index 657241f..3d65482 100644
--- a/src/NDS.cpp
+++ b/src/NDS.cpp
@@ -33,6 +33,7 @@
#include "AREngine.h"
#include "Platform.h"
#include "ARMJIT.h"
+#include "ARMJIT_Memory.h"
#include "DSi.h"
#include "DSi_SPI_TSC.h"
@@ -94,17 +95,17 @@ u32 CPUStop;
u8 ARM9BIOS[0x1000];
u8 ARM7BIOS[0x4000];
-u8 MainRAM[0x1000000];
+u8* MainRAM;
u32 MainRAMMask;
-u8 SharedWRAM[0x8000];
+u8* SharedWRAM;
u8 WRAMCnt;
-u8* SWRAM_ARM9;
-u8* SWRAM_ARM7;
-u32 SWRAM_ARM9Mask;
-u32 SWRAM_ARM7Mask;
-u8 ARM7WRAM[0x10000];
+// putting them together so they're always next to each other
+MemRegion SWRAM_ARM9;
+MemRegion SWRAM_ARM7;
+
+u8* ARM7WRAM;
u16 ExMemCnt[2];
@@ -171,6 +172,10 @@ bool Init()
#ifdef JIT_ENABLED
ARMJIT::Init();
+#else
+ MainRAM = new u8[MainRAMSize];
+ ARM7WRAM = new u8[ARM7WRAMSize];
+ SharedWRAM = new u8[SharedWRAMSize];
#endif
DMAs[0] = new DMA(0, 0);
@@ -485,6 +490,10 @@ void Reset()
printf("ARM7 BIOS loaded\n");
fclose(f);
}
+
+#ifdef JIT_ENABLED
+ ARMJIT::Reset();
+#endif
if (ConsoleType == 1)
{
@@ -510,7 +519,7 @@ void Reset()
InitTimings();
- memset(MainRAM, 0, 0x1000000);
+ memset(MainRAM, 0, MainRAMMask + 1);
memset(SharedWRAM, 0, 0x8000);
memset(ARM7WRAM, 0, 0x10000);
@@ -587,10 +596,6 @@ void Reset()
}
AREngine::Reset();
-
-#ifdef JIT_ENABLED
- ARMJIT::Reset();
-#endif
}
void Stop()
@@ -705,7 +710,7 @@ bool DoSavestate(Savestate* file)
file->VarArray(MainRAM, 0x400000);
file->VarArray(SharedWRAM, 0x8000);
- file->VarArray(ARM7WRAM, 0x10000);
+ file->VarArray(ARM7WRAM, ARM7WRAMSize);
file->VarArray(ExMemCnt, 2*sizeof(u16));
file->VarArray(ROMSeed0, 2*8);
@@ -1128,43 +1133,40 @@ void MapSharedWRAM(u8 val)
if (val == WRAMCnt)
return;
+ ARMJIT_Memory::RemapSWRAM();
+
WRAMCnt = val;
switch (WRAMCnt & 0x3)
{
case 0:
- SWRAM_ARM9 = &SharedWRAM[0];
- SWRAM_ARM9Mask = 0x7FFF;
- SWRAM_ARM7 = NULL;
- SWRAM_ARM7Mask = 0;
+ SWRAM_ARM9.Mem = &SharedWRAM[0];
+ SWRAM_ARM9.Mask = 0x7FFF;
+ SWRAM_ARM7.Mem = NULL;
+ SWRAM_ARM7.Mask = 0;
break;
case 1:
- SWRAM_ARM9 = &SharedWRAM[0x4000];
- SWRAM_ARM9Mask = 0x3FFF;
- SWRAM_ARM7 = &SharedWRAM[0];
- SWRAM_ARM7Mask = 0x3FFF;
+ SWRAM_ARM9.Mem = &SharedWRAM[0x4000];
+ SWRAM_ARM9.Mask = 0x3FFF;
+ SWRAM_ARM7.Mem = &SharedWRAM[0];
+ SWRAM_ARM7.Mask = 0x3FFF;
break;
case 2:
- SWRAM_ARM9 = &SharedWRAM[0];
- SWRAM_ARM9Mask = 0x3FFF;
- SWRAM_ARM7 = &SharedWRAM[0x4000];
- SWRAM_ARM7Mask = 0x3FFF;
+ SWRAM_ARM9.Mem = &SharedWRAM[0];
+ SWRAM_ARM9.Mask = 0x3FFF;
+ SWRAM_ARM7.Mem = &SharedWRAM[0x4000];
+ SWRAM_ARM7.Mask = 0x3FFF;
break;
case 3:
- SWRAM_ARM9 = NULL;
- SWRAM_ARM9Mask = 0;
- SWRAM_ARM7 = &SharedWRAM[0];
- SWRAM_ARM7Mask = 0x7FFF;
+ SWRAM_ARM9.Mem = NULL;
+ SWRAM_ARM9.Mask = 0;
+ SWRAM_ARM7.Mem = &SharedWRAM[0];
+ SWRAM_ARM7.Mask = 0x7FFF;
break;
}
-
-#ifdef JIT_ENABLED
- ARMJIT::UpdateMemoryStatus9(0x3000000, 0x3000000 + 0x1000000);
- ARMJIT::UpdateMemoryStatus7(0x3000000, 0x3000000 + 0x1000000);
-#endif
}
@@ -1835,12 +1837,12 @@ u8 ARM9Read8(u32 addr)
switch (addr & 0xFF000000)
{
case 0x02000000:
- return *(u8*)&MainRAM[addr & MainRAMMask];
+ return *(u8*)&MainRAM[addr & (MainRAMSize - 1)];
case 0x03000000:
- if (SWRAM_ARM9)
+ if (SWRAM_ARM9.Mem)
{
- return *(u8*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask];
+ return *(u8*)&SWRAM_ARM9.Mem[addr & SWRAM_ARM9.Mask];
}
else
{
@@ -1900,12 +1902,12 @@ u16 ARM9Read16(u32 addr)
switch (addr & 0xFF000000)
{
case 0x02000000:
- return *(u16*)&MainRAM[addr & MainRAMMask];
+ return *(u16*)&MainRAM[addr & (MainRAMSize - 1)];
case 0x03000000:
- if (SWRAM_ARM9)
+ if (SWRAM_ARM9.Mem)
{
- return *(u16*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask];
+ return *(u16*)&SWRAM_ARM9.Mem[addr & SWRAM_ARM9.Mask];
}
else
{
@@ -1968,9 +1970,9 @@ u32 ARM9Read32(u32 addr)
return *(u32*)&MainRAM[addr & MainRAMMask];
case 0x03000000:
- if (SWRAM_ARM9)
+ if (SWRAM_ARM9.Mem)
{
- return *(u32*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask];
+ return *(u32*)&SWRAM_ARM9.Mem[addr & SWRAM_ARM9.Mask];
}
else
{
@@ -2026,7 +2028,7 @@ void ARM9Write8(u32 addr, u8 val)
{
case 0x02000000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateMainRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
#endif
*(u8*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
@@ -2035,12 +2037,12 @@ void ARM9Write8(u32 addr, u8 val)
return;
case 0x03000000:
- if (SWRAM_ARM9)
+ if (SWRAM_ARM9.Mem)
{
#ifdef JIT_ENABLED
- ARMJIT::InvalidateSWRAM9IfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_SWRAM>(addr);
#endif
- *(u8*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask] = val;
+ *(u8*)&SWRAM_ARM9.Mem[addr & SWRAM_ARM9.Mask] = val;
}
return;
@@ -2085,7 +2087,7 @@ void ARM9Write16(u32 addr, u16 val)
{
case 0x02000000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateMainRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
#endif
*(u16*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
@@ -2094,12 +2096,12 @@ void ARM9Write16(u32 addr, u16 val)
return;
case 0x03000000:
- if (SWRAM_ARM9)
+ if (SWRAM_ARM9.Mem)
{
#ifdef JIT_ENABLED
- ARMJIT::InvalidateSWRAM9IfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_SWRAM>(addr);
#endif
- *(u16*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask] = val;
+ *(u16*)&SWRAM_ARM9.Mem[addr & SWRAM_ARM9.Mask] = val;
}
return;
@@ -2113,18 +2115,16 @@ void ARM9Write16(u32 addr, u16 val)
return;
case 0x06000000:
+#ifdef JIT_ENABLED
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(addr);
+#endif
switch (addr & 0x00E00000)
{
case 0x00000000: GPU::WriteVRAM_ABG<u16>(addr, val); return;
case 0x00200000: GPU::WriteVRAM_BBG<u16>(addr, val); return;
case 0x00400000: GPU::WriteVRAM_AOBJ<u16>(addr, val); return;
case 0x00600000: GPU::WriteVRAM_BOBJ<u16>(addr, val); return;
- default:
-#ifdef JIT_ENABLED
- ARMJIT::InvalidateLCDCIfNecessary(addr);
-#endif
- GPU::WriteVRAM_LCDC<u16>(addr, val);
- return;
+ default: GPU::WriteVRAM_LCDC<u16>(addr, val); return;
}
case 0x07000000:
@@ -2165,7 +2165,7 @@ void ARM9Write32(u32 addr, u32 val)
{
case 0x02000000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateMainRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
#endif
*(u32*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
@@ -2174,12 +2174,12 @@ void ARM9Write32(u32 addr, u32 val)
return ;
case 0x03000000:
- if (SWRAM_ARM9)
+ if (SWRAM_ARM9.Mem)
{
#ifdef JIT_ENABLED
- ARMJIT::InvalidateSWRAM9IfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_SWRAM>(addr);
#endif
- *(u32*)&SWRAM_ARM9[addr & SWRAM_ARM9Mask] = val;
+ *(u32*)&SWRAM_ARM9.Mem[addr & SWRAM_ARM9.Mask] = val;
}
return;
@@ -2193,18 +2193,16 @@ void ARM9Write32(u32 addr, u32 val)
return;
case 0x06000000:
+#ifdef JIT_ENABLED
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(addr);
+#endif
switch (addr & 0x00E00000)
{
case 0x00000000: GPU::WriteVRAM_ABG<u32>(addr, val); return;
case 0x00200000: GPU::WriteVRAM_BBG<u32>(addr, val); return;
case 0x00400000: GPU::WriteVRAM_AOBJ<u32>(addr, val); return;
case 0x00600000: GPU::WriteVRAM_BOBJ<u32>(addr, val); return;
- default:
-#ifdef JIT_ENABLED
- ARMJIT::InvalidateLCDCIfNecessary(addr);
-#endif
- GPU::WriteVRAM_LCDC<u32>(addr, val);
- return;
+ default: GPU::WriteVRAM_LCDC<u32>(addr, val); return;
}
case 0x07000000:
@@ -2250,10 +2248,10 @@ bool ARM9GetMemRegion(u32 addr, bool write, MemRegion* region)
return true;
case 0x03000000:
- if (SWRAM_ARM9)
+ if (SWRAM_ARM9.Mem)
{
- region->Mem = SWRAM_ARM9;
- region->Mask = SWRAM_ARM9Mask;
+ region->Mem = SWRAM_ARM9.Mem;
+ region->Mask = SWRAM_ARM9.Mask;
return true;
}
break;
@@ -2292,17 +2290,17 @@ u8 ARM7Read8(u32 addr)
return *(u8*)&MainRAM[addr & MainRAMMask];
case 0x03000000:
- if (SWRAM_ARM7)
+ if (SWRAM_ARM7.Mem)
{
- return *(u8*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask];
+ return *(u8*)&SWRAM_ARM7.Mem[addr & SWRAM_ARM7.Mask];
}
else
{
- return *(u8*)&ARM7WRAM[addr & 0xFFFF];
+ return *(u8*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)];
}
case 0x03800000:
- return *(u8*)&ARM7WRAM[addr & 0xFFFF];
+ return *(u8*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)];
case 0x04000000:
return ARM7IORead8(addr);
@@ -2352,17 +2350,17 @@ u16 ARM7Read16(u32 addr)
return *(u16*)&MainRAM[addr & MainRAMMask];
case 0x03000000:
- if (SWRAM_ARM7)
+ if (SWRAM_ARM7.Mem)
{
- return *(u16*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask];
+ return *(u16*)&SWRAM_ARM7.Mem[addr & SWRAM_ARM7.Mask];
}
else
{
- return *(u16*)&ARM7WRAM[addr & 0xFFFF];
+ return *(u16*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)];
}
case 0x03800000:
- return *(u16*)&ARM7WRAM[addr & 0xFFFF];
+ return *(u16*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)];
case 0x04000000:
return ARM7IORead16(addr);
@@ -2419,17 +2417,17 @@ u32 ARM7Read32(u32 addr)
return *(u32*)&MainRAM[addr & MainRAMMask];
case 0x03000000:
- if (SWRAM_ARM7)
+ if (SWRAM_ARM7.Mem)
{
- return *(u32*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask];
+ return *(u32*)&SWRAM_ARM7.Mem[addr & SWRAM_ARM7.Mask];
}
else
{
- return *(u32*)&ARM7WRAM[addr & 0xFFFF];
+ return *(u32*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)];
}
case 0x03800000:
- return *(u32*)&ARM7WRAM[addr & 0xFFFF];
+ return *(u32*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)];
case 0x04000000:
return ARM7IORead32(addr);
@@ -2474,7 +2472,7 @@ void ARM7Write8(u32 addr, u8 val)
case 0x02000000:
case 0x02800000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateMainRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
#endif
*(u8*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
@@ -2483,28 +2481,28 @@ void ARM7Write8(u32 addr, u8 val)
return;
case 0x03000000:
- if (SWRAM_ARM7)
+ if (SWRAM_ARM7.Mem)
{
#ifdef JIT_ENABLED
- ARMJIT::InvalidateSWRAM7IfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_SWRAM>(addr);
#endif
- *(u8*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask] = val;
+ *(u8*)&SWRAM_ARM7.Mem[addr & SWRAM_ARM7.Mask] = val;
return;
}
else
{
#ifdef JIT_ENABLED
- ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
#endif
- *(u8*)&ARM7WRAM[addr & 0xFFFF] = val;
+ *(u8*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
return;
}
case 0x03800000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
#endif
- *(u8*)&ARM7WRAM[addr & 0xFFFF] = val;
+ *(u8*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
return;
case 0x04000000:
@@ -2514,7 +2512,7 @@ void ARM7Write8(u32 addr, u8 val)
case 0x06000000:
case 0x06800000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateARM7WVRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(addr);
#endif
GPU::WriteVRAM_ARM7<u8>(addr, val);
return;
@@ -2551,7 +2549,7 @@ void ARM7Write16(u32 addr, u16 val)
case 0x02000000:
case 0x02800000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateMainRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
#endif
*(u16*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
@@ -2560,28 +2558,28 @@ void ARM7Write16(u32 addr, u16 val)
return;
case 0x03000000:
- if (SWRAM_ARM7)
+ if (SWRAM_ARM7.Mem)
{
#ifdef JIT_ENABLED
- ARMJIT::InvalidateSWRAM7IfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_SWRAM>(addr);
#endif
- *(u16*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask] = val;
+ *(u16*)&SWRAM_ARM7.Mem[addr & SWRAM_ARM7.Mask] = val;
return;
}
else
{
#ifdef JIT_ENABLED
- ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
#endif
- *(u16*)&ARM7WRAM[addr & 0xFFFF] = val;
+ *(u16*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
return;
}
case 0x03800000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
#endif
- *(u16*)&ARM7WRAM[addr & 0xFFFF] = val;
+ *(u16*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
return;
case 0x04000000:
@@ -2599,7 +2597,7 @@ void ARM7Write16(u32 addr, u16 val)
case 0x06000000:
case 0x06800000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateARM7WVRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(addr);
#endif
GPU::WriteVRAM_ARM7<u16>(addr, val);
return;
@@ -2638,7 +2636,7 @@ void ARM7Write32(u32 addr, u32 val)
case 0x02000000:
case 0x02800000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateMainRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
#endif
*(u32*)&MainRAM[addr & MainRAMMask] = val;
#ifdef JIT_ENABLED
@@ -2647,28 +2645,28 @@ void ARM7Write32(u32 addr, u32 val)
return;
case 0x03000000:
- if (SWRAM_ARM7)
+ if (SWRAM_ARM7.Mem)
{
#ifdef JIT_ENABLED
- ARMJIT::InvalidateSWRAM7IfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_SWRAM>(addr);
#endif
- *(u32*)&SWRAM_ARM7[addr & SWRAM_ARM7Mask] = val;
+ *(u32*)&SWRAM_ARM7.Mem[addr & SWRAM_ARM7.Mask] = val;
return;
}
else
{
#ifdef JIT_ENABLED
- ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
#endif
- *(u32*)&ARM7WRAM[addr & 0xFFFF] = val;
+ *(u32*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
return;
}
case 0x03800000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateARM7WRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
#endif
- *(u32*)&ARM7WRAM[addr & 0xFFFF] = val;
+ *(u32*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
return;
case 0x04000000:
@@ -2687,7 +2685,7 @@ void ARM7Write32(u32 addr, u32 val)
case 0x06000000:
case 0x06800000:
#ifdef JIT_ENABLED
- ARMJIT::InvalidateARM7WVRAMIfNecessary(addr);
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(addr);
#endif
GPU::WriteVRAM_ARM7<u32>(addr, val);
return;
@@ -2736,17 +2734,17 @@ bool ARM7GetMemRegion(u32 addr, bool write, MemRegion* region)
// then access all the WRAM as one contiguous block starting at 0x037F8000
// this case needs a bit of a hack to cover
// it's not really worth bothering anyway
- if (!SWRAM_ARM7)
+ if (!SWRAM_ARM7.Mem)
{
region->Mem = ARM7WRAM;
- region->Mask = 0xFFFF;
+ region->Mask = ARM7WRAMSize-1;
return true;
}
break;
case 0x03800000:
region->Mem = ARM7WRAM;
- region->Mask = 0xFFFF;
+ region->Mask = ARM7WRAMSize-1;
return true;
}