diff options
Diffstat (limited to 'src/NDS.cpp')
| -rw-r--r-- | src/NDS.cpp | 274 |
1 files changed, 226 insertions, 48 deletions
diff --git a/src/NDS.cpp b/src/NDS.cpp index ceeeb79..47f96c9 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -22,6 +22,7 @@ #include "NDS.h" #include "ARM.h" #include "NDSCart.h" +#include "GBACart.h" #include "DMA.h" #include "FIFO.h" #include "GPU.h" @@ -169,6 +170,7 @@ bool Init() IPCFIFO7 = new FIFO<u32>(16); if (!NDSCart::Init()) return false; + if (!GBACart::Init()) return false; if (!GPU::Init()) return false; if (!SPU::Init()) return false; if (!SPI::Init()) return false; @@ -190,6 +192,7 @@ void DeInit() delete IPCFIFO7; NDSCart::DeInit(); + GBACart::DeInit(); GPU::DeInit(); SPU::DeInit(); SPI::DeInit(); @@ -491,6 +494,7 @@ void Reset() RCnt = 0; NDSCart::Reset(); + GBACart::Reset(); GPU::Reset(); SPU::Reset(); SPI::Reset(); @@ -692,6 +696,7 @@ bool DoSavestate(Savestate* file) ARM7->DoSavestate(file); NDSCart::DoSavestate(file); + GBACart::DoSavestate(file); GPU::DoSavestate(file); SPU::DoSavestate(file); SPI::DoSavestate(file); @@ -720,6 +725,19 @@ bool LoadROM(const char* path, const char* sram, bool direct) } } +bool LoadGBAROM(const char* path, const char* sram) +{ + if (GBACart::LoadROM(path, sram)) + { + return true; + } + else + { + printf("Failed to load ROM %s\n", path); + return false; + } +} + void LoadBIOS() { Reset(); @@ -1610,16 +1628,20 @@ u8 ARM9Read8(u32 addr) case 0x08000000: case 0x09000000: - if (ExMemCnt[0] & (1<<7)) return 0xFF; // TODO: proper open bus - //return *(u8*)&NDSCart::CartROM[addr & (NDSCart::CartROMSize-1)]; - //printf("GBA read8 %08X\n", addr); - // TODO!!! - return 0xFF; + if (ExMemCnt[0] & (1<<7)) return 0x00; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return *(u8*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)]; + } + return 0xFF; // TODO: proper open bus case 0x0A000000: - if (ExMemCnt[0] & (1<<7)) return 0xFF; // TODO: proper open bus - // TODO!!! - return 0xFF; + if (ExMemCnt[0] & (1<<7)) return 0x00; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return GBACart_SRAM::Read8(addr & (GBACart_SRAM::SRAMLength-1)); + } + return 0xFF; // TODO: proper open bus } printf("unknown arm9 read8 %08X\n", addr); @@ -1671,16 +1693,20 @@ u16 ARM9Read16(u32 addr) case 0x08000000: case 0x09000000: - if (ExMemCnt[0] & (1<<7)) return 0xFFFF; // TODO: proper open bus - //return *(u8*)&NDSCart::CartROM[addr & (NDSCart::CartROMSize-1)]; - //printf("GBA read8 %08X\n", addr); - // TODO!!! - return 0xFFFF; + if (ExMemCnt[0] & (1<<7)) return 0x0000; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return *(u16*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)]; + } + return 0xFFFF; // TODO: proper open bus case 0x0A000000: - if (ExMemCnt[0] & (1<<7)) return 0xFFFF; // TODO: proper open bus - // TODO!!! - return 0xFFFF; + if (ExMemCnt[0] & (1<<7)) return 0x0000; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return GBACart_SRAM::Read16(addr & (GBACart_SRAM::SRAMLength-1)); + } + return 0xFFFF; // TODO: proper open bus } //printf("unknown arm9 read16 %08X %08X\n", addr, ARM9->R[15]); @@ -1732,16 +1758,20 @@ u32 ARM9Read32(u32 addr) case 0x08000000: case 0x09000000: - if (ExMemCnt[0] & (1<<7)) return 0xFFFFFFFF; // TODO: proper open bus - //return *(u8*)&NDSCart::CartROM[addr & (NDSCart::CartROMSize-1)]; - //printf("GBA read8 %08X\n", addr); - // TODO!!! - return 0xFFFFFFFF; + if (ExMemCnt[0] & (1<<7)) return 0x00000000; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return *(u32*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)]; + } + return 0xFFFFFFFF; // TODO: proper open bus case 0x0A000000: - if (ExMemCnt[0] & (1<<7)) return 0xFFFFFFFF; // TODO: proper open bus - // TODO!!! - return 0xFFFFFFFF; + if (ExMemCnt[0] & (1<<7)) return 0x00000000; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return GBACart_SRAM::Read32(addr & (GBACart_SRAM::SRAMLength-1)); + } + return 0xFFFFFFFF; // TODO: proper open bus } printf("unknown arm9 read32 %08X | %08X %08X\n", addr, ARM9->R[15], ARM9->R[12]); @@ -1772,6 +1802,27 @@ void ARM9Write8(u32 addr, u8 val) case 0x07000000: // checkme return; + + case 0x08000000: + case 0x09000000: + if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + if ((addr & 0x00FFFFFF) >= 0xC4 && (addr & 0x00FFFFFF) <= 0xC9) + { + GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val); + return; + } + } + break; + + case 0x0A000000: + if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + GBACart_SRAM::Write8(addr & (GBACart_SRAM::SRAMLength-1), val); + } + return; } printf("unknown arm9 write8 %08X %02X\n", addr, val); @@ -1815,6 +1866,29 @@ void ARM9Write16(u32 addr, u16 val) if (!(PowerControl9 & ((addr & 0x400) ? (1<<9) : (1<<1)))) return; *(u16*)&GPU::OAM[addr & 0x7FF] = val; return; + + case 0x08000000: + case 0x09000000: + if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + // Note: the lower bound is adjusted such that a write starting + // there will hit the first byte of the GPIO region. + if ((addr & 0x00FFFFFF) >= 0xC3 && (addr & 0x00FFFFFF) <= 0xC9) + { + GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val); + return; + } + } + break; + + case 0x0A000000: + if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + GBACart_SRAM::Write16(addr & (GBACart_SRAM::SRAMLength-1), val); + } + return; } //printf("unknown arm9 write16 %08X %04X\n", addr, val); @@ -1858,6 +1932,30 @@ void ARM9Write32(u32 addr, u32 val) if (!(PowerControl9 & ((addr & 0x400) ? (1<<9) : (1<<1)))) return; *(u32*)&GPU::OAM[addr & 0x7FF] = val; return; + + case 0x08000000: + case 0x09000000: + if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + // Note: the lower bound is adjusted such that a write starting + // there will hit the first byte of the GPIO region. + if ((addr & 0x00FFFFFF) >= 0xC1 && (addr & 0x00FFFFFF) <= 0xC9) + { + GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val & 0xFF); + GBACart::WriteGPIO((addr + 2) & (GBACart::CartROMSize-1), (val >> 16) & 0xFF); + return; + } + } + break; + + case 0x0A000000: + if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + GBACart_SRAM::Write32(addr & (GBACart_SRAM::SRAMLength-1), val); + } + return; } printf("unknown arm9 write32 %08X %08X | %08X\n", addr, val, ARM9->R[15]); @@ -1935,16 +2033,20 @@ u8 ARM7Read8(u32 addr) case 0x08000000: case 0x09000000: - if (!(ExMemCnt[0] & (1<<7))) return 0xFF; // TODO: proper open bus - //return *(u8*)&NDSCart::CartROM[addr & (NDSCart::CartROMSize-1)]; - //printf("GBA read8 %08X\n", addr); - // TODO!!! - return 0xFF; + if (!(ExMemCnt[0] & (1<<7))) return 0x00; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return *(u8*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)]; + } + return 0xFF; // TODO: proper open bus case 0x0A000000: - if (!(ExMemCnt[0] & (1<<7))) return 0xFF; // TODO: proper open bus - // TODO!!! - return 0xFF; + if (!(ExMemCnt[0] & (1<<7))) return 0x00; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return GBACart_SRAM::Read8(addr & (GBACart_SRAM::SRAMLength-1)); + } + return 0xFF; // TODO: proper open bus } printf("unknown arm7 read8 %08X %08X %08X/%08X\n", addr, ARM7->R[15], ARM7->R[0], ARM7->R[1]); @@ -1998,16 +2100,20 @@ u16 ARM7Read16(u32 addr) case 0x08000000: case 0x09000000: - if (!(ExMemCnt[0] & (1<<7))) return 0xFFFF; // TODO: proper open bus - //return *(u8*)&NDSCart::CartROM[addr & (NDSCart::CartROMSize-1)]; - //printf("GBA read8 %08X\n", addr); - // TODO!!! - return 0xFFFF; + if (!(ExMemCnt[0] & (1<<7))) return 0x0000; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return *(u16*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)]; + } + return 0xFFFF; // TODO: proper open bus case 0x0A000000: - if (!(ExMemCnt[0] & (1<<7))) return 0xFFFF; // TODO: proper open bus - // TODO!!! - return 0xFFFF; + if (!(ExMemCnt[0] & (1<<7))) return 0x0000; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return GBACart_SRAM::Read16(addr & (GBACart_SRAM::SRAMLength-1)); + } + return 0xFFFF; // TODO: proper open bus } printf("unknown arm7 read16 %08X %08X\n", addr, ARM7->R[15]); @@ -2061,16 +2167,20 @@ u32 ARM7Read32(u32 addr) case 0x08000000: case 0x09000000: - if (!(ExMemCnt[0] & (1<<7))) return 0xFFFFFFFF; // TODO: proper open bus - //return *(u8*)&NDSCart::CartROM[addr & (NDSCart::CartROMSize-1)]; - //printf("GBA read8 %08X\n", addr); - // TODO!!! - return 0xFFFFFFFF; + if (!(ExMemCnt[0] & (1<<7))) return 0x00000000; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return *(u32*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)]; + } + return 0xFFFFFFFF; // TODO: proper open bus case 0x0A000000: - if (!(ExMemCnt[0] & (1<<7))) return 0xFFFFFFFF; // TODO: proper open bus - // TODO!!! - return 0xFFFFFFFF; + if (!(ExMemCnt[0] & (1<<7))) return 0x00000000; // deselected CPU is 00h-filled + if (GBACart::CartInserted) + { + return GBACart_SRAM::Read32(addr & (GBACart_SRAM::SRAMLength-1)); + } + return 0xFFFFFFFF; // TODO: proper open bus } printf("unknown arm7 read32 %08X | %08X\n", addr, ARM7->R[15]); @@ -2110,6 +2220,27 @@ void ARM7Write8(u32 addr, u8 val) case 0x06800000: GPU::WriteVRAM_ARM7<u8>(addr, val); return; + + case 0x08000000: + case 0x09000000: + if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + if ((addr & 0x00FFFFFF) >= 0xC4 && (addr & 0x00FFFFFF) <= 0xC9) + { + GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val); + return; + } + } + break; + + case 0x0A000000: + if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + GBACart_SRAM::Write8(addr & (GBACart_SRAM::SRAMLength-1), val); + } + return; } printf("unknown arm7 write8 %08X %02X @ %08X\n", addr, val, ARM7->R[15]); @@ -2156,6 +2287,29 @@ void ARM7Write16(u32 addr, u16 val) case 0x06800000: GPU::WriteVRAM_ARM7<u16>(addr, val); return; + + case 0x08000000: + case 0x09000000: + if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + // Note: the lower bound is adjusted such that a write starting + // there will hit the first byte of the GPIO region. + if ((addr & 0x00FFFFFF) >= 0xC3 && (addr & 0x00FFFFFF) <= 0xC9) + { + GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val); + return; + } + } + break; + + case 0x0A000000: + if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + GBACart_SRAM::Write16(addr & (GBACart_SRAM::SRAMLength-1), val); + } + return; } //printf("unknown arm7 write16 %08X %04X @ %08X\n", addr, val, ARM7->R[15]); @@ -2203,6 +2357,30 @@ void ARM7Write32(u32 addr, u32 val) case 0x06800000: GPU::WriteVRAM_ARM7<u32>(addr, val); return; + + case 0x08000000: + case 0x09000000: + if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + // Note: the lower bound is adjusted such that a write starting + // there will hit the first byte of the GPIO region. + if ((addr & 0x00FFFFFF) >= 0xC1 && (addr & 0x00FFFFFF) <= 0xC9) + { + GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val & 0xFF); + GBACart::WriteGPIO((addr + 2) & (GBACart::CartROMSize-1), (val >> 16) & 0xFF); + return; + } + } + break; + + case 0x0A000000: + if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write + if (GBACart::CartInserted) + { + GBACart_SRAM::Write32(addr & (GBACart_SRAM::SRAMLength-1), val); + } + return; } //printf("unknown arm7 write32 %08X %08X @ %08X\n", addr, val, ARM7->R[15]); |