aboutsummaryrefslogtreecommitdiff
path: root/src/DSi.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'src/DSi.cpp')
-rw-r--r--src/DSi.cpp408
1 files changed, 316 insertions, 92 deletions
diff --git a/src/DSi.cpp b/src/DSi.cpp
index 9267f14..cfce0ac 100644
--- a/src/DSi.cpp
+++ b/src/DSi.cpp
@@ -1,5 +1,5 @@
/*
- Copyright 2016-2021 Arisotura
+ Copyright 2016-2022 melonDS team
This file is part of melonDS.
@@ -47,8 +47,6 @@
namespace DSi
{
-u32 BootAddr[2];
-
u16 SCFG_BIOS;
u16 SCFG_Clock9;
u16 SCFG_Clock7;
@@ -79,16 +77,12 @@ DSi_NDMA* NDMAs[8];
DSi_SDHost* SDMMC;
DSi_SDHost* SDIO;
-FILE* SDMMCFile = nullptr;
-
u64 ConsoleID;
u8 eMMC_CID[16];
-u8 ITCMInit[0x8000];
-u8 ARM7Init[0x3C00];
-
void Set_SCFG_Clock9(u16 val);
+void Set_SCFG_MC(u32 val);
bool Init()
@@ -100,6 +94,7 @@ bool Init()
#endif
if (!DSi_I2C::Init()) return false;
+ if (!DSi_CamModule::Init()) return false;
if (!DSi_AES::Init()) return false;
if (!DSi_DSP::Init()) return false;
@@ -127,6 +122,7 @@ void DeInit()
#endif
DSi_I2C::DeInit();
+ DSi_CamModule::DeInit();
DSi_AES::DeInit();
DSi_DSP::DeInit();
@@ -134,8 +130,6 @@ void DeInit()
delete SDMMC;
delete SDIO;
-
- CloseDSiNAND();
}
void Reset()
@@ -144,27 +138,31 @@ void Reset()
//NDS::ARM9->CP15Write(0x911, 0x00000020);
//NDS::ARM9->CP15Write(0x100, NDS::ARM9->CP15Read(0x100) | 0x00050000);
- NDS::ARM9->JumpTo(BootAddr[0]);
- NDS::ARM7->JumpTo(BootAddr[1]);
+ NDS::MapSharedWRAM(3);
NDMACnt[0] = 0; NDMACnt[1] = 0;
for (int i = 0; i < 8; i++) NDMAs[i]->Reset();
- memcpy(NDS::ARM9->ITCM, ITCMInit, 0x8000);
-
DSi_I2C::Reset();
- DSi_AES::Reset();
+ DSi_CamModule::Reset();
DSi_DSP::Reset();
+ SDMMC->CloseHandles();
+ SDIO->CloseHandles();
+
+ LoadNAND();
+
SDMMC->Reset();
SDIO->Reset();
+ DSi_AES::Reset();
+
SCFG_BIOS = 0x0101; // TODO: should be zero when booting from BIOS
SCFG_Clock9 = 0x0187; // CHECKME
SCFG_Clock7 = 0x0187;
SCFG_EXT[0] = 0x8307F100;
SCFG_EXT[1] = 0x93FFFB06;
- SCFG_MC = 0x0010;//0x0011;
+ SCFG_MC = 0x0010 | (~((u32)NDSCart::CartInserted)&1);//0x0011;
SCFG_RST = 0;
DSi_DSP::SetRstLine(false);
@@ -172,22 +170,98 @@ void Reset()
// LCD init flag
GPU::DispStat[0] |= (1<<6);
GPU::DispStat[1] |= (1<<6);
+}
- NDS::MapSharedWRAM(3);
+void Stop()
+{
+ DSi_CamModule::Stop();
+}
- for (u32 i = 0; i < 0x3C00; i+=4)
- ARM7Write32(0x03FFC400+i, *(u32*)&ARM7Init[i]);
+void DoSavestate(Savestate* file)
+{
+ file->Section("DSIG");
- u32 eaddr = 0x03FFE6E4;
- ARM7Write32(eaddr+0x00, *(u32*)&eMMC_CID[0]);
- ARM7Write32(eaddr+0x04, *(u32*)&eMMC_CID[4]);
- ARM7Write32(eaddr+0x08, *(u32*)&eMMC_CID[8]);
- ARM7Write32(eaddr+0x0C, *(u32*)&eMMC_CID[12]);
- ARM7Write16(eaddr+0x2C, 0x0001);
- ARM7Write16(eaddr+0x2E, 0x0001);
- ARM7Write16(eaddr+0x3C, 0x0100);
- ARM7Write16(eaddr+0x3E, 0x40E0);
- ARM7Write16(eaddr+0x42, 0x0001);
+ file->Var16(&SCFG_BIOS);
+ file->Var16(&SCFG_Clock9);
+ file->Var16(&SCFG_Clock7);
+ file->VarArray(&SCFG_EXT[0], sizeof(u32)*2);
+ file->Var32(&SCFG_MC);
+ file->Var16(&SCFG_RST);
+
+ //file->VarArray(ARM9iBIOS, 0x10000);
+ //file->VarArray(ARM7iBIOS, 0x10000);
+
+ if (file->Saving)
+ {
+ file->VarArray(&MBK[0][0], sizeof(u32)*8);
+ file->VarArray(&MBK[1][5], sizeof(u32)*3);
+ file->Var32(&MBK[0][8]);
+ }
+ else
+ {
+ Set_SCFG_Clock9(SCFG_Clock9);
+ Set_SCFG_MC(SCFG_MC);
+ DSi_DSP::SetRstLine(SCFG_RST & 0x0001);
+
+ MBK[0][8] = 0;
+ MBK[1][8] = 0;
+
+ u32 mbk[12];
+ file->VarArray(&mbk, sizeof(u32)*12);
+
+ MapNWRAM_A(0, mbk[0] & 0xFF);
+ MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
+ MapNWRAM_A(2, (mbk[0] >> 16) & 0xFF);
+ MapNWRAM_A(3, mbk[0] >> 24);
+
+ MapNWRAM_B(0, mbk[1] & 0xFF);
+ MapNWRAM_B(1, (mbk[1] >> 8) & 0xFF);
+ MapNWRAM_B(2, (mbk[1] >> 16) & 0xFF);
+ MapNWRAM_B(3, mbk[1] >> 24);
+ MapNWRAM_B(4, mbk[2] & 0xFF);
+ MapNWRAM_B(5, (mbk[2] >> 8) & 0xFF);
+ MapNWRAM_B(6, (mbk[2] >> 16) & 0xFF);
+ MapNWRAM_B(7, mbk[2] >> 24);
+
+ MapNWRAM_C(0, mbk[3] & 0xFF);
+ MapNWRAM_C(1, (mbk[3] >> 8) & 0xFF);
+ MapNWRAM_C(2, (mbk[3] >> 16) & 0xFF);
+ MapNWRAM_C(3, mbk[3] >> 24);
+ MapNWRAM_C(4, mbk[4] & 0xFF);
+ MapNWRAM_C(5, (mbk[4] >> 8) & 0xFF);
+ MapNWRAM_C(6, (mbk[4] >> 16) & 0xFF);
+ MapNWRAM_C(7, mbk[4] >> 24);
+
+ MapNWRAMRange(0, 0, mbk[5]);
+ MapNWRAMRange(0, 1, mbk[6]);
+ MapNWRAMRange(0, 2, mbk[7]);
+
+ MapNWRAMRange(1, 0, mbk[8]);
+ MapNWRAMRange(1, 1, mbk[9]);
+ MapNWRAMRange(1, 2, mbk[10]);
+
+ mbk[11] &= 0x00FFFF0F;
+ MBK[0][8] = mbk[11];
+ MBK[1][8] = mbk[11];
+ }
+
+ for (int i = 0; i < 8; i++)
+ NDMAs[i]->DoSavestate(file);
+
+ DSi_AES::DoSavestate(file);
+ DSi_CamModule::DoSavestate(file);
+ DSi_DSP::DoSavestate(file);
+ DSi_I2C::DoSavestate(file);
+ SDMMC->DoSavestate(file);
+ SDIO->DoSavestate(file);
+}
+
+void SetCartInserted(bool inserted)
+{
+ if (inserted)
+ SCFG_MC &= ~1;
+ else
+ SCFG_MC |= 1;
}
void DecryptModcryptArea(u32 offset, u32 size, u8* iv)
@@ -445,7 +519,7 @@ void SetupDirectBoot()
ARM9Write32(0x02FFE000+i, tmp);
}
- if (DSi_NAND::Init(SDMMCFile, &DSi::ARM7iBIOS[0x8308]))
+ if (DSi_NAND::Init(&DSi::ARM7iBIOS[0x8308]))
{
u8 userdata[0x1B0];
DSi_NAND::ReadUserData(userdata);
@@ -544,21 +618,22 @@ void SoftReset()
NDS::ARM9->CP15Reset();
- memcpy(NDS::ARM9->ITCM, ITCMInit, 0x8000);
+ NDS::MapSharedWRAM(3);
- DSi_AES::Reset();
// TODO: does the DSP get reset? NWRAM doesn't, so I'm assuming no
// *HOWEVER*, the bootrom (which does get rerun) does remap NWRAM, and thus
// the DSP most likely gets reset
DSi_DSP::Reset();
+ SDMMC->CloseHandles();
+ SDIO->CloseHandles();
+
LoadNAND();
SDMMC->Reset();
SDIO->Reset();
- NDS::ARM9->JumpTo(BootAddr[0]);
- NDS::ARM7->JumpTo(BootAddr[1]);
+ DSi_AES::Reset();
SCFG_BIOS = 0x0101; // TODO: should be zero when booting from BIOS
SCFG_Clock9 = 0x0187; // CHECKME
@@ -574,22 +649,6 @@ void SoftReset()
// LCD init flag
GPU::DispStat[0] |= (1<<6);
GPU::DispStat[1] |= (1<<6);
-
- NDS::MapSharedWRAM(3);
-
- for (u32 i = 0; i < 0x3C00; i+=4)
- ARM7Write32(0x03FFC400+i, *(u32*)&ARM7Init[i]);
-
- u32 eaddr = 0x03FFE6E4;
- ARM7Write32(eaddr+0x00, *(u32*)&eMMC_CID[0]);
- ARM7Write32(eaddr+0x04, *(u32*)&eMMC_CID[4]);
- ARM7Write32(eaddr+0x08, *(u32*)&eMMC_CID[8]);
- ARM7Write32(eaddr+0x0C, *(u32*)&eMMC_CID[12]);
- ARM7Write16(eaddr+0x2C, 0x0001);
- ARM7Write16(eaddr+0x2E, 0x0001);
- ARM7Write16(eaddr+0x3C, 0x0100);
- ARM7Write16(eaddr+0x3E, 0x40E0);
- ARM7Write16(eaddr+0x42, 0x0001);
}
bool LoadBIOS()
@@ -650,12 +709,14 @@ bool LoadNAND()
{
printf("Loading DSi NAND\n");
- if (!DSi_NAND::Init(SDMMCFile, &DSi::ARM7iBIOS[0x8308]))
+ if (!DSi_NAND::Init(&DSi::ARM7iBIOS[0x8308]))
{
printf("Failed to load DSi NAND\n");
return false;
}
+ FILE* nand = DSi_NAND::GetFile();
+
// Make sure NWRAM is accessible.
// The Bits are set to the startup values in Reset() and we might
// still have them on default (0) or some bits cleared by the previous
@@ -676,8 +737,8 @@ bool LoadNAND()
memset(NWRAMMask, 0, sizeof(NWRAMMask));
u32 bootparams[8];
- fseek(SDMMCFile, 0x220, SEEK_SET);
- fread(bootparams, 4, 8, SDMMCFile);
+ fseek(nand, 0x220, SEEK_SET);
+ fread(bootparams, 4, 8, nand);
printf("ARM9: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n",
bootparams[0], bootparams[1], bootparams[2], bootparams[3]);
@@ -690,8 +751,8 @@ bool LoadNAND()
MBK[1][8] = 0;
u32 mbk[12];
- fseek(SDMMCFile, 0x380, SEEK_SET);
- fread(mbk, 4, 12, SDMMCFile);
+ fseek(nand, 0x380, SEEK_SET);
+ fread(mbk, 4, 12, nand);
MapNWRAM_A(0, mbk[0] & 0xFF);
MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
@@ -745,12 +806,12 @@ bool LoadNAND()
AES_init_ctx_iv(&ctx, boot2key, boot2iv);
- fseek(SDMMCFile, bootparams[0], SEEK_SET);
+ fseek(nand, bootparams[0], SEEK_SET);
dstaddr = bootparams[2];
for (u32 i = 0; i < bootparams[3]; i += 16)
{
u8 data[16];
- fread(data, 16, 1, SDMMCFile);
+ fread(data, 16, 1, nand);
for (int j = 0; j < 16; j++) tmp[j] = data[15-j];
AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
@@ -770,12 +831,12 @@ bool LoadNAND()
AES_init_ctx_iv(&ctx, boot2key, boot2iv);
- fseek(SDMMCFile, bootparams[4], SEEK_SET);
+ fseek(nand, bootparams[4], SEEK_SET);
dstaddr = bootparams[6];
for (u32 i = 0; i < bootparams[7]; i += 16)
{
u8 data[16];
- fread(data, 16, 1, SDMMCFile);
+ fread(data, 16, 1, nand);
for (int j = 0; j < 16; j++) tmp[j] = data[15-j];
AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
@@ -787,11 +848,6 @@ bool LoadNAND()
ARM7Write32(dstaddr, *(u32*)&data[12]); dstaddr += 4;
}
- // repoint the CPUs to the boot2 binaries
-
- BootAddr[0] = bootparams[2];
- BootAddr[1] = bootparams[6];
-
#define printhex(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); printf("\n"); }
#define printhex_rev(str, size) { for (int z = (size)-1; z >= 0; z--) printf("%02X", (str)[z]); printf("\n"); }
@@ -800,18 +856,36 @@ bool LoadNAND()
printf("eMMC CID: "); printhex(eMMC_CID, 16);
printf("Console ID: %" PRIx64 "\n", ConsoleID);
- memset(ITCMInit, 0, 0x8000);
- memcpy(&ITCMInit[0x4400], &ARM9iBIOS[0x87F4], 0x400);
- memcpy(&ITCMInit[0x4800], &ARM9iBIOS[0x9920], 0x80);
- memcpy(&ITCMInit[0x4894], &ARM9iBIOS[0x99A0], 0x1048);
- memcpy(&ITCMInit[0x58DC], &ARM9iBIOS[0xA9E8], 0x1048);
+ u32 eaddr = 0x03FFE6E4;
+ ARM7Write32(eaddr+0x00, *(u32*)&eMMC_CID[0]);
+ ARM7Write32(eaddr+0x04, *(u32*)&eMMC_CID[4]);
+ ARM7Write32(eaddr+0x08, *(u32*)&eMMC_CID[8]);
+ ARM7Write32(eaddr+0x0C, *(u32*)&eMMC_CID[12]);
+ ARM7Write16(eaddr+0x2C, 0x0001);
+ ARM7Write16(eaddr+0x2E, 0x0001);
+ ARM7Write16(eaddr+0x3C, 0x0100);
+ ARM7Write16(eaddr+0x3E, 0x40E0);
+ ARM7Write16(eaddr+0x42, 0x0001);
+
+ memcpy(&NDS::ARM9->ITCM[0x4400], &ARM9iBIOS[0x87F4], 0x400);
+ memcpy(&NDS::ARM9->ITCM[0x4800], &ARM9iBIOS[0x9920], 0x80);
+ memcpy(&NDS::ARM9->ITCM[0x4894], &ARM9iBIOS[0x99A0], 0x1048);
+ memcpy(&NDS::ARM9->ITCM[0x58DC], &ARM9iBIOS[0xA9E8], 0x1048);
+ u8 ARM7Init[0x3C00];
memset(ARM7Init, 0, 0x3C00);
memcpy(&ARM7Init[0x0000], &ARM7iBIOS[0x8188], 0x200);
memcpy(&ARM7Init[0x0200], &ARM7iBIOS[0xB5D8], 0x40);
memcpy(&ARM7Init[0x0254], &ARM7iBIOS[0xC6D0], 0x1048);
memcpy(&ARM7Init[0x129C], &ARM7iBIOS[0xD718], 0x1048);
+ for (u32 i = 0; i < 0x3C00; i+=4)
+ ARM7Write32(0x03FFC400+i, *(u32*)&ARM7Init[i]);
+
+ // repoint the CPUs to the boot2 binaries
+ NDS::ARM9->JumpTo(bootparams[2]);
+ NDS::ARM7->JumpTo(bootparams[6]);
+
DSi_NAND::PatchUserData();
DSi_NAND::DeInit();
@@ -819,12 +893,6 @@ bool LoadNAND()
return true;
}
-void CloseDSiNAND()
-{
- if (DSi::SDMMCFile)
- fclose(DSi::SDMMCFile);
- DSi::SDMMCFile = nullptr;
-}
void RunNDMAs(u32 cpu)
{
@@ -1190,7 +1258,6 @@ u8 ARM9Read8(u32 addr)
switch (addr & 0xFF000000)
{
case 0x03000000:
- case 0x03800000:
if (SCFG_EXT[0] & (1 << 25))
{
if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0])
@@ -1218,6 +1285,9 @@ u8 ARM9Read8(u32 addr)
case 0x09000000:
case 0x0A000000:
return (NDS::ExMemCnt[0] & (1<<7)) ? 0 : 0xFF;
+
+ case 0x0C000000:
+ return *(u8*)&NDS::MainRAM[addr & NDS::MainRAMMask];
}
return NDS::ARM9Read8(addr);
@@ -1236,7 +1306,6 @@ u16 ARM9Read16(u32 addr)
switch (addr & 0xFF000000)
{
case 0x03000000:
- case 0x03800000:
if (SCFG_EXT[0] & (1 << 25))
{
if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0])
@@ -1264,6 +1333,9 @@ u16 ARM9Read16(u32 addr)
case 0x09000000:
case 0x0A000000:
return (NDS::ExMemCnt[0] & (1<<7)) ? 0 : 0xFFFF;
+
+ case 0x0C000000:
+ return *(u16*)&NDS::MainRAM[addr & NDS::MainRAMMask];
}
return NDS::ARM9Read16(addr);
@@ -1287,7 +1359,6 @@ u32 ARM9Read32(u32 addr)
break;
case 0x03000000:
- case 0x03800000:
if (SCFG_EXT[0] & (1 << 25))
{
if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0])
@@ -1315,6 +1386,9 @@ u32 ARM9Read32(u32 addr)
case 0x09000000:
case 0x0A000000:
return (NDS::ExMemCnt[0] & (1<<7)) ? 0 : 0xFFFFFFFF;
+
+ case 0x0C000000:
+ return *(u32*)&NDS::MainRAM[addr & NDS::MainRAMMask];
}
return NDS::ARM9Read32(addr);
@@ -1325,7 +1399,6 @@ void ARM9Write8(u32 addr, u8 val)
switch (addr & 0xFF000000)
{
case 0x03000000:
- case 0x03800000:
if (SCFG_EXT[0] & (1 << 25))
{
if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0])
@@ -1413,6 +1486,13 @@ void ARM9Write8(u32 addr, u8 val)
case 0x09000000:
case 0x0A000000:
return;
+
+ case 0x0C000000:
+#ifdef JIT_ENABLED
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
+#endif
+ *(u8*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
+ return;
}
return NDS::ARM9Write8(addr, val);
@@ -1423,7 +1503,6 @@ void ARM9Write16(u32 addr, u16 val)
switch (addr & 0xFF000000)
{
case 0x03000000:
- case 0x03800000:
if (SCFG_EXT[0] & (1 << 25))
{
if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0])
@@ -1497,6 +1576,13 @@ void ARM9Write16(u32 addr, u16 val)
case 0x09000000:
case 0x0A000000:
return;
+
+ case 0x0C000000:
+#ifdef JIT_ENABLED
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
+#endif
+ *(u16*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
+ return;
}
return NDS::ARM9Write16(addr, val);
@@ -1507,7 +1593,6 @@ void ARM9Write32(u32 addr, u32 val)
switch (addr & 0xFF000000)
{
case 0x03000000:
- case 0x03800000:
if (SCFG_EXT[0] & (1 << 25))
{
if (addr >= NWRAMStart[0][0] && addr < NWRAMEnd[0][0])
@@ -1581,6 +1666,13 @@ void ARM9Write32(u32 addr, u32 val)
case 0x09000000:
case 0x0A000000:
return;
+
+ case 0x0C000000:
+#ifdef JIT_ENABLED
+ ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
+#endif
+ *(u32*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
+ return;
}
return NDS::ARM9Write32(addr, val);
@@ -1591,6 +1683,7 @@ bool ARM9GetMemRegion(u32 addr, bool write, NDS::MemRegion* region)
switch (addr & 0xFF000000)
{
case 0x02000000:
+ case 0x0C000000:
region->Mem = NDS::MainRAM;
region->Mask = NDS::MainRAMMask;
return true;
@@ -1671,6 +1764,10 @@ u8 ARM7Read8(u32 addr)
case 0x0A000000:
case 0x0A800000:
return (NDS::ExMemCnt[0] & (1<<7)) ? 0xFF : 0;
+
+ case 0x0C000000:
+ case 0x0C800000:
+ return *(u8*)&NDS::MainRAM[addr & NDS::MainRAMMask];
}
return NDS::ARM7Read8(addr);
@@ -1724,6 +1821,10 @@ u16 ARM7Read16(u32 addr)
case 0x0A000000:
case 0x0A800000:
return (NDS::ExMemCnt[0] & (1<<7)) ? 0xFFFF : 0;
+
+ case 0x0C000000:
+ case 0x0C800000:
+ return *(u16*)&NDS::MainRAM[addr & NDS::MainRAMMask];
}
return NDS::ARM7Read16(addr);
@@ -1777,6 +1878,10 @@ u32 ARM7Read32(u32 addr)
case 0x0A000000:
case 0x0A800000:
return (NDS::ExMemCnt[0] & (1<<7)) ? 0xFFFFFFFF : 0;
+
+ case 0x0C000000:
+ case 0x0C800000:
+ return *(u32*)&NDS::MainRAM[addr & NDS::MainRAMMask];
}
return NDS::ARM7Read32(addr);
@@ -1864,6 +1969,14 @@ void ARM7Write8(u32 addr, u8 val)
case 0x0A000000:
case 0x0A800000:
return;
+
+ case 0x0C000000:
+ case 0x0C800000:
+#ifdef JIT_ENABLED
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
+#endif
+ *(u8*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
+ return;
}
return NDS::ARM7Write8(addr, val);
@@ -1951,6 +2064,14 @@ void ARM7Write16(u32 addr, u16 val)
case 0x0A000000:
case 0x0A800000:
return;
+
+ case 0x0C000000:
+ case 0x0C800000:
+#ifdef JIT_ENABLED
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
+#endif
+ *(u16*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
+ return;
}
return NDS::ARM7Write16(addr, val);
@@ -2038,6 +2159,14 @@ void ARM7Write32(u32 addr, u32 val)
case 0x0A000000:
case 0x0A800000:
return;
+
+ case 0x0C000000:
+ case 0x0C800000:
+#ifdef JIT_ENABLED
+ ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
+#endif
+ *(u32*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
+ return;
}
return NDS::ARM7Write32(addr, val);
@@ -2049,6 +2178,8 @@ bool ARM7GetMemRegion(u32 addr, bool write, NDS::MemRegion* region)
{
case 0x02000000:
case 0x02800000:
+ case 0x0C000000:
+ case 0x0C800000:
region->Mem = NDS::MainRAM;
region->Mask = NDS::MainRAMMask;
return true;
@@ -2107,7 +2238,7 @@ u8 ARM9IORead8(u32 addr)
if ((addr & 0xFFFFFF00) == 0x04004200)
{
if (!(SCFG_EXT[0] & (1<<17))) return 0;
- return DSi_Camera::Read8(addr);
+ return DSi_CamModule::Read8(addr);
}
if (addr >= 0x04004300 && addr <= 0x04004400)
@@ -2139,7 +2270,7 @@ u16 ARM9IORead16(u32 addr)
if ((addr & 0xFFFFFF00) == 0x04004200)
{
if (!(SCFG_EXT[0] & (1<<17))) return 0;
- return DSi_Camera::Read16(addr);
+ return DSi_CamModule::Read16(addr);
}
if (addr >= 0x04004300 && addr <= 0x04004400)
@@ -2201,7 +2332,7 @@ u32 ARM9IORead32(u32 addr)
if ((addr & 0xFFFFFF00) == 0x04004200)
{
if (!(SCFG_EXT[0] & (1<<17))) return 0;
- return DSi_Camera::Read32(addr);
+ return DSi_CamModule::Read32(addr);
}
return NDS::ARM9IORead32(addr);
@@ -2265,7 +2396,7 @@ void ARM9IOWrite8(u32 addr, u8 val)
if ((addr & 0xFFFFFF00) == 0x04004200)
{
if (!(SCFG_EXT[0] & (1<<17))) return;
- return DSi_Camera::Write8(addr, val);
+ return DSi_CamModule::Write8(addr, val);
}
if (addr >= 0x04004300 && addr <= 0x04004400)
@@ -2325,7 +2456,7 @@ void ARM9IOWrite16(u32 addr, u16 val)
if ((addr & 0xFFFFFF00) == 0x04004200)
{
if (!(SCFG_EXT[0] & (1<<17))) return;
- return DSi_Camera::Write16(addr, val);
+ return DSi_CamModule::Write16(addr, val);
}
if (addr >= 0x04004300 && addr <= 0x04004400)
@@ -2475,7 +2606,7 @@ void ARM9IOWrite32(u32 addr, u32 val)
if ((addr & 0xFFFFFF00) == 0x04004200)
{
if (!(SCFG_EXT[0] & (1<<17))) return;
- return DSi_Camera::Write32(addr, val);
+ return DSi_CamModule::Write32(addr, val);
}
return NDS::ARM9IOWrite32(addr, val);
@@ -2512,6 +2643,9 @@ u8 ARM7IORead8(u32 addr)
case 0x04004D06: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 48) & 0xFF;
case 0x04004D07: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID >> 56;
case 0x04004D08: return 0;
+
+ case 0x4004700: return DSi_DSP::SNDExCnt;
+ case 0x4004701: return DSi_DSP::SNDExCnt >> 8;
}
return NDS::ARM7IORead8(addr);
@@ -2544,6 +2678,8 @@ u16 ARM7IORead16(u32 addr)
case 0x04004D04: if (SCFG_BIOS & (1<<10)) return 0; return (ConsoleID >> 32) & 0xFFFF;
case 0x04004D06: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID >> 48;
case 0x04004D08: return 0;
+
+ case 0x4004700: return DSi_DSP::SNDExCnt;
}
if (addr >= 0x04004800 && addr < 0x04004A00)
@@ -2615,6 +2751,10 @@ u32 ARM7IORead32(u32 addr)
case 0x04004D00: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID & 0xFFFFFFFF;
case 0x04004D04: if (SCFG_BIOS & (1<<10)) return 0; return ConsoleID >> 32;
case 0x04004D08: return 0;
+
+ case 0x4004700:
+ printf("32-Bit SNDExCnt read? %08X\n", NDS::ARM7->R[15]);
+ return DSi_DSP::SNDExCnt;
}
if (addr >= 0x04004800 && addr < 0x04004A00)
@@ -2662,6 +2802,46 @@ void ARM7IOWrite8(u32 addr, u8 val)
case 0x04004500: DSi_I2C::WriteData(val); return;
case 0x04004501: DSi_I2C::WriteCnt(val); return;
+
+ case 0x4004700:
+ DSi_DSP::WriteSNDExCnt((u16)val | (DSi_DSP::SNDExCnt & 0xFF00));
+ return;
+ case 0x4004701:
+ DSi_DSP::WriteSNDExCnt(((u16)val << 8) | (DSi_DSP::SNDExCnt & 0x00FF));
+ return;
+ }
+
+ if (addr >= 0x04004420 && addr < 0x04004430)
+ {
+ u32 shift = (addr&3)*8;
+ addr -= 0x04004420;
+ addr &= ~3;
+ DSi_AES::WriteIV(addr, (u32)val << shift, 0xFF << shift);
+ return;
+ }
+ if (addr >= 0x04004430 && addr < 0x04004440)
+ {
+ u32 shift = (addr&3)*8;
+ addr -= 0x04004430;
+ addr &= ~3;
+ DSi_AES::WriteMAC(addr, (u32)val << shift, 0xFF << shift);
+ return;
+ }
+ if (addr >= 0x04004440 && addr < 0x04004500)
+ {
+ u32 shift = (addr&3)*8;
+ addr -= 0x04004440;
+ addr &= ~3;
+
+ int n = 0;
+ while (addr >= 0x30) { addr -= 0x30; n++; }
+
+ switch (addr >> 4)
+ {
+ case 0: DSi_AES::WriteKeyNormal(n, addr&0xF, (u32)val << shift, 0xFF << shift); return;
+ case 1: DSi_AES::WriteKeyX(n, addr&0xF, (u32)val << shift, 0xFF << shift); return;
+ case 2: DSi_AES::WriteKeyY(n, addr&0xF, (u32)val << shift, 0xFF << shift); return;
+ }
}
return NDS::ARM7IOWrite8(addr, val);
@@ -2693,12 +2873,51 @@ void ARM7IOWrite16(u32 addr, u16 val)
case 0x04004062:
if (!(SCFG_EXT[1] & (1 << 31))) /* no access to SCFG Registers if disabled*/
return;
- u32 tmp = MBK[0][8];
- tmp &= ~(0xffff << ((addr % 4) * 8));
- tmp |= (val << ((addr % 4) * 8));
- MBK[0][8] = tmp & 0x00FFFF0F;
- MBK[1][8] = MBK[0][8];
+ {
+ u32 tmp = MBK[0][8];
+ tmp &= ~(0xffff << ((addr % 4) * 8));
+ tmp |= (val << ((addr % 4) * 8));
+ MBK[0][8] = tmp & 0x00FFFF0F;
+ MBK[1][8] = MBK[0][8];
+ }
return;
+
+ case 0x4004700:
+ DSi_DSP::WriteSNDExCnt(val);
+ return;
+ }
+
+ if (addr >= 0x04004420 && addr < 0x04004430)
+ {
+ u32 shift = (addr&1)*16;
+ addr -= 0x04004420;
+ addr &= ~1;
+ DSi_AES::WriteIV(addr, (u32)val << shift, 0xFFFF << shift);
+ return;
+ }
+ if (addr >= 0x04004430 && addr < 0x04004440)
+ {
+ u32 shift = (addr&1)*16;
+ addr -= 0x04004430;
+ addr &= ~1;
+ DSi_AES::WriteMAC(addr, (u32)val << shift, 0xFFFF << shift);
+ return;
+ }
+ if (addr >= 0x04004440 && addr < 0x04004500)
+ {
+ u32 shift = (addr&1)*16;
+ addr -= 0x04004440;
+ addr &= ~1;
+
+ int n = 0;
+ while (addr >= 0x30) { addr -= 0x30; n++; }
+
+ switch (addr >> 4)
+ {
+ case 0: DSi_AES::WriteKeyNormal(n, addr&0xF, (u32)val << shift, 0xFFFF << shift); return;
+ case 1: DSi_AES::WriteKeyX(n, addr&0xF, (u32)val << shift, 0xFFFF << shift); return;
+ case 2: DSi_AES::WriteKeyY(n, addr&0xF, (u32)val << shift, 0xFFFF << shift); return;
+ }
}
if (addr >= 0x04004800 && addr < 0x04004A00)
@@ -2798,6 +3017,11 @@ void ARM7IOWrite32(u32 addr, u32 val)
case 0x04004400: DSi_AES::WriteCnt(val); return;
case 0x04004404: DSi_AES::WriteBlkCnt(val); return;
case 0x04004408: DSi_AES::WriteInputFIFO(val); return;
+
+ case 0x4004700:
+ printf("32-Bit SNDExCnt write? %08X %08X\n", val, NDS::ARM7->R[15]);
+ DSi_DSP::WriteSNDExCnt(val);
+ return;
}
if (addr >= 0x04004420 && addr < 0x04004430)