diff options
| -rw-r--r-- | src/ARM.cpp | 2 | ||||
| -rw-r--r-- | src/ARM.h | 2 | ||||
| -rw-r--r-- | src/CP15.cpp | 8 | ||||
| -rw-r--r-- | src/DSi.cpp | 38 | ||||
| -rw-r--r-- | src/NDS.cpp | 2 |
5 files changed, 48 insertions, 4 deletions
diff --git a/src/ARM.cpp b/src/ARM.cpp index 8530795..ecf94cd 100644 --- a/src/ARM.cpp +++ b/src/ARM.cpp @@ -80,7 +80,7 @@ ARM::~ARM() ARMv5::ARMv5() : ARM(0) { #ifndef JIT_ENABLED - DTCM = new u8[DTCMSize]; + DTCM = new u8[DTCMPhysicalSize]; #endif } @@ -57,7 +57,7 @@ public: } virtual void Execute() = 0; -#ifdef ENABLE_JIT +#ifdef JIT_ENABLED virtual void ExecuteJIT() = 0; #endif diff --git a/src/CP15.cpp b/src/CP15.cpp index 992c83f..6ac31aa 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -21,9 +21,11 @@ #include "NDS.h" #include "DSi.h" #include "ARM.h" + +#ifdef JIT_ENABLED #include "ARMJIT.h" #include "ARMJIT_Memory.h" - +#endif // access timing for cached regions // this would be an average between cache hits and cache misses @@ -105,7 +107,7 @@ void ARMv5::UpdateDTCMSetting() { newDTCMBase = DTCMSetting & 0xFFFFF000; newDTCMSize = 0x200 << ((DTCMSetting >> 1) & 0x1F); - //printf("DTCM [%08X] enabled at %08X, size %X\n", DTCMSetting, DTCMBase, DTCMSize); + //printf("DTCM [%08X] enabled at %08X, size %X\n", DTCMSetting, newDTCMBase, newDTCMSize); } else { @@ -115,7 +117,9 @@ void ARMv5::UpdateDTCMSetting() } if (newDTCMBase != DTCMBase || newDTCMSize != DTCMSize) { +#ifdef JIT_ENABLED ARMJIT_Memory::RemapDTCM(newDTCMBase, newDTCMSize); +#endif DTCMBase = newDTCMBase; DTCMSize = newDTCMSize; } diff --git a/src/DSi.cpp b/src/DSi.cpp index 97a63cd..839fdbf 100644 --- a/src/DSi.cpp +++ b/src/DSi.cpp @@ -540,7 +540,9 @@ void MapNWRAM_A(u32 num, u8 val) return; } +#ifdef JIT_ENABLED ARMJIT_Memory::RemapNWRAM(0); +#endif int mbkn = 0, mbks = 8*num; @@ -573,7 +575,9 @@ void MapNWRAM_B(u32 num, u8 val) return; } +#ifdef JIT_ENABLED ARMJIT_Memory::RemapNWRAM(1); +#endif int mbkn = 1+(num>>2), mbks = 8*(num&3); @@ -610,7 +614,9 @@ void MapNWRAM_C(u32 num, u8 val) return; } +#ifdef JIT_ENABLED ARMJIT_Memory::RemapNWRAM(2); +#endif int mbkn = 3+(num>>2), mbks = 8*(num&3); @@ -644,7 +650,9 @@ void MapNWRAMRange(u32 cpu, u32 num, u32 val) u32 oldval = MBK[cpu][5+num]; if (oldval == val) return; +#ifdef JIT_ENABLED ARMJIT_Memory::RemapNWRAM(num); +#endif MBK[cpu][5+num] = val; @@ -850,7 +858,9 @@ void ARM9Write8(u32 addr, u8 val) if (ptr) { *(u8*)&ptr[addr & 0xFFFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr); +#endif } return; } @@ -860,7 +870,9 @@ void ARM9Write8(u32 addr, u8 val) if (ptr) { *(u8*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr); +#endif } return; } @@ -870,7 +882,9 @@ void ARM9Write8(u32 addr, u8 val) if (ptr) { *(u8*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr); +#endif } return; } @@ -895,7 +909,9 @@ void ARM9Write16(u32 addr, u16 val) if (ptr) { *(u16*)&ptr[addr & 0xFFFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr); +#endif } return; } @@ -905,7 +921,9 @@ void ARM9Write16(u32 addr, u16 val) if (ptr) { *(u16*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr); +#endif } return; } @@ -915,7 +933,9 @@ void ARM9Write16(u32 addr, u16 val) if (ptr) { *(u16*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr); +#endif } return; } @@ -940,7 +960,9 @@ void ARM9Write32(u32 addr, u32 val) if (ptr) { *(u32*)&ptr[addr & 0xFFFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr); +#endif } return; } @@ -950,7 +972,9 @@ void ARM9Write32(u32 addr, u32 val) if (ptr) { *(u32*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr); +#endif } return; } @@ -960,7 +984,9 @@ void ARM9Write32(u32 addr, u32 val) if (ptr) { *(u32*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr); +#endif } return; } @@ -1196,7 +1222,9 @@ void ARM7Write16(u32 addr, u16 val) if (ptr) { *(u16*)&ptr[addr & 0xFFFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr); +#endif } return; } @@ -1206,7 +1234,9 @@ void ARM7Write16(u32 addr, u16 val) if (ptr) { *(u16*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr); +#endif } return; } @@ -1216,7 +1246,9 @@ void ARM7Write16(u32 addr, u16 val) if (ptr) { *(u16*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr); +#endif } return; } @@ -1241,7 +1273,9 @@ void ARM7Write32(u32 addr, u32 val) if (ptr) { *(u32*)&ptr[addr & 0xFFFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr); +#endif } return; } @@ -1251,7 +1285,9 @@ void ARM7Write32(u32 addr, u32 val) if (ptr) { *(u32*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr); +#endif } return; } @@ -1261,7 +1297,9 @@ void ARM7Write32(u32 addr, u32 val) if (ptr) { *(u32*)&ptr[addr & 0x7FFF] = val; +#ifdef JIT_ENABLED ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr); +#endif } return; } diff --git a/src/NDS.cpp b/src/NDS.cpp index 2ad6bad..18ae3e9 100644 --- a/src/NDS.cpp +++ b/src/NDS.cpp @@ -1137,7 +1137,9 @@ void MapSharedWRAM(u8 val) if (val == WRAMCnt) return; +#ifdef JIT_ENABLED ARMJIT_Memory::RemapSWRAM(); +#endif WRAMCnt = val; |